Hydrogen in amorphous Si and Ge during solid phase epitaxy

Studies into the effect of hydrogen on the kinetics of solid phase epitaxy (SPE) in amorphous Si (a-Si) and Ge (a-Ge) are presented. During SPE, H diffuses into surface amorphous layers from the surface and segregates at the crystalline-amorphous interface. Some of the H crosses the interface and diffuses into the crystalline material where it either leaves the sample or is trapped by defects. H segregation at concentrations up to 2.3 × 10²⁰ H/cm³ is observed in buried pha-Si layers with the SPE rate decreasing by up to 20%. H also results in a reduction of dopant-enhanced SPE rates and is used to explain the asymmetry effects between the SPE velocity profile and the dopant concentration profile observed with shallow dopant implants. Conversely, H diffusion is enhanced by dopants in a-Si. These studies suggest that H diffusion and SPE may be mediated by the same defect. The extent of H in-diffusion into a-Ge surface layers during SPE is about one order of magnitude less that that observed for a-Si layers. This is thought to be due to the lack of a stable surface oxide on a-Ge. However, a considerably greater retarding effect on the SPE rate in a-Ge of up to 70% is observed. A single unifying model is applied to both dopant-enhanced SPE and H diffusion processes.     

Electrical isolation of dislocations in Ge layers on Si(001) substrates through CMOS-compatible suspended structures

Abstract

Suspended crystalline Ge semiconductor structures are created on a Si(001) substrate by a combination of epitaxial growth and simple patterning from the front surface using anisotropic underetching. Geometric definition of the surface Ge layer gives access to a range of crystalline planes that have different etch resistance. The structures are aligned to avoid etch-resistive planes in making the suspended regions and to take advantage of these planes to retain the underlying Si to support the structures. The technique is demonstrated by forming suspended microwires, spiderwebs and van der Pauw cross structures. We finally report on the low-temperature electrical isolation of the undoped Ge layers. This novel isolation method increases the Ge resistivity to 280 Ω cm at 10 K, over two orders of magnitude above that of a bulk Ge on Si(001) layer, by removing material containing the underlying misfit dislocation network that otherwise provides the main source of electrical conduction.     

Electrical isolation of dislocations in Ge layers on Si(001) substrates through CMOS-compatible suspended structures

Suspended crystalline Ge semiconductor structures are created on a Si(001) substrate by a combination of epitaxial growth and simple patterning from the front surface using anisotropic underetching. Geometric definition of the surface Ge layer gives access to a range of crystalline planes that have different etch resistance. The structures are aligned to avoid etch-resistive planes in making the suspended regions and to take advantage of these planes to retain the underlying Si to support the structures. The technique is demonstrated by forming suspended microwires, spiderwebs and van der Pauw cross structures. We finally report on the low-temperature electrical isolation of the undoped Ge layers. This novel isolation method increases the Ge resistivity to 280 Ω cm at 10 K, over two orders of magnitude above that of a bulk Ge on Si(001) layer, by removing material containing the underlying misfit dislocation network that otherwise provides the main source of electrical conduction.     

Transport modulation in Ge/Si core/shell nanowires through controlled synthesis of doped Si shells

Appropriately controlling the properties of the Si shell in Ge/Si core/shell nanowires permits not only passivation of the Ge surface states, but also introduces new interface phenomena, thereby enabling novel nanoelectronics concepts. Here, we report a rational synthesis of Ge/Si core/shell nanowires with doped Si shells. We demonstrate that the morphology and thickness of Si shells can be controlled for different dopant types by tuning the growth parameters during synthesis. We also present distinctly different electrical characteristics that arise from nanowire field-effect transistors fabricated using the synthesized Ge/Si core/shell nanowires with different shell morphologies. Furthermore, a clear transition in the modification of device characteristics is observed for crystalline shell nanowires following removal of the shell using a unique trimming process of successive native oxide formation/etching. Our results demonstrate that the preferred transport path through the nanowire structure can be modulated by appropriately tuning the growth conditions.     

Semiconductor surface doping by electron beam melting of thin evaporated layers

We have studied the distribution profiles of Cu and Sb introduced into Si substrates, and Sb introduced into Ge substrates by electron beam melting of thin (～30nm) layers of the dopant evaporated onto the substrate. Surface evaporation of the dopant during melting was reduced by a cover layer of the substrate material evaporated on top. We propose a novel model which explains solute surface accumulation phenomena oberved in laser and electron beam surface melting experiments. It is based on a mechanism of solute immobilization at the very surface.     

Diffusion in Si(x)Ge(1-x)/Si nanowire heterostructures

Si0.48Ge0.52/Si tip/nanowire heterostructures were grown by pulsed laser vaporization (PLV) at a growth temperature of 1100 degrees C. Ge diffusion in [111]-growth Si nanowires was studied for different post-synthesis annealing temperatures from 200 degrees C to 800 degrees C. Ge composition profiles were quantified by energy-dispersive X-ray spectroscopy in a transmission electron microscope. The compositional profiles were modeled by a limited-source diffusion model to extract temperature-dependent diffusion coefficients. The Ge diffusion coefficients followed an Arrhenius relationship with an activation energy of 0.622 +/- 0.050 eV. This rather low activation energy barrier is similar to the previously reported activation energy barrier of 0.67 eV for Ge surface diffusion on Si, suggesting that surface diffusion may dominate in nanowires at this length scale.     

Transfer of physically-based models from process to device simulations: Application to advanced SOI MOSFETs

Dopant implantation, followed by spike annealing is one of the main focus areas in the simulation of silicon processing due to its ability to form highly-activated ultra-shallow junctions. Coupled with the growing interest in the use of silicon-on-insulator (SOI) wafers, modelling and simulation of the influence of SOI structure on damage evolution and ultra-shallow junction formation on one hand, and on electrical MOSFET device characteristics on the other hand, are required.In this work, physically-based models of dopant implantation and diffusion, including amorphization, defect interactions and evolution, as well as dopant-defect interactions in both bulk silicon and SOI are integrated within a unique simulation tool to model the different physical mechanisms involved in the process of ultra-shallow junction formation.The application to 65 nm SOI MOSFET devices demonstrated the strong impact of the process simulation models on the simulated electrical device characteristics, in particular for both defect evolution and defect dopant interaction with the additional silicon/buried oxide (Si/BOX) interface. Simulation results of the threshold voltage (V_th) and the variation of the on- and off-state currents of the explored structures are in good agreement with experimental data and can provide important insight for optimizing the process in both bulk silicon and SOI technologies.     

Investigations of diffusion kinetics in Si/Ta/Cu/W and Si/Co/Ta systems by secondary neutral mass spectrometry

Proper understanding of the degradation mechanisms and diffusion kinetics of copper and cobalt interconnections for advanced microelectronics is important from the point of view of fundamental research and technology as well. In this paper Si(substrate)/Ta(10 nm)/Cu(25 nm)/W(10 nm) and Si(substrate)/Co(150 nm)/Ta(10 nm) samples, prepared by DC magnetron sputtering, were in investigated. The samples were annealed at several temperatures ranging from 423 K to 823 K for various times. The composition distributions were detected by means of Secondary Neutral Mass Spectrometry (SNMS). Microstructural characterization of samples was carried out by means of Transmission Electron Microscopy (TEM). It is shown that the changes in the composition profiles were mainly caused by grain boundary, GB, diffusion and the effective GB diffusion coefficients of Ta in Cu were determined both by the “first appearance” and “centre-gradient” methods. The activation energy is 100 kJ/mol. The importance of the Ta penetration into the Cu and its accumulation at the Cu/W interface can lead to an increase of the Ta content in the copper film. This can be an important factor in the change/degradation of the physical parameters (e.g. the electrical resistance) of interconnects. Furthermore a Ta segregation factor in Cu was evaluated. Preliminary results in the Si(substrate)/Co(150 nm)/Ta(10 nm) indicate fast (GB) diffusion of the Si into the Co layer, formation of a cobalt silicide layer at the Co/Si interface and Si accumulation first at the Ta/Co interface and later a retarded accumulation at the free Ta surface.     

Investigations of diffusion kinetics in Si/Ta/Cu/W and Si/Co/Ta systems by secondary neutral mass spectrometry

Proper understanding of the degradation mechanisms and diffusion kinetics of copper and cobalt interconnections for advanced microelectronics is important from the point of view of fundamental research and technology as well. In this paper Si(substrate)/Ta(10 nm)/Cu(25 nm)/W(10 nm) and Si(substrate)/Co(150 nm)/Ta(10 nm) samples, prepared by DC magnetron sputtering, were in investigated. The samples were annealed at several temperatures ranging from 423 K to 823 K for various times. The composition distributions were detected by means of Secondary Neutral Mass Spectrometry (SNMS). Microstructural characterization of samples was carried out by means of Transmission Electron Microscopy (TEM). It is shown that the changes in the composition profiles were mainly caused by grain boundary, GB, diffusion and the effective GB diffusion coefficients of Ta in Cu were determined both by the “first appearance” and “centre-gradient” methods. The activation energy is 100 kJ/mol. The importance of the Ta penetration into the Cu and its accumulation at the Cu/W interface can lead to an increase of the Ta content in the copper film. This can be an important factor in the change/degradation of the physical parameters (e.g. the electrical resistance) of interconnects. Furthermore a Ta segregation factor in Cu was evaluated. Preliminary results in the Si(substrate)/Co(150 nm)/Ta(10 nm) indicate fast (GB) diffusion of the Si into the Co layer, formation of a cobalt silicide layer at the Co/Si interface and Si accumulation first at the Ta/Co interface and later a retarded accumulation at the free Ta surface.     

Epitaxy and Molecular Organization on Solid Substrates

The recent emergence of molecular films as candidates for functional electronic materials has prompted numerous investigations of the underlying mechanisms responsible for their structure and formation. This review describes the role of epitaxy in molecular organization on crystalline substrates. A much‐needed grammar of epitaxy is presented that classifies the various modes of epitaxy according to transformation matrices that relate the overlayer lattice to the substrate lattice. The different modes of epitaxy can be organized hierarchically to reflect the balance of overlayer–substrate and molecule–molecule energies. In the case of molecular overlayers, the mismatch of overlayer and substrate symmetries commonly leads to coincident epitaxy in which some of the overlayer lattice points do not reside on substrate lattice points. Analyses of numerous reported epitaxial molecular films reveal that coincidence is quite common even though, based on overlayer–substrate interface energies alone, not as energetically favorable as commensurism. The prevalence of coincidence can be attributed to overlayer elastic constants, associated with molecule–molecule interactions within the overlayer, that are larger than the elastic constants of the overlayer–substrate interface. This condition facilitates prediction of the epitaxial configuration and overlayer structure through simple and comparatively efficient geometric modeling that does not require the input of potential energies, while revealing the role of phase coherence between the overlayer and substrate lattices.     

A new understanding of near-threshold damage for 200 keV irradiation in silicon

Recently we reported room temperature point defect creation and subsequent extended defect nucleation in nitrogen-doped silicon during 200 kV electron irradiation, while identical irradiation of nitrogen-free silicon produced no effect. In this paper, first principles calculations are combined with new transmission electron microscope (TEM) observations to support a new model for elastic electron-silicon interactions in the TEM, which encompasses both nitrogen doped and nitrogen free silicon. Specifically, the nudged elastic band method was used to study the energetics along the diffusion path during an electron collision event in the vicinity of a nitrogen pair. It was found that the 0 K estimate for the energy barrier of a knock-on event is lowered from ∼ 12 to 6.2 eV. However, this is still inadequate to explain the observations. We therefore propose an increase in the energy barrier for Frenkel pair recombination associated with N₂-V bonding. Concerning pure silicon, stacking fault formation near irradiation-induced holes demonstrates the participation of bulk processes. In low oxygen float zone material, 2–5 nm voids were formed, while oxygen precipitation in Czochralski Si has been verified by electron energy-loss spectroscopy. Models of irradiation-induced point defect aggregation are presented and it is concluded that these must be bulk and not surface mediated phenomena.     

Amorphization, recrystallization and end of range defects in germanium

The controlled doping of germanium by ion implantation is a process which requires basic research before optimization. For this reason, we have experimentally studied by transmission electron microscopy both the kinetics of amorphization and of recrystallization of Ge during ion implantation (Ge, P and B) and further annealing. As in Si, the crystalline to amorphous phase transition occurs through the linear accumulation of damage with the dose until a certain threshold is reached above which the material turns amorphous. We show that the Critical Damage Energy Density (CDED) model can be used in germanium to predict the existence, position and extension of amorphous layers resulting from the implantation of ions for almost all mass/energy/dose combinations reported here and in the literature. During annealing, these amorphous layers recrystallize by solid-phase epitaxy following an Arrhenius-type law which we have determined. We observe that this regrowth results in the formation of extended defects of interstitial type. During annealing these defects evolve in size and density following an Ostwald ripening mechanism which becomes non-conservative (defects “evaporate”) as the temperature is increased to 600 °C. These results have important implications for the modeling of diffusion of implanted dopant in Ge. Transient diffusion may also exist in Ge, driven by an interstitial component usually not evidenced under equilibrium conditions.     

UHV/CVD生长锗硅材料的偏析现象

本文对利用超高真空CVD方法生长的Si1-xGex合金外延层中的锗表面分布情况和Ge在界面偏析现象进行了深入的研究.通过XPS和SIMS图谱的研究,指出表面由于锗的偏析,造成锗在体内和表面的含量不同,在低温时生长锗硅合金,表面氢原子的吸附可有效地抑制锗的偏析,但随着温度的升高,氢的脱附造成锗的偏析现象更加明显.     

Interstitial Pt in crystalline Si under thin (<12 nm) overlayers of Pt and PtSi

The Rutherford backscattering flux focusing effect is utilized to specifically detect interstitial Pt in Si. Measurements are performed on Si wafers after Pt evaporation at substrate temperatures of room temperature and 200 C, and for silicide formation after a subsequent 450 C anneal. We observe a high concentration, of the order of 3 at %, of interstitial Pt in crystalline Si for those conditions where Pt rapidly reacts with Si to form silicide. The interstitial Pt concentration is reduced when the suicide reaction is blocked in the metal film. We conclude that the high concentration of interstitial Pt in crystalline Si in the immediate (< 10nm) interface region to a metal or suicide overlayer may be crucial for the reaction of 3d transition metals with Si to form a suicide at low temperatures.     

Ion–solid interactions at the extremes of electronic energy loss: Examples for amorphous semiconductors and embedded nanostructures

A selection of ion–solid interactions in the swift heavy-ion irradiation regime is reviewed. We consider the effects of electronic energy loss at tens of keV/nm on both bulk material and nanostructures embedded in a matrix. Specific examples include ion track formation at low ion fluences in bulk Si and Ge and porous layer formation at high ion fluences in bulk Ge. In addition, the intriguing shape and phase transformations observable at high ion fluences in Ge and metallic nanoparticles embedded in bulk SiO₂ are examined and compared. Experiment, modelling and simulation are combined synergistically as we seek fundamental atomistic insight into these unique yet poorly understood processes operative only at the extremes of electronic energy loss.     

Orientation control of epitaxial Ge thin films growth on SrTiO3 (100) by ultrahigh vacuum sputtering

We report the orientation control of crystalline Ge (111) and Ge (001) growth on SrTiO₃ (100) substrate by adjusting the temperature of substrate. It is found that the substrate temperature plays an important role for the formation of crystalline Ge with different surface orientations and interfacial chemical configuration during the sputtering process. At 500 °C, Ge (111) with good crystalline quality is formed, while Ge (001) is preferably grown on SrTiO₃ substrate at 650 °C. Our results show the possibility of manipulating the surface orientations during Ge growth on SrTiO₃ by controlling the substrate temperatures.     

Composition and local strain mapping in Au-catalyzed axial Si/Ge nanowires

For most applications, heterostructures in nanowires (NWs) with lattice mismatched materials are required and promise certain advantages thanks to lateral strain relaxation. The formation of Si/Ge axial heterojunctions is a challenging task to obtain straight, defect free and extended NWs. And the control of the interface will determine the future device properties. This paper reports the growth and analysis of NWs consisting of an axial Si/Ge heterostructure grown by a vapor-liquid-solid process. The composition gradient and the strain distribution at the heterointerface were measured by advanced quantitative electron microscopy methods with a resolution at the nanometer scale. The transition from pure Ge to pure Si shows an exponential slope with a transition width of 21?nm for a NW diameter of 31?nm. Although diffuse, the heterointerface makes possible strain engineering along the axis of the NW. The interface is dislocation-free and a tensile out-of-plane strain is noticeable in the Ge section of the NW, indicating a lattice accommodation. Experimental results were compared to finite element calculations.     

On the characterisation of grown-in defects in Czochralski-grown Si and Ge

High yield processing of advanced integrated devices poses stringent demands on substrate and active device layer quality. Wafers have to be free of electrically active defects and should therefore be free of so called large pit defects and Crystal Originated Particles (COP’s) which can be formed during Czochralski (Cz) crystal growth. These COP’s are surface pits formed by large vacancy clusters and are observed by surface inspection tools based on light scattering as “particles”. They are formed by vacancy clustering during crystal growth. In Cz Si these defects can also be observed inside the bulk of the material by using infra red light scattering tomography and transmission electron microscopy. Recently similar defects were observed on polished Cz Ge wafers using optical and scanning electron microscopy and the same surface inspection tools as used for silicon wafers. In the present paper the characterisation of grown-in voids in Si and Ge using these various techniques is discussed. The observed void size-density distributions are compared with results of the simulation of vacancy incorporation and clustering during the Czochralski growth process.     

Charged point defects in semiconductors

Native point defects control many aspects of semiconductor behavior. Such defects can be electrically charged, both in the bulk and on the surface. This charging can affect numerous defect properties such as structure, thermal diffusion rates, trapping and recombination rates for electrons and holes, and luminescence quenching rates. Charging also introduces new phenomena such as nonthermally photostimulated diffusion, thereby offering distinctive mechanisms for defect engineering. The present work incorporates the first comprehensive account of semiconductor defect charging, identifying correspondences and contrasts between surfaces and the bulk as well as among semiconductor classes (group IV, groups III–V, and metal oxides). For example, small lattice parameters, close-packed unit cells, and basis atoms with large atomic radii all inhibit the formation of ionized interstitials and antisites. The charged defects that exist in III–V and oxide semiconductors can be predicted with surprising accuracy from the chemical potential and oxygen partial pressure of the ambient. The symmetry-lowering relaxations, formation energies, and diffusion mechanisms of bulk and surface defect structures often depend strongly on charge state with similar qualitative behavior, although for a given material surface defects do not typically take on the same configurations or range of stable charge states as their counterparts in the bulk.     

A combined chemical vapor deposition and rapid thermal diffusion process for SiGe Esaki diodes by ultra-shallow junction formation

SiGe Esaki diodes have been realized by rapid thermal diffusion of phosphorous into an SiGe layer grown by ultra-high-vacuum chemical-vapor-deposition on an Si p/sup +/-substrate for the first time. The phosphorous-doped SiGe forms the n/sup +/-electrode, while heavily boron-doped Si/sub 0.74/Ge/sub 0.26/ and Si substrate is used for the p/sup +/ electrode. The diodes show a peak current density of 0.18 kA/cm/sup 2/, a current peak-to-valley ratio of 2.6 at room temperature, and they exhibit only a weak temperature dependence. Cross-sectional transmission microscopy showed a good crystalline quality of the strained Si/sub 0.74/Ge/sub 0.26/ layer even after the diffusion step at 900/spl deg/C.