基于递归最小二乘支持向量机的动态系统建模研究

针对递归最小二乘支持向量机的递归性易导致建模中偏微分方程组求解困难的问题,提出用解析法求解偏微分方程组,实现了完整的递归最小二乘支持向量机模型．首先分析了各参数的相关性,然后推导出偏微分方程的解析表达式并求解．仿真实例表明,在动态系统建模中,该模型的性能比常用的串并联模型以及现有不完整递归最小二乘支持向量机模型的精度更高、性能更好．     

采用PETSc的有限元并行计算实现与优化

可移植可扩展科学计算工具箱PETSc提供了高性能求解偏微分方程组的大量对象和解法库,基于此进行结构有限元并行计算,可降低难度和成本。给出了基于PETS的结构有限元并行计算实现方法,包括有限元方程组的并行形成和并行求解的实现。根据PETSc的特点,提出了提高计算性能的优化措施,即数据局部化和存储预分配。数值实验表明实现方法可行,优化措施效果明显。     

一阶常微分方程组加速算法及数值仿真

针对一阶常微分方程组提出了一种数值加速算法,给出了该算法的误差分析,并将该加速算法应用于求解太阳帆航天器轨道运动方程组。该算法实现简单,计算量小,计算精度较高。     

块对角占优性与对称矩阵的块对角预条件

§1.引言 稀疏线性方程组的求解在科学计算与工程应用中非常重要。在材料模拟与设计、电磁场计算、计算流体力学和核爆数值模拟等领域中经常要求解微分方程,并通过有限元或有限差分与有限体积等方法进行离散,化为非线性方程组或稀疏线性方程组。非线性方程组的求解     

基于递归最小二乘支持向量机的动态系统建模研究

针对递归最小二乘支持向量机的递归性易导致建模中偏微分方程组求解困难的问题,提出用解析法求解偏微分方程组,实现了完整的递归最小二乘支持向量机模型．首先分析了各参数的相关性,然后推导出偏微分方程的解析表达式并求解．仿真实例表明,在动态系统建模中,该模型的性能比常用的串并联模型以及现有不完整递归最小二乘支持向量机模型的精度更高、性能更好．

     

pH型有机磷水解酶生物传感器的稳态模型

从分析pH型有机磷水解酶(OPH)生物传感器(简称OPH-pH型传感器)的工作原理出发,建立了描述稳态检测过程的扩散传质方程组,并根据方程组的特点将二阶微分方程组简化为二阶微分方程和非线性方程的求解,从而建立了OPH-pH型传感器的稳态模型。模型的计算结果给出了传感器性能的影响因素,可对传感器的设计提供一定的理论指导,自行制备的传感器实验结果与模型的计算结果基本吻合,验证了模型的正确性。     

FPGA架构上面向稀疏矩阵求解的静态调度算法

在电力系统仿真中,大型稀疏矩阵的求解会消耗大量存储和计算资源,未有效利用矩阵的稀疏性将导致存储空间浪费以及计算效率低下的问题。当前关于稀疏矩阵求解算法的研究主要针对众核加速硬件,聚焦于挖掘层次集合的并行度以提升算法的并行效率,而在众核处理器架构上频繁地进行缓存判断及细粒度访问可能导致潜在的性能问题。针对基于现场可编程门阵列（FPGA）的下三角稀疏矩阵求解问题,在吴志勇等设计的FPGA稀疏矩阵求解器硬件结构的基础上,提出一种静态调度求解算法。通过对稀疏矩阵进行预处理,设计数据分布和指令排布流程,将下三角稀疏矩阵的求解过程静态映射到多个FPGA片上的处理单元,以实现下三角稀疏矩阵在FPGA上的并行高速求解。将串行算法中所有的隐式并行关系排布到缓冲中,使得所有计算单元都能实现计算、访存和单元间通信的高效并行,从而最大限度地利用FPGA的硬件资源。典型算例上的测试结果表明,相较传统的CPU/GPU求解算法,该算法能够实现5~10倍的加速效果。     

基于FFT的泊松方程快速求解器的硬件实现

针对传统的泊松方程求解算法执行效率低、功耗大,很难满足实际需要的缺点,设计了一种FPGA硬件平台的泊松方程快速求解器。设计采用软件与硬件结合的方式,由软件执行控制复杂、计算量较小的任务,而由硬件完成控制简单、计算量大的任务,从而达到硬件加速的目的。在FPGA平台上,独立设计的FFT协处理器可以流水和高度并行化的处理数据,提高了求解器的性能。实验结果表明,硬件实现的基于FFT的泊松方程快速求解器具有较高的计算性能和良好的可扩展性。     

椭圓型偏微分方程的迭代解法

1.引言当某些椭圆型偏微分方程用差分方程组代替时,所得的线代数方程组可用迭代法求解。设平面区域G由简单闭曲线C包围,现要求在G中解椭圆型偏微分方程:     

工程计算中大型稀疏矩阵存储方法研究

在工程实际中,许多问题都可以归结为数值法求解偏微分方程(组)的问题.偏微分方程数值解法主要包括有限差分法、有限元法和有限体积法,其中大多数方法都是通过离散的方式将方程转化为线性方程组,通过求解线性系统得到原方程的数值解.在这个过程中,线性方程组的系数矩阵通常很大并且很稀疏,会占用大量存储空间并使方程组难以求解.针对这个问题,本文研究大型稀疏矩阵的压缩存储方法,只存储非零元素,降低存储空间消耗,避免零元素参与计算,提升计算效率.具体来说,在稀疏矩阵生成过程中,使用十字链表法存储,可以在常数时间内完成非零元素的插入操作;在方程组求解过程中,使用按行(列)压缩存储方法,既节约存储空间,又可以提高求解器的求解效率.在实验部分,本文分别使用有限差分法求解Laplace方程和有限元法计算圆环截面应力分布问题,对其中大型稀疏线性方程组的系数矩阵,采用十字链表法和按行(列)压缩存储法存储,使用直接法和迭代法求解线性方程组.实验结果显示,对于结构化和非结构化的稀疏矩阵,压缩存储方法不仅能够大幅度减少内存空间的占用,而且能够显著提升求解器的效率.     

基于FPGA的超声波信号处理设计与实现

为了满足超声波探伤检测的实时性需求,通过研究超声波探伤的工作原理,提出了基于FPGA芯片的实时信号处理系统实现方案及硬件结构设计,并根据FPGA逻辑结构模型实现了软件系统的模块化设计。根据实验测试及统计数据得出,基于FPGA芯片的信号处理系统提高了探伤检测的准确性与稳定性,满足了探伤过程中B超显示的实时性要求。     

基于Camera link的图像采集系统

介绍了一种基于FPGA和Camera link协议的图像采集系统设计方案。设计中将接口信号和图像数据转换为低压差分信号(LVDS)进行传输,提高了信号的精度和传输距离。阐述了具体的硬件接口电路设计以及接口信号程序设计,并给出了实验结果。     

Massively parallel acceleration of a document-similarity classifier to detect web attacks

This paper describes our approach to adapting a text document similarity classifier based on the Term Frequency Inverse Document Frequency (TFIDF) metric to two massively multi-core hardware platforms. The TFIDF classifier is used to detect web attacks in HTTP data. In our parallel hardware approaches, we design streaming, real time classifiers by simplifying the sequential algorithm and manipulating the classifier’s model to allow decision information to be represented compactly. Parallel implementations on the Tilera 64-core System on Chip and the Xilinx Virtex 5-LX FPGA are presented. For the Tilera, we employ a reduced state machine to recognize dictionary terms without requiring explicit tokenization, and achieve throughput of 37 MB/s at a slightly reduced accuracy. For the FPGA, we have developed a set of software tools to help automate the process of converting training data to synthesizable hardware and to provide a means of trading off between accuracy and resource utilization. The Xilinx Virtex 5-LX implementation requires 0.2% of the memory used by the original algorithm. At 166 MB/s (80X the software) the hardware implementation is able to achieve Gigabit network throughput at the same accuracy as the original algorithm.     

Evolvable Reasoning Hardware: Its Prototyping and Performance Evaluation

In this paper, we propose evolvable reasoning hardware and its design methodology. In the proposed design methodology, case databases of each reasoning task are transformed into truth tables, which are evolved to extract rules behind the past cases through a genetic algorithm. Circuits for the evolvable reasoning hardware are synthesized from the evolved truth-tables. Parallelism in each task can be embedded directly in the circuits through the direct hardware implementation of the case databases. We developed the evolvable reasoning hardware prototype using Xilinx Virtex FPGA chips and applied it to the English-pronunciation-reasoning (EPR) task. The evolvable reasoning hardware for the EPR task was implemented with 270K gates, achieving an extremely high reasoning speed of less than 300 ns/phoneme. It also achieved a reasoning accuracy of 82.1% which is almost the same accuracy as NETTalk in neural networks and MBRTalk in parallel AI.     

基于FPGA与ARM单片机的CAN总线分析仪设计

针对CAN总线网络通信质量分析、测试和验证的需要,论证了一种基于ARM单片机与FPGA完成的CAN总线分析仪设计;该分析仪采用集成的CAN控制器与专用总线电平采样双通道信息采集硬件结构;采用单片机及基于FPGA的专用电路完成对CAN网络的实时通信数据的收集与监控;采用PC机完成数据分析与参考信息显示;文章详细讨论了分析仪硬件的具体设计;分析了CAN总线通信波特率的自动检测、总线故障的检测与定位方法;最后结合软件设计给出了所设计的CAN总线分析仪的实测试验结果,可实现总线报文的正常监测、总线状态分析与错误检测功能。     

基于FPGA 的快速中频自动增益控制系统

为了同时满足系统的动态范围和响应时间的需要,提出了一种基于FPGA 的快速 中频自动增益控制( AGC) 系统。首先进行了计算机仿真,利用Quartus II 对系统AGC 算法进 行了仿真,验证了系统搭建控制模块、达到了60 dB 的动态范围控制。通过逻辑仿真软件的验 证和硬件电路的测试,证明系统响应迅速,控制精度高,并且系统用在实际的雷达接收机中取 得了良好的结果,增大了接收机的动态范围,提高了雷达系统的性能。     

Pipelined architecture for real-time cost-optimized extraction of visual primitives based on FPGAs

This paper presents an architecture for the extraction of visual primitives on chip: energy, orientation, disparity, and optical flow. This cost-optimized architecture processes in real time high-resolution images for real-life applications. In fact, we present a versatile architecture that may be customized for different performance requirements depending on the target application. In this case, dedicated hardware and its potential on-chip implementation on FPGA devices become an efficient solution. We have developed a multi-scale approach for the computation of the gradient-based primitives. Gradient-based methods are very popular in the literature because they provide a very competitive accuracy vs. efficiency trade-off. The hardware implementation of the system is performed using superscalar fine-grain pipelines to exploit the maximum degree of parallelism provided by the FPGA. The system reaches 350 and 270 VGA frames per second (fps) for the disparity and optical flow computations respectively in their mono-scale version and up to 32 fps for the multi-scale scheme extracting all the described features in parallel. In this work we also analyze the performance in accuracy and hardware resources of the proposed implementation.     

FPGA implementation of image processing technique for blood samples characterization

This work presents a hardware implementation of an image processing algorithm for blood type determination. The image processing technique proposed in this paper uses the appearance of agglutination to determine blood type by detecting edges and contrast within the agglutinated sample. An FPGA implementation and parallel processing algorithms are used in conjugation with image processing techniques to make this system reliable for the characterization of large numbers of blood samples. The program was developed using Matlab software then transferred and implemented on a Vertex 6 FPGA from Xilinx employing ISE software. Hardware implementation of the proposed algorithm on FPGA demonstrates a power consumption of 770 mW from a 2.5 V power supply. Blood type characterization using our FPGA implementation requires only 6.6 s, while a desktop computer-based algorithm with Matlab implementation on a Pentium 4 processor with a 3 GHz clock takes 90 s. The presented device is faster, more portable, less expensive, and consumes less power than conventional instruments. The proposed hardware solution achieved accuracy of 99.5% when tested with over 500 different blood samples.     

A system on chip for melanoma detection using FPGA-based SVM classifier

Support Vector Machine (SVM) is a robust machine learning model that shows high accuracy with different classification problems, and is widely used for various embedded applications. However, implementation of embedded SVM classifiers is challenging, due to the inherent complicated computations required. This motivates implementing the SVM on hardware platforms for achieving high performance computing at low cost and power consumption. Melanoma is the most aggressive form of skin cancer that increases the mortality rate. We aim to develop an optimized embedded SVM classifier dedicated for a low-cost handheld device for early detection of melanoma at the primary healthcare. In this paper, we propose a hardware/software co-design for implementing the SVM classifier onto FPGA to realize melanoma detection on a chip. The implemented SVM on a recent hybrid FPGA (Zynq) platform utilizing the modern UltraFast High-Level Synthesis design methodology achieves efficient melanoma classification on chip. The hardware implementation results demonstrate classification accuracy of 97.9%, and a significant hardware acceleration rate of 21 with only 3% resources utilization and 1.69 W for power consumption. These results show that the implemented system on chip meets crucial embedded system constraints of high performance and low resources utilization, power consumption, and cost, while achieving efficient classification with high classification accuracy.     

基于固件的系统芯片协同验证平台

使用FPGA进行全系统仿真是验证基于平台设计的系统芯片(SoC)的有效手段,但FPGA原型验证一方面须等待硬件设计完成编码,另一方面FPGA全系统环境下的硬件设计错误定位耗时,验证周期较长.为更早展开系统级验证工作并缩短验证周期,提出一种基于固件的协同验证平台-FCVP.FCVP在FPGA上基于固件模拟待测硬件设计和系...