Efficient Hardware/Software Implementation of an Adaptive Neuro-Fuzzy System

This paper describes the development of efficient hardware/software (HW/SW) neuro-fuzzy systems. The model used in this work consists of an adaptive neuro-fuzzy inference system modified for efficient HW/SW implementation. The design of two different on-chip approaches are presented: a high-performance parallel architecture for offline training and a pipelined architecture suitable for online parameter adaptation. Details of important aspects concerning the design of HW/SW solutions are given. The proposed architectures have been implemented using a system-on-a-programmable-chip. The device contains an embedded-processor core and a large field programmable gate array (FPGA). The processor provides flexibility and high precision to implement the learning algorithms, while the FPGA allows the development of high-speed inference architectures for real-time embedded applications.     

The image understanding architecture

This paper provides an overview of the Image Understanding Architecture (IUA), a massively parallel, multilevel system for supporting real-time image understanding applications and research in knowledge-based computer vision. The design of the IUA is motivated by considering the architectural requirements for integrated real-time vision in terms of the type of processing element, control of processing, and communication between processing elements.The IUA integrates parallel processors operating simultaneously at three levels of computational granularity in a tightly coupled architecture. Each level of the IUA is a parallel processor that is distinctly different from the other two levels, designed to best meet the processing needs at each of the corresponding levels of abstraction in the interpretation process. Communication between levels takes place via parallel data and control paths. The processing elements within each level can also communicate with each other in parallel, via a different mechanism at each level that is designed to meet the specific communication needs of each level of abstraction.An associative processing paradigm has been utilized as the principle control mechanism at the low and intermediate levels. It provides a simple yet general means of managing massive parallelism, through rapid responses to queries involving partial matches of processor memory to broadcast values. This has been enhanced with hardware operations that provide for global broadcast, local compare, Some/None response, responder count, and single responder select. To demonstrate how the IUA may be used for vision processing, several sample algorithms and a typical interpretation scenario on the IUA are presented.We believe that the IUA represents a major step toward the development of a proper combination of integrated processing power, communication, and control required for real-time computer vision. A proof-of-concept prototype of 1/64th of the IUA is currently being constructed by the University of Massachusetts and Hughes Research Laboratories.     

Application-controlled memory management in a single address space environment

With reference to a memory management system supporting the single address space abstraction and a uniform, persistent view of storage, we present a set of mechanisms that allow applications to exert explicit control over memory management activities. These mechanisms make it possible to move the contents of a virtual page to primary memory for fast processor access, or to push these contents back to secondary memory to free primary memory space. Our memory management scheme allows programs to exploit the memory reference pattern of the underlying algorithms, thereby improving utilisation of the system storage resources. This result is illustrated by using significant examples of memory management activities implemented at the application program level. Published online: 8 February 2001     

A road map to solid modeling

The objective of solid modeling is to represent, manipulate and reason about the 3D shape of solid physical objects by computer. Such representations should be unambiguous. Solid modeling's major application areas include design, manufacturing, computer vision, graphics and virtual reality. The field draws on diverse sources, including numerical analysis, symbolic algebraic computation, approximation theory, applied mathematics, point set topology, algebraic geometry, computational geometry and databases. In this article, we begin with some mathematical foundations of the field. We next review the major representation schemata of solids. Then, major layers of abstraction in a typical solid modeling system are characterized. The lowest level of abstraction comprises a substratum of basic service algorithms. At an intermediate level of abstraction there are algorithms for larger, more conceptual operations. Finally, a yet higher level of abstraction presents to the user a functional view that is typically targeted towards solid design. We look at some applications and at user interaction concepts. The classical design paradigms of solid modeling concentrated on obtaining one specific final shape. Those paradigms are becoming supplanted by feature-based, constraint-based design paradigms that are oriented more toward the design process and define classes of shape instances. These new paradigms venture into territory that has yet to be explored systematically. Concurrent with this paradigm shift, there is also a shift in the system architecture towards modularized confederations of plug-compatible functional components     

高职院校公共基础课程在线考试系统研究

把传统的人工考试流程进行分解,对用计算机实现在线考试系统的系统功能、关系型数据模型设计、组卷算法、网上考试和评分算法进行分析和研究,并建立相应的算法,为在线考试系统的软件设计和实现奠定理论基础.     

Extension Language Automation of Embedded System Debugging

Embedded systems contain several layers of target processing abstraction. These layers include electronic circuit, binary machine code, mnemonic assembly code, and high-level procedural and object-oriented abstractions. Physical and temporal constraints and artifacts within physically embedded systems make it impossible for software engineers to operate at a single layer of processor abstraction. The Luxdbg embedded system debugger exposes these layers to debugger users, and it adds an additional layer, the extension language layer, that allows users to extend both the debugger and its target processor capabilities. Tcl is Luxdbg's extension language. Luxdbg users can apply Tcl to automate interactive debugging steps, to redirect and to interconnect target processor input-output facilities, to schedule multiple processor execution, to log and to react to target processing exceptions, to automate target system testing, and to prototype new debugging features. Inclusion of an extension language like Tcl in a debugger promises additional advantages for distributed debugging, where debuggers can pass extension language expressions across computer networks.     

An efficient query optimization strategy for spatio-temporal queries in video databases

The interest for multimedia database management systems has grown rapidly due to the need for the storage of huge volumes of multimedia data in computer systems. An important building block of a multimedia database system is the query processor, and a query optimizer embedded to the query processor is needed to answer user queries efficiently. Query optimization problem has been widely studied for conventional database systems; however it is a new research area for multimedia database systems. Due to the differences in query processing strategies, query optimization techniques used in multimedia database systems are different from those used in traditional databases. In this paper, a query optimization strategy is proposed for processing spatio-temporal queries in video database systems. The proposed strategy includes reordering algorithms to be applied on query execution tree. The performance results obtained by testing the reordering algorithms on different query sets are also presented.     

一种网络测量中的时钟同步算法

包延迟跟踪在端到端性能分析和流量控制算法设计中是很重要的度量指标。论文介绍在延迟测量中评估和消除相对时钟误差的convexhulls法,这些算法能大大改善测量的准确性,可以在线和离线使用。     

Design of embedded dance teaching control system based on FPGA and motion recognition processing

The complex human activities, to the dance teaching, it has not been constrained, it is a difficult task for computer vision. Field-programmable gate array (FPGA) a classification of the movement of the Indian classical dance by using the powerful features of the built-in system tools. Human behavior recognition for this work, classical dance education in India from offline and live performance to the online control of material in the carried out of the guidance record of audio and dance, in. Another theme and 10 familiar dance of 200 m / bills have created, is the offline data of guidance form of a variety of classical dance in various postures. The data collection of a variety of topics. Or education attitude accounted for 60, Dance education in both cases. FPGA training and eight different sample size, will be performed by each of the multi-group object. The remaining two samples are tested, it has been trained on the FPGA. Different FPGA architecture design, and excellent recognition accuracy, because to get our test data. Compared to the same data set and of other classification model report, the recognition rate.     

互联网车险平台批量导入功能设计和实现

针对互联网车险"直销+网销"的过渡性发展模式,需要将线上线下保单统一管理。根据运营管理平台批量导入的需求模式,设计实现方案,完成了系统功能的开发和测试。整个功能涉及到运营管理平台与业务接口平台的对接、业务接口平台与保险公司接口的对接。系统的软件框架采用了SSM+Dubbo+Zookeeper,平台与平台间采用httpclient进行交互,且整个功能通过了所有的测试用例,并已上线使用。     

信息系统在防治新型冠状病毒的应用

为提高医院防治新型冠状病毒的信息化应急能力,提出基于信息系统的应急处理办法.依托计算机技术、互联网技术、5G技术快速构建线上应急诊疗专区,搭建门急诊分流限流管理平台,开展新冠患者远程会诊.实现慢病、特病、专病患者线上问诊、在线续方、药品配送到家的全流程应用,搭建了机构之间新冠患者远程会诊服务,调整了门诊放号算法,降低了线下就医人群交叉感染率.通过信息系统的应急响应措施,实现医院从线上到线下的疫情应急防治全覆盖,依托信息化手段采用分流、截流、导流快速助力疫情防控,增强了新型冠状病毒的防治效果.     

一款可编程语音处理器的设计与应用

为了提高通信系统的保密性,降低制造成本,需要进行专用处理器的设计.该文基于SELP(Sinusoidal Excitation Linear Prediction)算法模型原理,设计了一款高质量多速率语音专用处理器芯片.芯片使用可重构体系结构和超长指令字系统设计方法,将复杂度高的子程序进行优化,能够显著提高指令并行度.仿真结果表明:在该芯片上实现语音压缩编码算法,执行效率高于相同工艺水平的通用数字信号处理器,并保持原有编码质量.该处理器能够实现多种类型的语音压缩算法,使语音算法可以达到高保密性、低复杂度和易开发性.     

Integrating online and offline testing of a switching memory

A circuit used in a telephone switching unit features several test techniques, including BIST, partial scan, and boundary scan. By sharing the same circuitry for both online and offline testing, the design minimizes additional logic while achieving very high fault coverage     

基于NIOSⅡ软核处理器的嵌入式测试系统软硬件设计研究

介绍了利用NIOSⅡ软核处理器设计嵌入式测试系统的两类系统架构,详细讲述了基于NIOSⅡ软核处理器的嵌入式测试系统软硬件设计方法;最后结合EP2C8Q-208C8型FPGA芯片,利用Verilog语言描述A/D芯片的工作时序逻辑,利用NIOSⅡ软核处理器设计串口处理单元,将A/D采集的数据通过串口发送到计算机显示。实践表明,利用NIOS II软核处理器设计嵌入式测试系统,具有开发周期短,系统集成度高,功能灵活多样等特点,与传统利用单片机设计嵌入式测试系统相比,具有时钟频率高、运行速度快、调试方便等特点,是一种值得推广的嵌入式测试系统设计方法。     

A study of solution algorithms for shape design sensitivity analysis on a supermini computer with an attached array processor

This paper presents a study and comparison of shape design sensitivity analysis algorithms that are based on the continuum adjoint variable method, the continuum direct differentiation method, and the finite difference method, implemented on a supermini computer with an attached array processor. The basic algorithms and their differences in evaluating shape design sensitivity coefficients are outlined. A solution method for solving a system of equations, using a general sparse storage technique, is used for numerical implementation of shape design sensitivity analysis. It is found that computing shape design sensitivity coefficients using the direct differentiation method is significantly more efficient than using the adjoint variable method or the finite difference method. A detailed performance evaluation of the methods, using an attached array processor, is presented. The performance of the attached array processor, compared to a supermini computer is shown to depend strongly on the type of computations to be carried out. When only parts of a program are running on an attached array processor, the CPU time distribution among the different subroutines of the program can change significantly, compared to using the host processor only.     

A method of parallel-sequential detection of image features in computer vision systems

The paper is devoted to the problem of formalization of software-hardware solutions in designing real-time computer vision systems. The main attention is paid to the methods of implementation of low-level operations that find features (simple elements) in the image input to the system. Algorithmic types of detectors of simple elements in images are analyzed from the point of view of hardware organization in computer vision systems. In this connection, the necessary performance and memory resources are estimated. The capabilities of parallel and pipeline execution of detector algorithms are investigated. A method of using a field programmable gate array and a digital signal processor in solving the problem of image processing in real-time computer vision systems is considered in detail.     

Applying real-time interface and calculus for dynamic power management in hard real-time systems

Power dissipation has been an important design issue for a wide range of computer systems in the past decades. Dynamic power consumption due to signal switching activities and static power consumption due to leakage current are the two major sources of power consumption in a CMOS circuit. As CMOS technology advances towards deep sub-micron domain, static power dissipation is comparable to or even more than dynamic power dissipation. This article explores how to apply dynamic power management to reduce static power for hard real-time systems. We propose online algorithms that adaptively control the power mode of a system, procrastinating the processing of arrived events as late as possible. To cope with multiple event streams with different characteristics, we provide solutions for preemptive earliest-deadline-first and fixed-priority scheduling policies. By adopting a worst-case interval-based abstraction, our approach can not only tackle arbitrary event arrivals, e.g., with burstiness, but also guarantee hard real-time requirements with respect to both timing and backlog constraints. We also present extensive simulation results to demonstrate the effectiveness of our approaches.     

Reinforcement learning based computational adaptive optimal control and system identification for linear systems

The duality of estimation and control problems is a well known fact in control theory literature. Simultaneous parameter estimation while maintaining closed loop stability is a very difficult proposition and more so for unstable systems, even for linear systems. This typically motivates system identification to be performed only in offline experiments. Clearly, there is a need for a higher level abstraction for a control and identification scheme which acts in stages and prioritizes various aspects of the problem at each of these stages. The stage abstraction for the controller design in this paper is inspired by human intuition towards dealing with control and identification simultaneously and hence named “Intuitive Control Framework”. The first phase prioritizes stabilization of the system only. The controller moves onto the next phase after the unknown system is stabilized. The subsequent stages during this phase involve optimization with different performance metrics through adaptive learning. After enough information for identification is acquired, the control schemes developed for various optimal metrics are used to estimate the unknown parameters in the final phase. This narrative for selective prioritization of objectives and a higher level abstraction for control schemes is illustrated for a continuous linear time invariant state space realization with state feedback. Numerous real-world applications can benefit from this online system identification routine inspired by the human cognitive process. This offers a seamless integration of control and identification with a higher level of priorities. Such a framework is presented with explicit formulations for certain classes of dynamic systems, and evaluated with computer simulations as well as experimental results. An unstable multi-input multi-output linear system is used as an example to illustrate the approach.     

Levels of abstraction in designs of human–computer interaction: The case of e-mail

People process information at different levels of abstraction (e.g., talking about a topic in general terms and then going into the details). They move from one level to another but focus on a particular level at any specific moment. We see this behavior in the most common of tasks, such as solving problems, communicating and designing. This paper explores the implications of levels of abstraction on designing interactive systems. It demonstrates the idea by showing the feasibility and desirability of building a simple e-mail system based on the idea of levels of abstraction and testing its usability.We believe the implications of levels of abstraction on design are profound as regards the design of interactive systems that support dynamic behavior. Having shown the feasibility of some basic design implications, we call for empirical studies to test their usability and explore more advanced design implications.