代码缩减技术的研究

随着应用的深入，计算系统对性能的要求越来越高。另一方面，软件规模也越来越大，使得日益庞大的软件与有限的硬件资源之间的矛盾逐渐显现出来。在嵌入式系统、移动计算以及实时控制系统中，这个矛盾尤其突出。如何减少代码、提高代码的效率，成为近年来学术界和产业界关注的问题，许多组织和机构正围绕着此论题开展广泛而深入的研究。本文介绍代码缩减（code-size reduction）的研究背景，以及两种主要的代码缩减方法——代码压缩（code compression）和代码紧缩（code compaction）；着重讨论代码紧缩技术，包括：代码肾缩的主要方法、各个方法的特点及其中的关键技术；分析代码特缩技术尚存在的问题和面临的挑战，并对代码肾缩技术的未来发展趋势做了一些预测。     

基于代码压缩方法的低功耗嵌入式系统设计技术研究

低功耗是嵌入式系统设计中的重要约束条件之一．代码压缩能够减小程序目标代码尺寸，减小程序目标代码所占用的存储器空间和通信开销，从而在系统级上降低了系统功耗．本文对指令集裁剪压缩技术、全代码压缩与子代码压缩技术以及基于片上Cache的代码压缩技术等几种比较典型的代码压缩技术的特征进行了讨论和分析．     

安全通过方式--移动代码安全的新方法

根据ABLP信任逻辑提出了一种新的堆栈检测方式——安全通过方式，并以Java为例把此方法应用到移动代码系统中去。安全通过方式无须专门的硬件及语言执行时间的支持，在可信任代码和不可信任代码结合在一起运行时，它能够捕获两者之间的复杂关系，有效地解决移动代码的安全问题。     

基于代码检测的软件故障定位方法

针对现有软件故障定位方法的缺陷，提出了一种基于代码检测的软件故障定位方法，用嵌入式模块获取软件发生故障时的模块运行序列，分析出软件故障可疑模块集及其故障系数，在此基础上对故障模块进行代码的分类检测，根据上述过程中得到的结果进行综合分析运算，得出软件故障的可疑代码集和故障系数，采用代码分析辅助工具进行排查，定位故障。该方法已成功应用于软件密集型系统的故障诊断，能快速有效地实现软件故障定位。     

在嵌入式Java芯片中使用即时编译技术

Java虚拟机具有面向堆栈与面向对象的特点,不利于硬件有效支持字节码的直接执行,传统JIT也不适应嵌入式系统的应用环境,介绍了在自行设计的嵌入式Java芯片中使用JIT的技术途径,通过对Java虚拟机堆栈和复杂指令的支持,密切配合JIT软件,较好地解决了Java芯片设计中的问题。测试结果表明,相对于目前前界最好的picoJava-Ⅱ内核而言内核而言,JC401的编译后代码性能提高了1．2至1．9倍,在硬件复杂度、执行速度、内存开销等方面都有较大程度的改善,适合于嵌入式应用。     

堆栈处理器代码生成器的设计与实现

堆栈处理器是一种面向嵌入式控制领域的处理器,其执行过程不依赖于通用寄存器而是硬件堆栈。文中以一款基于FPGA设计的16位堆栈处理器为平台,研究如何将一个C源代码转换成能够被目标处理器汇编器识别的汇编指令。为了能够迅速有效地实现代码生成器,文中选用LCC。LCC是一款可变目标的C编译器,通过重新书写目标处理器的描述文件,LCC可以生成特定处理器的汇编指令。文章的最后通过一个简单的测试证明了C语言是可以移植到堆栈处理器上的。     

基于GCC的交叉编译器研究与开发

随着日前越来越多嵌入式系统的飞速发展，必须快速有效地为之开发合适的交叉编译器。因为GCC(GNU Compiler Collection)是非常优秀的交叉编译器而且具有很好的可移植性，所以移植GCC是一个非常正确的方法。以交叉编译系统ZLTCG的开发为背景，详细分析了交叉编译系统GCC的体系结构，对其高度可移植性所依赖的中间表示和机器描述技术进行了深入研究，并在此基础上阐述了如何基于GCC构造用于嵌入式系统开发的交叉编译器。介绍了GCC的内核和工作机制，特别是RTL(Register Transfer Language)代码和汇编代码的生成以及解释GCC的移植方法和移植实例，对测试方法进行了探讨。     

嵌入式Linux系统的引导过程及启动代码分析

在嵌入式系统开发中,启动代码的设计是系统开发的关键技术。结合嵌入式Linux系统的引导过程,重点分析了嵌入式系统中启动代码的设计方法,并对开源软件Uboot中启动部分代码进行了详细分析,从而为编写高效的启动代码提供参考,文中代码可在基于ARM7的系统上运行。     

用代码缓存复用技术提升Android即时编译器效率

选择性编译能降低程序编译开销和生成代码的存储空间需求,但面临热方法检测延时和编译延时问题.现有降低这些延时的方法因需要复杂数据结构、算法或特殊硬件的支持而不适合嵌入式虚拟机平台.针对嵌入式平台,提出使用将可执行代码缓存至文件并按需复用的方法来降低这两种延时.为此,本文以Android系统虚拟机的即时编译器为基础,设计实现了轻量级的CCARF(Code Cache and Reuse Framework).CCARF为即时编译器设计了位置无关代码生成算法,使编译生成的代码不合位置依赖信息,从而保证代码可被正确复用;基于该算法,CCARF实现了一个代码管理器,高效地将位置无关代码缓存并复用.SPECjvm98基准测试集的测试结果表明,CCARF能在控制生成代码增长的前提下,平均提升基准测试程序性能约11％.     

ARM处理器启动代码的分析与编程

优秀的启动代码的编写可以保证程序的稳定高效运行.首先介绍了ARM（Advanced RISC Machines）启动代码中中断向量表的定义、堆栈初始化、系统硬件初始化,然后重点分析了分散加载的目的与实现.虽然是针对LPC2210芯片,却可以推广到一般ARM7嵌入式系统的启动代码的分析与设计中去.     

基于嵌入式SIMD处理器的音频解码优化

嵌入式处理器越来越多地采用SIMD并行架构来提升其媒体处理能力,该文提出基于该架构的优化流程,采用算法和处理器架构紧密结合的优化原则,利用现有编译器来降低汇编编程工作量,对算法关键部分采用手工编程来确保优化效率。该流程被应用在基于XScale平台的MP3解码优化中,短时间内将解码效率提高60%,接近IPP库的性能。     

Customized pipeline and instruction set architecture for embedded processing engines

Custom instructions potentially improve execution speed and code compression of embedded applications. However, more efficient custom instructions need higher number of simultaneous registerfile accesses. Larger registerfiles are more power hungry with complex forwarding interconnects. Therefore, due to the limited ports of the base processor registerfile, size and efficiency of custom instructions could be generally limited. Recent researches have focused on overcoming this limitation by some innovative architectural techniques supplemented with customized compilations. However, to the best of our knowledge there are few researches that take into account the complete pipeline design and implementation considerations. This paper proposes a customized instruction set and pipeline architecture for an optimized embedded engine. The proposed architecture increases the performance by enhancing the available registerfile data bandwidth through register access pipelining. The achieved improvements are made by introducing double-word custom instructions whose registerfile accesses are overlapped in the pipeline. Potential hazards in such instructions are resolved by the introduced pipeline backwarding concept, yielding higher performance and code compression. While we study the effectiveness of the proposed architecture on domain-specific workloads from packet-processing benchmarks, the developed framework and architecture are applicable to other embedded application domains.     

Dictionary-based program compression on customizable processor architectures

The size of the program code has become a critical design constraint in embedded systems, especially in handheld devices. Large program codes require large memories, which increase the size and cost of the chip. In addition, the power consumption is increased due to higher memory I/O bandwidth. Program compression is one of the most often used methods to reduce the size of the program code. In this paper, dictionary-based program compression is evaluated on a customizable processor architecture with parallel resources. In addition to code density, the effectiveness of the method is evaluated in terms of area and power consumption. Furthermore, a mechanism is proposed to maintain the programmability after compression. Up to 77% reduction in area and 73% reduction in power consumption of the program memory and the associated control logic were obtained.     

基于交替-连续长度码的测试数据编码方法

为了减少测试数据量,提出基于交替-连续长度码的测试数据编码方法。采用变长-变长的编码方式,直接编码测试集中连续-交替的长度码。实验结果表明,该方法的解压结构是一个简单的有限状态机,所需额外硬件开销小,与同类型的编码方法相比,具有更高的测试数据压缩率。     

嵌入式系统软硬件协同验证中软件验证方法

随着集成电路及计算机技术的发展,嵌入式系统设计变得越来越复杂．复杂的嵌入式系统设计,通常采用验证的手段检验系统设计的正确性,硬件验证通常是在硬件设计描述的基础上建立用于模拟硬件功能的硬件模拟器;软件验证常用的方法是建立处理器功能模型(指令集模拟器ISS),逐条解释嵌入式软件在目标机器上的执行过程,产生模拟输出,驱动外围电路(即硬件设计)．指令集模拟器从底层时序关系模拟嵌入式软件在目标CPU上运行过程．对于复杂嵌入式系统设计,ISS模拟速度通常成为协同模拟瓶颈．基于RTOS的嵌入式软件快速验证方法可以有效地提高软件模拟速度,扩展RTOS功能,适应协同模拟需要,建立硬件模拟驱动,实现软件和硬件模拟器通信连接和协同模拟同步控制．基于RTOS的嵌入式软件验证方法以编译代码模型为基础,从系统行为级验证嵌入式软件功能,验证速度快．在实际应用中,该方法和ISS验证相结合,能够实现更有效、更快速的嵌入式系统协同验证．最后以几个典型硬件设计为基础,编写相应的控制软件,进行软硬件协同验证实验,实验结果数据说明该验证方法实用、有效、快速．     

Computation in the Context of Transport Triggered Architectures

Processors used in embedded systems have specific requirements which are not always met by off-the-shelf processors. A templated processor architecture, which can easily be tuned towards a certain application (domain) offers a solution. The transport triggered architecture (TTA) template presented in this paper has a number of properties that make it very suitable for embedded system design. Key to its success is to give the compiler more control; it has to schedule all data transports within the processor. This paper highlights two important TTA-related issues. First a new code generation method for TTAs is discussed; it integrates scheduling and register allocation, thereby avoiding the notorious phase ordering problem between these two steps. Secondly, we discuss how to tune the instruction repertoire for an embedded processor. A tool is described which automatically detects frequent patterns of operations. These patterns can then be implemented on special function units.     

基于.NET平台采用ADO.NET实现数据访问层

目前传统的Web应用程序访问数据库的方法是SQL代码嵌入在domain/business类中,一旦系统出现改动,就要修改源代码。目前比较通用的方法是SQL代码写在独立的一个或多个数据类中或在存储过程中,这种方法能压缩源代码。提出了通用数据类的概念。采用通用数据类,使程序开发人员摆脱开SQL和事务,达到了快速开发的目的。利用ADO.NET和XML技术实现了数据访问层的思想,并实现了事务集中处理。     

Effects of program compression

The size of the program code has become a critical design constraint in embedded systems, especially in handheld, battery operated devices. Large program codes require large memories, which increase the size and cost of the chip. In addition, the power consumption is increased due to higher memory I/O bandwidth. Program compression is one of the most often used methods to reduce the size of the program code. In this paper, two compression approaches, dictionary-based compression and instruction template-based compression, were evaluated on a customizable processor architecture with parallel resources. The effects on area and power consumption were measured. Dictionary-based compression reduced the area at best by 77% and power consumption by 73%. Instruction template-based compression resulted in increase in both area and power consumption and hence turned out to be impractical.     

Variable Length Instruction Compression on Transport Triggered Architectures

The memories used for embedded microprocessor devices consume a large portion of the system’s power. The power dissipation of the instruction memory can be reduced by using code compression methods, which may require the use of variable length instruction formats in the processor. The power-efficient design of variable length instruction fetch and decode is challenging for static multiple-issue processors, which aim for low power consumption on embedded platforms. The memory-side power savings using compression are easily lost on inefficient fetch unit design. We propose an implementation for instruction template-based compression and two instruction fetch alternatives for variable length instruction encoding on transport triggered architecture, a static multiple-issue exposed data path architecture. With applications from the CHStone benchmark suite, the compression approach reaches an average compression ratio of 44% at best. We show that the variable length fetch designs reduce the number of memory accesses and often allow the use of a smaller memory component. The proposed compression scheme reduced the energy consumption of synthesized benchmark processors by 15% and area by 33% on average.     

AADL模型代码自动生成技术研究*

随着嵌入式系统在安全关键领域的广泛应用,必须采用现代软件工程的技术进一步提高其可信性,以保证人们的生命安全。基于模型驱动方法,对AADL（体系结构分析设计语言）模型的框架代码自动生成技术进行了研究,提出了从AADL模型元素到C和Ada的语法元素的映射规则,由此实现了自动代码生成器generator并集成在开源工具OSATE中。最后通过一个实例,说明将AADL模型自动转换为框架代码后与模块代码结合的有效性。