Top-Down Layout for Hierarchical Custom Design

Champ, a chip floor-plan program, and Alpha, an automatic cell placement and routing system, provide a method for hierarchical custom VLSI design that is highly automated and completely top-down. The system can handle standard cell blocks as well as macro cells such as RAMs, ROMs, PLAs. Champ consists of initial block placement and block packing Designers can execute initial block placement either manually or automatically using a method based on attractive-repulsive forces. Block packing is performed automatically or interactively through the moving and reshaping of blocks, which is done as the chip boundaries are being shrunk. Following the floor-plan design, Alpha automatically executes cell placement and routing. Using Champ/Alpha, only seven mandays are needed to design a 20,000-gate VLSI layout, using a predesigned standard cell library and predesigned macro cells.     

A Fully-Automated Electron Beam Test System for VLSI Circuits

A fully automated, stroboscopic electrobeam test system that analyzes the behavior of logic VLSI circuits, this system consists of a stroboscopic electron-beam tester combined with an LSI CAD system. LSI circuit design data, read from the CAD system, provides a designed map. The host computer performs interconnection pattern recognition by superimposing this map onto an observed stroboscopic SEM image. Then, once the circuit nodes for voltage waveform measurements are automatically determined on the superimposed map. Next, the electron beam is positioned on the actual circuit-under-test wires. These automatic processes result in measured waveforms, which are displayed on the host computer terminal. This system has been applied to a 2.3K-gate logic LSI circuits, and has been successful in locating the critical path. This system, coupled with the recently developed fault diagnostic electron-beam tester, Finder, constitutes a unified electron-beam test system.     

LORES-2: A Logic Reorganization System

LORES-2 is a logic reorganization system which greatly contributes to the effective automation of logic design. LORES-2 uses a macro-expansion technique to help designers transform printed-circuit assembly logic composed of SSI and MSI circuits into master-slice LSI logic circuits. The number of gates of the most reorganized LSI circuit falls within ± 20 percent of the number of gates of the original circuit. When ROMS and/or PLAs are not-allowed on the target LSI circuit, those elements are converted into optimized, multilevel random logic using logic minimization, factoring and macro-expansion techniques.     

Computer Aided Design for Large-Scale Integrated Circuits

The complexity of integrated circuits has increased steadily over the past several years from circuits consisting of simple gates through Medium Scale Integration (MSI) and Large Scale Integration (LSI). Fabrication techniques for LSI have evolved from well-established integrated circuit technology. Because of the large physical size and the large number of components on the individual silicon die, production techniques have been substantially improved in order to maintain reasonable yields. However, the most significant effects of LSI on the semiconductor manufacturer are in the areas of design and testing; techniques used in the past for simpler integrated circuits are inadequate for LSI.     

A methodology for custom VLSI layout

In this paper, we present a new methodology for custom VLSI layout which aims at a low turnaround time and a high quality of design. VLSI circuits are highly complex, and to speed up the design process we exploit the hierarchical structure of a design, splitting the problem domain into several levels. The process of layout at each level is divided into steps such as placement of rectangular blocks, determining block dimensions, determining interconnection paths, etc. In order to obtain high quailty, designs, we have systematically analyzed the relationship among the parameters being computed at various steps and have accordingly organized the flow of data and control through these steps. There are two novel features in our scheme. First, we do not follow the usual pure top-down or pure bottom-up approach, so as to take into account the influence of design decisions at the higher levels on design decisions made at the lower levels, as well as vice versa. For example, we determine the geometry, of a block taking into consideration the context in which it is placed, as well as the geometries of the lower level blocks it encloses. Second, we perform a look-ahead operation when the values of some parameters are needed before they are actually deterministically computable by the process. For example, at the time of placement, the area required for routing is estimated statistically (before doing the actual routing) so that a more routable placement can be obtained, thereby avoiding some unnecessary iterations.     

Analog nonlinear function synthesis

Describes a resistive network combining constant and controlled resistors, as well as its implementation with MOS transistors. This circuit synthesizes nonlinear functions of several variables. We can consider it an implementation of fuzzy rules, since its constituents serve as membership functions, fuzzy logic gates, and center-of-gravity defuzzification circuits. Alternatively, we can consider it a lookup table with interpolation, since fuzzy rules and lookup table entries act alike. Its single generic circuit structure lets us synthesize a number of different nonlinear functions by customizing geometric parameters or connection patterns. This simple, stable, low-power circuit supports microsensor-microactuator interfacing and management. Its straightforward design reduces custom IC design costs     

深亚微米CMOS电路漏电流快速模拟器

随着工艺的发展 ,功耗成为大规模集成电路设计领域中一个关键性问题 降低电源电压是减少电路动态功耗的一种十分有效的方法 ,但为了保证系统性能 ,必须相应地降低电路器件的阈值电压 ,而这样又将导致静态功耗呈指数形式增长 ,进入深亚微米工艺后 ,漏电功耗已经能和动态功耗相抗衡 ,因此 ,漏电功耗快速模拟器和低功耗低漏电技术一样变得十分紧迫 诸如HSPICE的精确模拟器可以准确估计漏电功耗 ,但仅仅适合于小规模电路 首先证实了CMOS晶体管和基本逻辑门都存在堆栈效应 ,然后提出了快速模拟器的漏电模型 ,最后通过对ISCAS85& 89基准电路的实验 ,说明了在精度许可 (误差不超过 3% )的前提下 ,模拟器获得了成百倍的加速 ,同时也解决了精确模拟器的内存爆炸问题     

Design of reversible logic based full adder in current-mode logic circuits

Demand of Very Large Scale Integration (VLSI) circuits with very high speed and low power are increased due to communication system's transmission speed increase. During computation, heat is dissipated by a traditional binary logic or logic gates. There will be one or more input and only one output in irreversible gates. Input cannot be reconstructed using those outputs. In low power VLSI, reversible logic is commonly preferred in recent days. Information is not lost in reversible gates and back computation is possible in reversible circuits with reduced power dissipation. Reversible full adder circuits are implemented in the previous work to optimize the design and speed of the circuits. Reversible logic gates like TSG, Peres, Feynman, Toffoli, Fredkin are mostly used for designing reversible circuits. However it does not produced a satisfactory result in terms of static power dissipation. In this proposed research work, reversible logic is implemented in the full adder of MOS Current-Mode Logic (MCML) to achieve high speed circuit design with reduced power consumption. In VLSI circuits, reliable performance and high speed operation is exhibited by a MCML when compared with CMOS logic family. Area and better power consumption can be produced implementing reversible logic in full adder of MCML. Minimum garbage output and constant inputs are used in reversible full adder. The experimental results shows that the proposed designed circuit achieves better performance compared with the existing reversible logic circuits such as Feynman gate based FA, Peres gate based FA, TSG based FA in terms of average power, static power dissipation, static current and area.     

FUZZY LOGIC FOR STANDARD CELL PLACEMENT

Improved manufacturing processes and techniques have increased the level of integration and complexity of the ubiquitous silicon chip. But as design complexity grows, physical design automation becomes indispensable. At present a variety of tools are available to assist the designer in the various phases of circuit design. Tools for automatic placement of VLSI cells, in particular, have received much attention, because good placement is a key factor in achieving the demanded performance levels. In this paper, we present a new technique based on fuzzy logic for the placement of double-entry standard cells. Fuzzy logic offers a better alternative for handling uncertainty, and it models the human operator rather than the operation. Simulation results for the placement of nine test circuits are presented and compared with those of two other techniques.     

A lower cost graphics system for VLSI design,design rule checking and pattern generation

Increasing interest by traditional systems houses in the design of custom and semi-custom integrated circuits (LSI and VLSI) provided the impetus for the development of a lower cost interactive graphics systems (IGS) for VLSI design, design verification, and the efficient generation of optical pattern generation and electron beam control files.While extremely attractive, but expensive, IGS units are available from such manufactures as Applicon and Calma for use in very large design groups, it was felt that a lower cost system incorporating the latest in design aids was needed for smaller or geographically dispersed design operations. This paper describes the implementation of one such system, and examines the various implementation options which must be examined by any group which might wish to build or acquire such a capability.     

性能驱动总体布线的关键技术及研究进展

在计算机软件领域,超大规模集成电路技术的迅猛发展迫切需要高性能CAD工具——电子设计自动化(EDA)软件工具的支持.与物理设计相关的CAD技术称为布图设计,总体布线是布图设计中一个极为重要的环节.目前,在深亚微米、超深亚微米工艺下的超大规模、甚大规模集成电路设计中,性能驱动总体布线算法已成为布图设计中的一个国际研究热点.针对这一热点,分析了性能驱动总体布线算法研究中亟待解决的关键技术,并详细阐述了国内外的重要相关研究工作进展情况.     

The new DFM approach based on a genetic algorithm

As scaling has continued for more than 20 years, it has yielded faster and denser chips with ever increasing functionality. With recent advances in technology, the number of transistors mounted on a VLSI chip is about 10 million gates. In such advanced technology, device feature sizes have become increasingly smaller than the wavelength of light used by the available optical lithography equipment. Therefore, a design for manufacturability (DFM) approach has become the most important factor in the design of LSI. In this article, we propose a new DFM approach as the target for the next generation in the layout design phase. Simulation results evaluating the proposed algorithm show good performance. This work was presented in part at the 11th International Symposium on Artificial Life and Robotics, Oita, Japan, January 23–25, 2006     

Timing Accuracy in Modern ATE

LSI test systems built in the 1970s had compact, 60-pin test heads that presented devices under test with open wires leading to lumped-capacitive loads. Today's VLSI testers have 256-pin test heads with transmission lines leading from the DUTs to driver-comparator circuits that are as far away as 50 cm. Even though these automatic testers are adjusted to subnanosecond accuracy, reflections within the transmission lines can cause timing measurement errors up to 10 ns for MOS devices whose output impedances are not matched to the transmission lines. The authors offer the Advice circuit simulator (an AT&T proprietary version of SPICE) as one way to analyze errors due to transmission line problems before testing. They also discuss ways to correct timing errors. Finally, they recommend that very high speed ICs be designed to drive transmission lines that are terminated with matched resistors at the comparators.     

Large-scale nonlinear optimization in circuit tuning

Circuit tuning is an important task in the design of custom digital integrated circuits such as high-performance microprocessors. The goal is to improve certain aspects of the circuit, such as speed, area, or power, by optimally choosing the widths of the transistors. This task can be formulated as a large-scale nonlinear, nonconvex optimization problem, where function values and derivatives are obtained by simulation of individual gates. This application offers an excellent example of a nonlinear optimization problem, for which it is very desirable to increase the size of the problems that can be solved in a reasonable amount of time. In this paper we describe the mathematical formulation of this problem and the implementation of a circuit tuning tool. We demonstrate how the integration of a novel state-of-the-art interior point algorithm for nonlinear programming led to considerable improvement in efficiency and robustness. Particularly, as will be demonstrated with numerical results, the new approach has great potential for parallel and distributed computing.     

Novel designs of nanometric parity preserving reversible compressor

Reversible logic is a new field of study that has applications in optical information processing, low power CMOS design, DNA computing, bioinformatics, and nanotechnology. Low power consumption is a basic issue in VLSI circuits today. To prevent the distribution of errors in the quantum circuit, the reversible logic gates must be converted into fault-tolerant quantum operations. Parity preserving is used to realize fault tolerant in this circuits. This paper proposes a new parity preserving reversible gate. We named it NPPG gate. The most significant aspect of the NPPG gate is that it can be used to produce parity preserving reversible full adder circuit. The proposed parity preserving reversible full adder using NPPG gate is more efficient than the existing designs in term of quantum cost and it is optimized in terms of number of constant inputs and garbage outputs. Compressors are of importance in VLSI and digital signal processing applications. Effective VLSI compressors reduce the impact of carry propagation of arithmetic operations. They are built from the full adder blocks. We also proposed three new approaches of parity preservation reversible 4:2 compressor circuits. The third design is better than the previous two in terms of evaluation parameters. The important contributions have been made in the literature toward the design of reversible 4:2 compressor circuits; however, there are not efforts toward the design of parity preservation reversible 4:2 compressor circuits. All the scales are in the nanometric criteria.     

Designing Digital Systems? SSI And MSI Vs. LSI And VLSI

Digital system design with LSI and VLSI circuits can be better understood and performed if one can define an implementation-independent abstract processor, map processes on it, and proceed by steps, in a top-down fashion, from this abstraction to realization.     

VLSI Placement Using Quadratic Programming and Network Partitioning Techniques

VLSI cell placement involves positioning cells within a target placement geometry while minimizing the interconnecting wire length and placement area. In this paper, the placement problem is solved using a combination of quadratic programming, circuit partitioning, clustering and greedy cell interchange heuristics. The solution of a sequence of quadratic programs and circuit partitioning problems provides the general positions of cells in high quality palcement. Computational efficiency is achieved by using an interior point method for solving the sequence of quadratic programs. A very efficient clustering heuristic is used to keep important groups of cells together as the cells are spread throughout the placement area. Numerical results on a set of benchmark circuits illustrate that this new approach produces standard cell placements that are up 17% better in wire length. 14% better in row length and up to 25 times faster than a well known Simulated Annealing placement heuristic.     

双阈值CMOS电路静态功耗优化

集成电路设计进入深亚微米阶段后，静态功能不容忽视，提出一种基于双阈值电压的静态功耗优化算法，利用ISCAS85和ISCAS89电路集的实验结果表明，20％以上的静态功耗可以被消除（大规模电路在90％以上）。同时，文中算法也从很大程度上减小了电路的竞争冒险，提高了电路的性能。     

On the computational power of winner-take-all

This article initiates a rigorous theoretical analysis of the computational power of circuits that employ modules for computing winner-take-all. Computational models that involve competitive stages have so far been neglected in computational complexity theory, although they are widely used in computational brain models, artificial neural networks, and analog VLSI. Our theoretical analysis shows that winner-take-all is a surprisingly powerful computational module in comparison with threshold gates (also referred to as McCulloch-Pitts neurons) and sigmoidal gates. We prove an optimal quadratic lower bound for computing winner-take-all in any feedforward circuit consisting of threshold gates. In addition we show that arbitrary continuous functions can be approximated by circuits employing a single soft winner-take-all gate as their only nonlinear operation. Our theoretical analysis also provides answers to two basic questions raised by neurophysiologists in view of the well-known asymmetry between excitatory and inhibitory connections in cortical circuits: how much computational power of neural networks is lost if only positive weights are employed in weighted sums and how much adaptive capability is lost if only the positive weights are subject to plasticity.