一种虚拟共享存储器系统的实现

本文阐述了虚拟共享存储器的基本概念，并重点介绍了在多处理机系统中采用一种虚拟共享存储器的构成及其实现方法。     

利用共享RAM实现两CPU间的数据交换

介绍了基于单片机的分布式测控系统中一个节点内用来实现两个单片机紧耦合的共享存储器。通过分析比较几种共享存储器的方案，设计了一种使访存冲突完全在硬件电路控制下，在一个指令周期内得到解决的共享存储器结构，使系统对用户和两个ＣＰＵ都是透明的。     

一种共享存储器结构SIMD计算机互联网络的设计与实现

互连网络是设计 ＳＩＭＤ计算机的关键技术。该文通过设计 Ｌｅｅ无冲突访问互联网络,论述了共享存储器 ＳＩＭＤ计算机互联网络的一种设计与实现方法。     

共享存储器设计与应用

共享存储器是一种能被两个CPU访问的存储器。介绍不同类型共享存储器的设计方法及在应用中需要注意的若干问题。     

宿主机和并行处理机共享存储器模板的设计与实现

本文介绍了宿主机和并行处理机（MPP）之间采用共享存储器模板的数据交换方式,设计并实现了具有一定通用性的共享存储器模板。该模板采用主从式总线切换控制方法,存储器的组织方式可变,能够提供不同的访问带宽,可以为不同的宿主机和协处理机系统提供数据共享。     

一种高速微控制器

介绍一种与PC386微机进行高速数据交换的高速微控制器。提出了“互斥竞争式共享存储器”的设计思想,较好地解决了主从机之间的数据高速通信问题。相应给出了实现该方法的接口电路及有关逻辑。     

基于共享内存机制的控制系统模拟终端

介绍了一种基于共享内存进行数据通信的控制系统的模拟终端,重点阐述了数据通信的基本原理和模拟终端的软硬件设计和实现。该模拟终端的硬件平台采用计算机和PCI1730 I/O板卡组建,系统软件根据控制系统实际工作的通信机理,读取控制系统共享存储器中的数据,并对其进行处理、显示、存储。试验结果表明,该模拟终端可与控制系统之间实现共享存储器数据通信,达到了预期的目的。     

适用于SIMD并行算法的存储结构

本文给出一种适用于SIMD并行算法的共享存储器设计方案,它允许多个处理机按相应的同步并行算法并行无存取冲突地存取各自的数据,以满足算法执行的需要,该方案包含两部分,即数据在共享存储器内的存放方法和互联网络的结构及其功能,文章最后说明了该方案的若干性能、实现方法和优点。     

并行编程技术探讨

本文分别讨论了 共享存储器处理机和多计算机结构这两种并结构的并行编程方法和实现技术，这对于开发分布式编程环境，进行并行编程具有理论意义。     

实时并行图象处理系统的设计

该文介绍了一种并行实时图象处理系统的硬件实现。着重阐述了基于ＴＭＳ３２０系列的多ＤＳＰ处理器的硬件设计。给出了多处理器并行处理的原理，描述了多处理器间共享存储器及计算机主从系统的实现方法。此系统给图象的实时处理和其它的信号的实时处理提供了有力的工具，可广泛地用于计算机视觉，机器人视觉，工业监控和医学图象处理系统。     

CMOS current-mode neural associative memory design with on-chiplearning

Based on the Grossberg mathematical model called the outstar, a modular neural net with on-chip learning and memory is designed and analyzed. The outstar is the minimal anatomy that can interpret the classical conditioning or associative memory. It can also be served as a general-purpose pattern learning device. To realize the outstar, CMOS (complimentary metal-oxide semiconductor) current-mode analog dividers are developed to implement the special memory called the ratio-type memory. Furthermore, a CMOS current-mode analog multiplier is used to implement the correlation. The implemented CMOS outstar can on-chip store the relative ratio values of the trained weights for a long time. It can also be modularized to construct general neural nets. HSPICE (a circuit simulator of Meta Software, Inc.) simulation results of the CMOS outstar circuits as associative memory and pattern learner have successfully verified their functions. The measured results of the fabricated CMOS outstar circuits have also successfully confirmed the ratio memory and on-chip learning capability of the circuits. Furthermore, it has been shown that the storage time of the ratio memory can be as long as five minutes without refreshment. Also the outstar can enhance the contrast of the stored pattern within a long period. This makes the outstar circuits quite feasible in many applications.     

闪存高压电路的总剂量辐射效应研究

研究了闪存电路系统中高压电路的总剂量辐射效应（TID）。通过对内部高压电荷泵电路和高压负载电路的TID辐射效应测试研究,表明辐照后高压通路相关的存储阵列及高压晶体管漏电将造成电荷泵电路的负载电流过载失效,最终导致闪存电路编程或擦除操作失效。     

辐照加固集成电路

本文叙述了辐照加固集成电路在军事武器及航天设备中的意义，重点介绍了已有的辐照加固集成电路，如微处理器系列电路、数字电路、接口电路，最后通过对这些电路所用的加工技术的分析，提出了我国发展辐照加固集成电路的建议。     

Searching for memories, Sudoku, implicit check bits, and the iterative use of not-always-correct rapid neural computation

The algorithms that simple feedback neural circuits representing a brain area can rapidly carry out are often adequate to solve easy problems but for more difficult problems can return incorrect answers. A new excitatory-inhibitory circuit model of associative memory displays the common human problem of failing to rapidly find a memory when only a small clue is present. The memory model and a related computational network for solving Sudoku puzzles produce answers that contain implicit check bits in the representation of information across neurons, allowing a rapid evaluation of whether the putative answer is correct or incorrect through a computation related to visual pop-out. This fact may account for our strong psychological feeling of right or wrong when we retrieve a nominal memory from a minimal clue. This information allows more difficult computations or memory retrievals to be done in a serial fashion by using the fast but limited capabilities of a computational module multiple times. The mathematics of the excitatory-inhibitory circuits for associative memory and for Sudoku, both of which are understood in terms of energy or Lyapunov functions, is described in detail.     

Self-Dual Self-Testing Multicycle Circuits: Their Properties

Functional testing of memory circuits based on the properties of self-dual functions and a procedure for transforming the initial circuit into a self-dual circuit are described. Experimental results for MCNC benchmark circuits are given.     

浅谈存储器测试

随着半导体存储器向多品种、高速和高集成化等方向发展,测试问题显得越来越突出和重要。下面主要介绍了存储器电路的分类,以及存储器电路的测试参数和测试向量。     

A highly integrated AMLCD with low‐voltage operation

A highly integrated low‐temperature polysilicon AMLCD has been designed that operates from a 3‐V power supply and has a low‐voltage digital interface. This has been achieved by reducing the threshold voltage of the TFTs and integrating digital column drive circuits and charge‐pump circuits onto the display substrate. In standby mode, the display is capable of retaining an image without the need for external signals through the integration of dynamic‐memory circuits within the pixels of the display.     

Verification of Galois field based circuits by formal reasoning based on computational algebraic geometry

Algebraic error correcting codes (ECC) are widely used to implement reliability features in modern servers and systems and pose a formidable verification challenge. We present a novel methodology and techniques for provably correct design of ECC logics. The methodology is comprised of a design specification method that directly exposes the ECC algorithm’s underlying math to a verification layer, encapsulated in a tool “BLUEVERI”, which establishes the correctness of the design conclusively by using an apparatus of computational algebraic geometry (Buchberger’s algorithm for Gröbner basis construction). We present results from its application to example circuits to demonstrate the effectiveness of the approach. The methodology has been successfully applied to prove correctness of large error correcting circuits on IBM’s POWER systems to protect memory storage and processor to memory communication, as well as a host of smaller error correcting circuits.     

A new parallel sorting approach with sorting memory module

A new approach to accelerating parallel sorting processes is introduced in this paper. This approach involves the design of a new type of memory chip with sorting functions. This type of sorting memory chip is feasible with today's VLSI techniques. A memory module organizing several sorting memory chips associated with additional ECL or TTL control logic circuits is also presented. Using the sorting memory modules in a shared memory parallel processor machine, parallel sorting algorithms such as the column sort method can reduce the row access time significantly and avoid data collisions in the interconnection network. Experimental simulation results on the practical speedup achieved and the memory utilization for the proposed approach are described.