Low cost anodic bonding for MEMS packaging applications

Anodic bonding of Pyrex 7740 glass to bare silicon and oxidized silicon wafer is presented for micro electro mechanical systems (MEMS) device packaging. Experimentally it has been observed that anodic bonding process parameters are varying with different 3D structures. The effects of bonding temperature and voltage are discussed by keeping the temperature constant and varying the voltage. The bonding interface has been studied by scanning electron microscope observations. Effective parameters for MEMS structure such as bonding temperature, voltage has been discussed.     

Mechanical and electrical bonding between silicon wafer and glass wafer with etched channels containing metal tracks

In this paper a novel process to bond and, at the same time, to electrically connect a silicon wafer to a glass wafer is presented. It consists of a low temperature anodic bonding process between silicon and glass by using a glass wafer with etched channels in order to contain metal tracks. The glass-to-silicon anodic bonding process at low temperatures (not exceeding 300°C) assures a strong mechanical link (Berthold et al. in Transducers 1999, June:7–10, 1999). The electrical contacts between the metal pads on the backside of a silicon wafer and the metal pads on the glass wafer are achieved by sintering and diffusion of metals due to a kind of thermo compression bonding. This bonding method permits a high vertical control due to a well-controlled etching of the cavity depth and to the thickness precision of both metallization (pads on silicon wafers and metal tracks on glass wafer). This IC-processing compatible approach opens up the way to a new electrical connection concept keeping, at the same time, a strong mechanical bond between glass and silicon wafers for an easier fabrication of a more complex micro-system.     

Transfer of small structures by bonding

The work presented in this paper deals with the bonding of small structures, down to 1 μm. Its aim is to evaluate the dimensional limits of anodic bonding between silicon and pyrex 7740 glass. Test structures consisting in silicon pillars with controlled radii have been developed. The silicon pillars have been fabricated by deep reactive ion etching to allow a good geometry control of the structures. A collection of matrices of 3×3 identical silicon test structures with dimensions from 200 to 1 μm has been fabricated to determine the smallest area that can bond anodically. The test results have been applied to the transfer of small structures from one wafer to another wafer by bonding, with the final objective of transferring tips for AFM probes. From the test results, a new test for bonding has been defined, based on the pull test of small structures with controlled dimensions. Preliminary simulations by FEM of the pull test of the test structures are in agreement with the experimental results. The test has been used to determine the effect of the voltage and temperature conditions during the anodic bonding on the bond strength.     

Fabrication of an hermetically packaged silicon resonator on LTCC substrate

The design, fabrication and packaging process of silicon resonators capable of the integration of LSI (Large Scale Integration) have been developed on the basis of packaging technology using an LTCC (Low Temperature Co-fired Ceramic) substrate. The structures of silicon resonators are defined by deep reactive ion etching (DRIE) on a silicon on insulator (SOI) wafer and then transferred onto the LTCC substrate and hermetically sealed by anodic bonding technique. The measured resonant frequency of a micromechanical bulk acoustic mode silicon resonator after packaging at 0.02 Pa is 20.24 MHz with a quality factor of 50,600.     

Micro-mixer device with deep channels in silicon using modified RIE process: fabrication,packaging and characterization

In the present work, silicon based micromixer microfluidic devices have been fabricated in silicon substrates of 2-inch diameter. These devices are of 2-input and 1-output port configuration bearing channel depth in the range 80–280 µm. Conventional reactive ion etching (RIE) process used in integrated circuit fabrication was modified to get reasonably high silicon etch rate (~1.2 µm/min). It was anticipated that devices with channel depth in excess of 150 µm would become weak and susceptible to breakage. For such devices, a bonded pair of silicon having a 0.5 µm SiO₂ at the bonded interface was used as the starting substrate. The processed silicon wafer bearing channels was anodically bonded to a Corning^® 7740 glass plate of identical size for fluid confinement. Through-holes for input/output ports were made either in Si substrate or in glass plate before carrying out anodic bonding. Micro-channels were characterized using stylus and optical profiler. Surface roughness of the channel was observed to increase with increasing channel depth. The devices were packaged in a polycarbonate housing and pressure drop versus flow rate measurements were carried out. Reynolds number and friction factor were calculated for devices with 82 µm deep channels. It was observed that up to 25 sccm of gas and 10 ml/min of liquid, the flow was laminar in nature. It is envisaged that using bonded silicon wafer pair and combination of RIE and wet etching, it is possible to get an etch stop at the SiO₂ layer of the bonded silicon interface with much smaller value of surface roughness rendering smooth channel surface.     

Non-destructive in situ test for anodic bonding

New test structures have been designed, fabricated and tested to monitor the quality of the anodic bonding between silicon and glass. The main advantage of the described test is that it is not destructive and allows the bond quality to be monitored in processed wafers. This test is very easy to implement in a chip or in a wafer because of its simplicity. Test structures consist of a matrix of circular and rectangular cavities defined by reactive ion etching (RIE) on the silicon wafer, with different sizes and depths. The bonding process and quality can be monitorized by the measurement of the size of the smallest bonded cavity and the distance between the bonded area and the cavity border. These structures give information about the level of electrostatic pressure that has been applied to pull together into intimate contact the surfaces of the two wafers. The higher the electrostatic pressure, the better the bond. We have applied these test structures to study the influence of the voltage and the temperature on the anodic bonding process. Results are in good agreement with finite-element method (FEM) simulations.     

Research on low-temperature anodic bonding using induction heating

A novel low-temperature anodic bonding process using induction heating is presented in this paper. Anodic bonding between silicon and glass (Pyrex 7740) has been achieved at temperature below 300 °C and almost bubble-free interfaces have been obtained. A 1 kW 400 kHz power supply is used to induce heat in graphite susceptors (simultaneously as the high-voltage electrodes of anodic bonding), which conduct heat to the bonding pair and permanently join the pair in 5 min. The results of pull tests indicate a bonding strength of above 5.0 MPa for induction heating, which is greater than the strength for resistive heating at the same temperature. The fracture mainly occurs inside the glass or across the interface other than in the interface when the bonding temperature is over 200 °C. Finally, the interfaces are examined and analyzed by scanning electron microscopy (SEM) and the bonding mechanisms are discussed.     

A continuous-membrane micro deformable mirror based on anodic bonding of SOI to glass wafer

As one of the most important components in adaptive optics, the deformable mirror (DM) is required to have a flat surface for better performance. For micromachined DMs, single-crystal-silicon (SCS) membrane is an ideal material for high quality reflective mirror surface owing to its good flatness and small residual stress. In this research, a process was established to realize SCS mirror membrane by DRIE of SOI wafer and anodic bonding of SOI wafer to Pyrex 7740 glass. Using this process, the proof-of-concept for a micromachined DM composed of SCS mirror surface has been successfully demonstrated. The prototype DM shows a stroke of 4.23 μm at 120 V. The P–V and rms of the reflective mirror surface are 492 and 82 nm, respectively. The performance of the prototype DM can somewhat satisfy the need of AO in visible spectrum. Better surface quality is anticipated by employing SOI wafers with strictly controlled residual stress.     

Low-temperature anodic bonding of silicon to silicon wafers by means of intermediate glass layers

Silicon wafers have been anodically bonded to sputtered lithium borosilicate glass layers (Itb 1060) at temperatures as low as 150–180 °C and to sputtered Corning 7740 glass layers at 400 °C. Dependent on the thickness of the glass layer and the sputtering rate, the sputtered glass layers incorporate compressive stresses which cause the wafer to bow. As a result of this bowing, no anodic bond can be established especially along the edges of the silicon wafer. Successful anodic bonding not only requires plane surfaces, but also is determined very much by the alkali concentration in the glass layer. The concentration of alkali ions as measured by EDX and SNMS depends on both the sputtering rate and the oxygen fraction in the argon process gas. In Itb 1060 layers produced at a sputtering rate of 0.2 nm/s, and in Corning 7740 layers produced at sputtering rates of 0.03 and 0.5 nm/s, respectively, the concentration of alkali ions in the glass layers was sufficiently high, at oxygen partial pressures below 10^-4 Pa, to achieve anodic bonding. High-frequency ultrasonic microanalysis allowed the bonding area to be examined non-destructively. Tensile strengths between 4 and 14 MPa were measured in subsequent destructive tensile tests of single-bonded specimens.     

Versatile low temperature wafer bonding and bond strength measurement by a blister test method

We present a low temperature plasma assisted bonding process that enables the bonding of silicon, silicon oxide and silicon nitride wafers among each other at annealing temperatures as low as room temperature. The process can be applied using standard clean room equipment. Surface energies of differently treated bonded samples are determined by a blister test method for square shaped cavities. For this reason, we extend the well-known blister test method for round shaped cavities to the square shaped case by a combined analytical and numerical approach. Accordingly, the energetic favored crack front propagation in the bond interface is determined by numerical simulations. The surface energies of the tested samples are calculated and compared to anodic silicon-to-Pyrex^® bonds. Surface energies of up to 2.6 J/m² can be achieved between silicon and silicon oxide wafer pairs at low annealing temperatures. Room temperature bonded samples show a surface energy of 1.9 J/m². The surface energy of silicon-to-Pyrex glass bonds yields 1.3 J/m². Small structures, e.g., bridges down to 5 μm can be bonded using the discussed bonding process. Selective bonding of silicon-to-silicon oxide wafer pairs is performed by structuring the oxide layer. The successful integration of the bonding process into the fabrication of micropumps is highlighted.     

Defect-free wet etching through pyrex glass using Cr/Au mask

This paper reports the highest etch depth of annealed Pyrex glass achieved by wet etching in highly concentrated HF solution, using a low stress chromium–gold with assistance of photoresist as masking layer. The strategies to achieve that are: increasing the etch rate of glass and simultaneously increasing the resistance of Cr/Au mask in the etchant. By annealing the Pyrex glass and using a highly concentrated HF acid, a high etch rate can be obtained. Furthermore, a method to achieve a good resistance of the Cr/Au masking layer in the etching solution is to control the residual stress and to increase the thickness of Au deposition up to 1 μm. In addition, the presence of a hard baked photoresist can improve the etching performance. As a result, a 500-μm thick Pyrex glass wafer was etched through.     

Glass Blowing on a Wafer Level

A fabrication process for the simultaneous shaping of arrays of glass shells on a wafer level is introduced in this paper. The process is based on etching cavities in silicon, followed by anodic bonding of a thin glass wafer to the etched silicon wafer. The bonded wafers are then heated inside a furnace at a temperature above the softening point of the glass, and due to the expansion of the trapped gas in the silicon cavities the glass is blown into three-dimensional spherical shells. An analytical model which can be used to predict the shape of the glass shells is described and demonstrated to match the experimental data. The ability to blow glass on a wafer level may enable novel capabilities including mass-production of microscopic spherical gas confinement chambers, microlenses, and complex microfluidic networks     

Defect-free wet etching through pyrex glass using Cr/Au mask

This paper reports the highest etch depth of annealed Pyrex glass achieved by wet etching in highly concentrated HF solution, using a low stress chromium–gold with assistance of photoresist as masking layer. The strategies to achieve that are: increasing the etch rate of glass and simultaneously increasing the resistance of Cr/Au mask in the etchant. By annealing the Pyrex glass and using a highly concentrated HF acid, a high etch rate can be obtained. Furthermore, a method to achieve a good resistance of the Cr/Au masking layer in the etching solution is to control the residual stress and to increase the thickness of Au deposition up to 1 μm. In addition, the presence of a hard baked photoresist can improve the etching performance. As a result, a 500-μm thick Pyrex glass wafer was etched through.

     

Fabrication of a MEMS capacitive accelerometer with symmetrical double-sided serpentine beam-mass structure

This paper presents a symmetrical double-sided serpentine beam-mass structure design with a convenient and precise process of manufacturing MEMS accelerometers. The symmetrical double-sided serpentine beam-mass structure is fabricated from a single double-device-layer SOI wafer, which has identical buried oxides and device layers on both sides of a thick handle layer. The fabrication process produced proof mass with though wafer thickness (860 μm) to enable formation of a larger proof mass. Two layers of single crystal silicon serpentine beams with highly controllable dimension suspend the proof mass from both sides. A sandwich differential capacitive accelerometer based on symmetrical double-sided serpentine beams-mass structure is fabricated by three layer silicon/silicon wafer direct bonding. The resonance frequency of the accelerometer is measured in open loop system by a network analyzer. The quality factor and the resonant frequency are 14 and 724 Hz, respectively. The differential capacitance sensitivity of the fabricated accelerometer is 15 pF/g. The sensitivity of the device with close loop interface circuit is 2 V/g, and the nonlinearity is 0.6 % over the range of 0–1 g. The measured input referred noise floor of accelerometer with interface circuit is 2 μg/√Hz (0–250 Hz).     

Low-temperature quartz wafer bonding using hyperbranched polyurethane oligomers

In this paper, we introduce a new bonding technology for the assembly of micro- structured glass substrates for miniaturized chemical analysis. The protocol features a facile polymer chemistry method processing at lower temperatures (<100 °C). The method consisted of a proper cleaning of the two glass surfaces, followed by hydroxylization, aminosilylation and hyperbranched polyurethane oligomers (HPU) bridging on quartz wafer surfaces as the interlayer. Strong bonding with a shear force 4.5 MPa has been achieved. The present procedure avoids the possible micro-channel blockage and contamination by using conventional adhesives. Moreover, the microfluidic chips bonded by the above procedures are highly transparent therefore allowing for biochemical compositions to be easily characterized by UV–vis or IR spectroscopy.     

Sacrificial wafer bonding for planarization after very deep etching

A new technique is presented that provides planarization after a very deep etching step in silicon. This offers the possibility for resist spinning and layer patterning as well as realization of bridges or cantilevers across deep holes or grooves. The sacrificial wafer bonding technique contains a wafer bond step followed by an etch back. Results of polymer bonding followed by dry etching and anodic bonding combined with KOH etching are discussed. The polymer bonding has been applied in a strain based membrane pressure sensor to pattern the strain gauges and to provide electrical connections across a deep corrugation in a thin silicon nitride membrane by metal bridges     

Fabrication of silicon condenser microphones using single wafertechnology

A condenser microphone design that can be fabricated using the sacrificial layer technique is proposed and tested. The microphone backplate is a 1-μm plasma-enhanced chemical-vapor-deposited (PECVD) silicon nitride film with a high density of acoustic holes (120-525 holes/mm²), covered with a thin Ti/Au electrode. Microphones with a flat frequency response between 100 Hz and 14 kHz and a sensitivity of typically 1-2 mV/Pa have been fabricated in a reproducible way. These sensitivities can be achieved using a relatively low bias voltage of 6-16 V. The measured sensitivities and bandwidths are comparable to those of other silicon microphones with highly perforated backplates. The major advantage of the new microphone design is that it can be fabricated on a single wafer so that no bonding techniques are required     

A surface-tension driven micropump for low-voltage and low-power operations

In this paper, we first report a micropump actuated by surface tension based on continuous electrowetting (CEW). We have used the surface-tension-induced motion of a mercury drop in a microchannel filled with an electrolyte as actuation energy for the micropump. This allows low voltage operation as well as low-power consumption. The micropump is composed of a stack of three wafers bonded together. The microchannel is formed on a glass wafer using SU-8 and is filled with electrolyte where the mercury drop is inserted. The movement of the mercury pushes or drags the electrolyte, resulting in the deflection of a membrane that is formed on the second silicon wafer. Another silicon wafer, which has passive check valves and holes, is stacked on the membrane wafer, forming inlet and outlet chambers. Finally, these two chambers are connected through a silicone tube forming the complete micropump. The performance of the fabricated micropump has been tested for various operation voltages and frequencies. We have demonstrated actual liquid pumping up to 70 /spl mu/l/min with a driving voltage of 2.3 V and a power consumption of 170 /spl mu/W. The maximum pump pressure is about 800 Pa at the applied voltage of 2.3 V with an operation frequency of 25 Hz.     

Failure mechanisms of pressurized microchannels: model andexperiments

MicrochanneIs were created by fusion bonding of a Pyrex cover to a thermally oxidized silicon wafer, which contained anisotropically etched grooves. Such channels are frequently used in microfluidic handling systems, for example, in chemical analysis. Since in some of these labs-on-a-chip, in particular those used in liquid chromatography, the channels are subjected to high pressures of up to a few hundred bar, it is important to have information about the mechanical stability of the channel chip, in particular of the wafer bond involved in it. The latter is the subject of this paper. The maximum pressure that can be applied to several different channel chips was investigated experimentally. In order to find the relation among this maximum pressure, channel geometry, materials elasticity, and bond energy, an energy model was developed that is generally applicable to all types of wafer bonds. It was shown that the model is substantiated by the experimental pressure data, from which it could be calculated that the effective bond energy increased from 0.018 to 0.19 J/m² for an annealing temperature ranging from 310 to 470°C     

Room temperature bonding for vacuum applications: climatic and long time tests

A detailed and quantitative motivation for the necessity of room temperature (RT) bonding for wafer level packaging of silicon micro-mirrors will be given. Results on RT 6 inch wafer bonding with vacuum encapsulation on test structures are presented. Structured as well as unstructured wafers have been bonded at RT using a Mitsubishi Heavy Industries bonder. Unstructured wafers were used for the determination of the bonding strength, whereas the structured wafers were used for the evaluation of vacuum level and its stability with time.