嵌入式系统中的内存压缩技术

介绍内存压缩技术和一个基于硬件的内存压缩系统模型,探讨内存压缩技术在嵌入式系统中的应用;重点介绍内存压缩系统的硬件要求以及操作系统对内存压缩机制的支持;简单介绍内存压缩中常用的算法Lempel-Ziv,并就内存压缩技术在嵌入式系统中的应用问题作一些探讨。     

基于嵌入式工作站的粮情监控系统

介绍了一种基于MC68EZ328微处理器的嵌入式系统在粮情监控系统中的应用,阐述了嵌入式系统的规划方案、硬件构成和功能,并在此基础上提出了完整的软件、硬件实现方法。     

嵌入式Linux系统中USB的应用

随着USB设备在嵌入式系统中应用的日益广泛,对基于嵌入式系统的USB设备的开发需求也越发的迫切。本文首先对嵌入式系统和USB设备的发展进行了分析,然后从硬件结构及软件驱动等两方面论述了USB设备在嵌入式Linux系统中的应用。     

嵌入式远程监控系统的硬件设计与实现

随着电子技术与网络通信技术的飞速发展,嵌入式处理器逐渐在视频监控系统中得到了广泛的应用。本论文在简单介绍了嵌入式远程视频监控系统的特点,以及在对嵌入式处理器进行选型的基础上,重点分析探讨了嵌入式远程监控系统的硬件设计方案,给出了详细的系统层次框架设计,并对电源电路、A/D转换电路和网络通信电路进行了硬件设计,对于进一步提高嵌入式处理器在远程视频监控系统中的应用具有一定借鉴和指导意义。     

嵌入式Linux系统中USB的应用

随着USB设备在嵌入式系统中应用的日益广泛,对基于嵌入式系统的USB设备的开发需求也越发的迫切。本文首先对嵌入式系统和USB设备的发展进行了分析,然后从硬件结构及软件驱动等两方面论述了USB设备在嵌入式Linux系统中的应用。     

嵌入式系统门级在线自修复技术研究

为保证复杂电磁环境下嵌入式系统的安全运行,提出一种通用嵌入式系统在线故障自修复模型。基于ARM处理器和商业FPGA芯片实现原型试验系统,借鉴生物系统在遭受一定损伤时能自行康复的特点,结合仿生硬件领域中的内进化试验方法,在原型系统上设计重配置执行单元的门级冗余拓扑结构和自律控制单元的演化修复算法。利用马尔可夫模型评价系统的可靠性与稳态可用度。结果表明,在随机电磁损伤事件频繁发生并导致电路功能故障时,该系统能保持较高的可用度和安全性。     

无线通信在嵌入式系统中的应用

本文介绍了无线数传模块在嵌入式系统中的应用,嵌入式处理器与无线模块的硬件接口设计,无线模块的驱动程序的编写,预约式点对多点无线通信的传输协议的制定以及实现。为无线通信在嵌入式系统中的应用提供了有效的方案。     

无线通信在嵌入式系统中的应用

本文介绍了无线数传模块在嵌入式系统中的应用,嵌入式处理器与无线模块的硬件接口设计,无线模块的驱动程序的编写,预约式点对多点无线通信的传输协议的制定以及实现.为无线通信在嵌入式系统中的应用提供了有效的方案.     

基于Markov链的嵌入式系统硬件可靠性研究

嵌入式系统产品在使用过程中经常出现硬件故障,从而影响系统的安全可靠性。从嵌入式系统硬件层面研究其可靠性。首先定义嵌入式系统硬件目标,简单介绍了Markov过程理论;建立了单个IP硬核和嵌入式系统硬件的Markov模型;应用所建立的模型,对嵌入式站间自动闭塞控制器硬件进行了可靠度计算和分析。实验结果表明,该Markov模型能够准确描述嵌入式系统硬件的状态变迁,并能计算和分析其可靠度,具有一定的实用价值。     

嵌入式控制系统在分布式测控系统中的应用

分布式测控系统以其测控范围广、构建成本低等优势而得到广泛的应用,本文针对嵌入式控制系统在分布式测控系统中的应用展开了分析讨论,给出了完整的分布式测控系统的系统架构与系统层次功能的设计方案,并在此基础上重点对嵌入式控制系统,从硬件设计和软件设计两个角度完成了嵌入式分布测控系统的构建方案,对于进一步提高分布式测控系统,以及嵌入式控制系统在分布式网络中的应用均具有一定的借鉴和指导意义。     

一种实现演化硬件的软硬件协同工作模式

演化硬件是一个新兴的研究领域。文章讨论了演化硬件的基本原理,提出了演化硬件实现的四个条件,并对广泛用于实现演化硬件的一种FPGA-XC6200就其特点和结构以及它在实现演化硬件中的应用进行了介绍,并基于这种FPGA芯片给出了一种演化硬件的软硬件协同工作模式。文章最后就演化硬件进一步的研究方向进行了一个总结。     

基于进化算法的硬件演化基础研究

演化硬件研究将进化思想应用于电子系统内部结构的设计和调整,以实现硬件电路的自组织、自适应和自修复,从而提高系统的可靠性.介绍演化硬件的概念、基本原理和实现方法,指出目前研究存在的主要问题,给出进一步研究的设想与建议.     

Real-world applications of analog and digital evolvable hardware

In contrast to conventional hardware where the structure is irreversibly fixed in the design process, evolvable hardware (EHW) is designed to adapt to changes in task requirements or changes in the environment, through its ability to reconfigure its own hardware structure dynamically and autonomously. This capacity for adaptation, achieved by employing efficient search algorithms based on the metaphor of evolution, has great potential for the development of innovative industrial applications. This paper introduces EHW chips and six applications currently being developed as part of MITI's Real-World Computing Project; an analog EHW chip for cellular phones, a clock-timing architecture for Giga hertz systems, a neural network EHW chip capable of autonomous reconfiguration, a data compression EHW chip for electrophotographic printers, and a gate-level EHW chip for use in prosthetic hands and robot navigation     

Fault tolerance in co-evolutionary communication of EHW modules

Evolvable Hardware (EHW) is a new concept that applies evolutionary algorithms to hardware design. Based on previous work on co-evolutionary communication of EHW modules, this paper investigates the new feature of fault tolerance for this model. A fault model is built for the communication line between EHW modules. The experiment demonstrated in the presentation is the simulation of injecting stuck/bridging faults into an EHW-based serial adder that has been previously developed. The outcomes imply an outstanding feature of fault tolerance in this system with 100% fault coverage, which paves the way for bio-inspired approaches to fault tolerant design instead of the classic ones.     

Generalized disjunction decomposition for evolvable hardware.

Evolvable hardware (EHW) refers to self-reconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). One of the main difficulties in using EHW to solve real-world problems is scalability, which limits the size of the circuit that may be evolved. This paper outlines a new type of decomposition strategy for EHW, the "generalized disjunction decomposition" (GDD), which allows the evolution of large circuits. The proposed method has been extensively tested, not only with multipliers and parity bit problems traditionally used in the EHW community, but also with logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library and randomly generated circuits. In order to achieve statistically relevant results, each analyzed logic circuit has been evolved 100 times, and the average of these results is presented and compared with other EHW techniques. This approach is necessary because of the probabilistic nature of EA; the same logic circuit may not be solved in the same way if tested several times. The proposed method has been examined in an extrinsic EHW system using the (1 + lambda) evolution strategy. The results obtained demonstrate that GDD significantly improves the evolution of logic circuits in terms of the number of generations, reduces computational time as it is able to reduce the required time for a single iteration of the EA, and enables the evolution of larger circuits never before evolved. In addition to the proposed method, a short overview of EHW systems together with the most recent applications in electrical circuit design is provided.     

一种基于GEP的演化硬件复杂电路优化算法

演化硬件是近年来新兴的研究热点,它是演化算法和可编程逻辑器件相结合而形成的硬件设计新方法。在演化硬件中门电路的优化设计是一个重要的研究领域。提出一种新的基于基因表达式程序设计(GEP)的算法来进行复杂优化电路的设计,通过仿真实验表明,该算法不仅收敛速度快,而且还能利用该算法优化大规模的门电路,克服了传统优化方法的求解速度慢甚至不收敛等缺点。该算法较传统的电路优化方法更简单、更高效。     

On the practicality of using intrinsic reconfiguration for fault recovery

Evolvable hardware (EHW) combines the powerful search capability of evolutionary algorithms with the flexibility of reprogrammable devices, thereby providing a natural framework for reconfiguration. This framework has generated an interest in using EHW for fault-tolerant systems because reconfiguration can effectively deal with hardware faults whenever it is impossible to provide spares. But systems cannot tolerate faults indefinitely, which means reconfiguration does have a deadline. The focus of previous EHW research relating to fault-tolerance has been primarily restricted to restoring functionality, with no real consideration of time constraints. In this paper, we are concerned with EHW performing reconfiguration under deadline constraints. In particular, we investigate reconfigurable hardware that undergoes intrinsic evolution. We show that fault recovery done by intrinsic reconfiguration has some restrictions, which designers cannot ignore.     

模糊逻辑控制器的演化硬件实现

讨论在演化硬件（EHW）平台上实现模糊逻辑控制器的演化，模糊逻辑控制器是由一些if-the。规则的集合和具有模糊逻辑的输入输出语言术语特点的一些成员属性函数所构成，这里的演化硬件平台是指可编程模拟选择器阵列，通过遗传算法（GA）演化出的电路具有很强的自适应、自修复能力。     

基于精英池演化算法的数字电路在片演化方法

20世纪末演化硬件技术的提出为实现硬件系统的自适应与智能化等特征提供了一种可行的新技术,现阶段电路进化是演化硬件研究的热点之一.该文引入人工经验与规则,提出一种扩展矩阵编码法,保护具有较优结构的电路个体不易被淘汰;其次,基于多目标和局部寻优技术,结合子电路杂交与单元重要性的自适应变异策略,提出了一种设计数字电路的精英池演化算法,并在可编程逻辑器件上实现电路的自主动态重构与评价等演化过程.     

硬件演化原理及实现方法研究

文章对基于Virtex系列FPGA的硬件外部演化技术进行了研究，对演化算法的流程进行了分析，介绍了演化硬件的概念、原理、JBits API软件以及Virtex器件结构。基于JBits软件，采用外部演化的方式对电路进行演化，并通过仿真实例证明了这种方法的有效性。