基于FSM的测试序列生成方法研究

为了降低UIO序列方法的测试序列长度,通过研究现有的测试序列生成方法,将可逆序列引入到测试序列的生成算法中,将其作为所有转移和状态的连接序列,并利用中国农村邮递员问题的解法构造一条最短遍历路径,使得各个状态的UIO序列之间的重复部分达到最大,测试序列的整体长度被缩短。对测试序列的实验结果表明,算法能够有效降低测试序列的长度。     

On deriving test suites for nondeterministic finite state machines with time-outs

In the paper, the non-separability relation for finite state machines with time-outs is studied. A specific feature of such machines is integer-valued delays, or time-outs, which determine how long the finite state machine will stay in one or another state if there are no input actions. If the time-out is over and no input symbol has been applied, then the TFSM state is changed according to the transition under time delay. In the paper, an algorithm for constructing a separating sequence for such finite state machines is presented. Here, the separating sequence is a timed input sequence for which sets of input sequences of the TFSM do not intersect; hence, it is sufficient to apply the separating sequence once in order to distinguish the TFSMs by their output reactions. This algorithm underlies the algorithm for construction of test suites with respect to non-separability relation in the case where the fault domain is specified by means of a mutation machine. Test suite derivation with respect to non-separability relation by way of ??TFSM to FSM?? transformation is discussed.     

A construction of five-state real-time Fibonacci sequence generator

A cellular automaton (\(\mathrm {CA}\)) is a well-studied non-linear computational model of complex systems in which an infinite one-dimensional array of finite state machines (cells) updates itself in a synchronous manner according to a uniform local rule. A sequence generation problem on the \(\mathrm {CA}\) model has been studied for a long time and a lot of generation algorithms has been proposed for a variety of non-regular sequences such as \(\{2^n \,|\,n = 1, 2, 3,\ldots \}\), prime, and Fibonacci sequences, etc. In this paper, we propose a five-state real-time generator for Fibonacci sequence and give a formal proof of the correctness of the generator. The proposed five-state Fibonacci sequence generator is optimum in generation steps, and it is realized on a smallest, known at present finite state automaton in the number of states.     

Generating a checking sequence with a minimum number of reset transitions

Given a finite state machine M, a checking sequence is an input sequence that is guaranteed to lead to a failure if the implementation under test is faulty and has no more states than M. There has been much interest in the automated generation of a short checking sequence from a finite state machine. However, such sequences can contain reset transitions whose use can adversely affect both the cost of applying the checking sequence and the effectiveness of the checking sequence. Thus, we sometimes want a checking sequence with a minimum number of reset transitions rather than a shortest checking sequence. This paper describes a new algorithm for generating a checking sequence, based on a distinguishing sequence, that minimises the number of reset transitions used.     

面向Web服务测试的单线执行序列生成方法

测试用例自动生成是实现Web服务自动化测试的关键,基于代数规约的传统测试技术均依赖于创建、初始化和复制被测对象等操作来验证测试结果的正确性,但第三方Web服务并不支持这些操作,无法将测试用例转换成可执行操作序列。一种可行的解决方案是将测试用例转换成只包含一个被测服务实例、不包括实例初始化、只对实例进行状态修改和检查的线性执行序列。改进已有工作,提出包含逆项的测试执行图TEG-I来描述测试用例执行过程中的状态变化,设计TEG-I构造算法和单线执行序列生成算法并实现相应原型工具。实验结果表明,提出的方法能够有效地自动完成测试用例生成,提高Web服务的可测试性。     

Evolutionary generation of unique input/output sequences for class behavioral testing

Object-oriented software is composed of classes. Their behaviors are usually modeled with state diagrams or finite state machines (FSMs). Testing classes is regarded as testing FSMs in which unique input/output (UIO) sequences are widely applied. The generation of UIO sequences is shown to be an undecidable problem. For these problems, genetic algorithms (GAs) may offer much promise. This paper reports some primary results of on-going research on evolutionary testing classes. First, we explain how to define UIO sequence generation as a search problem, and then describe adapting genetic algorithms to generating UIO sequences. Special issues of using genetic algorithms such as solution representation, validity checking and fitness definition are discussed in detail. Primary experiments confirm the applicability and feasibility of applying GAs to UIO sequence generation.     

在带OCL约束的状态图下测试线索的自动生成*

保证软件质量的前提下如何减少测试用例规模是测试设计的关键技术之一。提出一种带OCL约束的状态图测试线索的自动生成方法。该方法自动解析类图和带OCL约束的状态图的XML模型文件,获取相应的状态节点邻接表,再结合状态对-事件约束集合生成带OCL约束的测试线索。实例研究表明,通过OCL约束冲突判断可避免不可行测试线索的生成,减少测试用例数目,达到降低测试成本的目的。实验结果证明了该方法的可行性和有效性。     

Test sequence generation and model checking using dynamic transition relations

The task of finding a set of test sequences that provides good coverage of industrial circuits is infeasible because of the size of the circuits. For small critical subcircuits of the design, however, designers can create a set of test sequences that achieve good coverage. These sequences cannot be used on the full design because the inputs to the subcircuit may not be accessible. In this work we present an efficient test generation algorithm that receives a test sequence created for the subcircuit and finds a test sequence for the full design that reproduces the given sequence on the subcircuit. The algorithm uses a new technique called dynamic transition relations to increase its efficiency .The most common and most expensive step in our algorithm is the computation of the set of predecessors of a set of states. To make this computation more efficient we exploit a partitioning of the transition relation into a set of simpler relations. At every step we use only those that are necessary, resulting in a smaller relation than the original one. A different relation is used for each step, hence the name dynamic transition relations. The same idea can be used to improve symbolic model checking for the temporal logic CTL.We have implemented the new method in SMV and run it on several large circuits. Our experiments indicate that the new method can provide gains of up to two orders of magnitude in time and space during verification. These results show that dynamic transition relations can make it possible to verify circuits that were previously unmanageable due to their size and complexity .     

一种用于类测试的改进型EFSM模型

扩展有限状态机(EFSM)中迁移存在前置条件和相应操作,而前置条件和相应操作中变量的相互依赖性导致了EFSM中存在不可达路径,不利于基于EFSM模型的类的测试。通过把UML状态图转换成EFSM模型,提出一种消除EFSM模型不可达路径算法,从而建立一种用于面向对象软件的类测试模型,通过该模型可以应用传统的数据流和控制流分析技术对类进行测试。     

基于通信扩展有限状态机的测试集生成技术

在协议一致性测试中，选择恰当的测试例至关重要。文章介绍协议一致性测试的基本概念及有限状态机和扩展有限状态机的测试模型，重点探讨基于通信扩展有限状态机的测试集生成技术。