一种工作在亚阈区超低功耗带隙基准源的设计

基于RFID标签芯片的低功耗要求,设计了一种超低功耗的带隙基准电压源,电路中的主要MOS管都工作在亚阈值状态。在spectre环境下仿真表明,当电源电压为3 V～7 V,温度在-30℃～+120℃变化时,输出基准电压为1.8 V±0.001 V。电源电压抑制比(PSRR)为69.5 dB,并且电路工作电流维持在1.5μA～7μA的范围内。     

一种低电压亚阈值CMOS基准电路的设计

利用负反馈技术设计了一款基于CMOS亚阈值MOS器件的低压高性能CMOS基准源电路。基于SMIC 0.18μm标准CMOS工艺,Cadence Spectre仿真结果表明：所设计的基准电路能在0.8V电压下稳定工作,输出380.4mV的基准电压;在1kHz频率范围内,电源噪声抑制比为-56.5dB;在5℃到140℃范围内,温度系数6.25ppm/℃。     

一种低功耗高精度带隙基准的设计

基于U MC 0.25μm BCD工艺,在传统带隙基准结构的基础上,设计了一种具有低功耗、高精度的基准,同时利用N MOS管工作在亚阈值区域时漏电流和栅极电压的指数特性,对基准温度特性曲线进行二阶补偿。仿真结果表明,电源电压5V时,静态电流功耗为3.16μA;电源电压2.5 V~5.5 V,基准电压变化53μV;温度在-40℃~130℃内,电路的温度系数为0.86×10-6/℃;三种工艺角下,低频时电路电源抑制比都小于-95 d B。     

一款应用于物联网芯片的皮安级CMOS电压基准源

设计了一种应用于物联网芯片的极低功耗电压基准源。由于漏致势垒降低(Drain-Induced Barrier Lowering,DIBL)效应,栅致漏极泄漏(Gate-Induced Drain Leakage, GIDL)效应及栅-漏电容馈通效应的影响,传统的基于MOS管漏电流的皮安级电压基准源虽然可以实现较低的温度系数,但是线性调整率及电源抑制比(Power Supply Rejection Ratio, PSRR)过低,大大限制了其在具有高电源噪声的物联网芯片中的应用。在传统的双MOS管电压基准源基础上,基于0.18μm CMOS工艺,设计了一种新型的自稳压五MOS管电压基准源。Spectre仿真结果显示,0～120℃范围内,该自稳压五MOS管电压基准源的平均温度系数为39.2 ppm/℃;电源电压1.0～2.0 V范围内,该电压基准源的线性调整率为33.4 ppm/V;负载电容3 pF情况下,该电压基准的PSRR性能为-9 dB@0.01 Hz及-62 dB@100 Hz。另外,在该0.18μm CMOS工艺下,该电压基准的电流消耗仅为59 pA@27℃,版图面积仅为5 400μm~2。     

基于阈值电压差原理的CMOS电压基准源

设计了一种新型的纯MOS结构电压基准源,提出了一个基于简单偏置电路的电流相加电路,利用该电路中具有与电源电压无关且与环境温度成反比特性的和式电流,改善了PMOS和NMOS阈值电压差电路输出电压的温度性能,提高了电压基准源的精度。     

0.13 μm CMOS电流模式高精度基准源设计

为提升基准源的精度,降低功耗,设计了一种新型带曲率补偿的低功耗带隙基准电路。该电路根据MOS管亚阈值区固有指数关系去补偿PNP型晶体管发射结电压的高阶温度特性,在只增加两股镜像电流下,该带隙基准电路与传统一阶低压带隙基准电路相比,具有低功耗和更低的温漂系数。基于中芯国际130 nm COMS工艺,仿真表明,温度在-20℃~80℃范围内,温漂为4.6 ppm/℃,电源抑制比为60 dB,输出基准电压为610 mV,整体电路功耗为820 nW。     

一种用于无源RFID标签芯片的可校准低功耗基准源

提出一种应用于RFID芯片的低功耗、可校准基准源电路。设计采用了全MOS管以及电阻来实现,大部分管子都工作在亚阈值状态,同时可以产生基准电压和基准电流。该基准源采用了GSMC 0.13 μm 1P5M工艺来实现,其最大工作电流不超过350 nA,供电电压为1.2 V,并且在0.9 V~2.5 V电压下均可工作。在-45℃~65℃的工作温度下,电压基准源的温度系数为30.3 ppm/℃,电流基准源的温度系数为20.7 ppm/℃。     

一种新颖的低电压CMOS带隙基准源设计

设计一种新颖的低电压CMOS带隙基准电压源电路.电路采用了适合低电源电压工作的nMOS输入对管折叠共源共栅运算放大器,并提出一种新颖的启动电路.基于SMICO.35μm标准CMOS工艺,Cadence Spectre仿真结果表明:在低于1-V的电源电压下,所设计的电路能稳定工作,输出稳定的基准电压为622mV,最低电源电压为760mV.不高于100KHz的频率范围内,电源噪声抑制比为-75dB.在-20℃到100℃范围内,温度系数20ppm/℃.     

一种二阶补偿带隙基准设计

基于分段补偿原理和MOS管的漏极电流是过驱动电压的平方关系函数,提出了一种新颖的二阶补偿结构,仅引入一股与温度成平方关系的电流,既补偿了低温阶段的基准电压,又补偿了高温阶段的基准电压,大大提高了基准电压源随温度变化的稳定性。采用0.5μm BCD工艺对电路进行仿真,结果表明,输出电压为1.24 V,温度范围在-35℃～135℃时,温度系数为2.82 ppm/℃;在低频时,电源抑制比达到了75.6 dB。     

一种带隙基准源分段线性补偿的改进方法

为了减小带隙基准源的温度系数和提高温度补偿的灵活性,设计了一种改进型分段线性补偿方法。利用双极型晶体管的温度非线性在整个温度区域内产生7段不同斜率的补偿电流,通过电流模形式对基准电压的高阶温度分量进行叠加,进而对带隙基准电压实现精确温度补偿。基于0.25μm BCD工艺设计了一款低温漂高精度的带隙基准源。HSPICE仿真结果表明,在5 V电源电压下,在-40℃~125℃温度范围内,基准电压的温度系数为0.37×10-6/℃,低频时电路的电源抑制比为-85 dB。电源电压在2 V~5 V范围内,基准电压的线性调整率为0.09 mV/V。     

PVT‐compensated low‐voltage and low‐power CMOS LNA for IoT applications

In this paper, a low‐noise amplifier (LNA) with process, voltage, and temperature (PVT) compensation for low power dissipation applications is designed. When supply voltage and LNA bias are close to the subthreshold, voltage has significant impact on power reduction. At this voltage level, the gain is reduced and various circuit parameters become highly sensitive to PVT variations. In the proposed LNA circuit, in order to enhance efficiency at low supply voltage, the cascade technique with g_m boosting is used. To improve circuit performance when in the subthreshold area, the forward body bias technique is used. Also, a new PVT compensator is suggested to reduce sensitivity of different circuit's parameters to PVT changes. The suggested PVT compensator employs a current reference circuit with constant output regarding temperature and voltage variations. This circuit produces a constant current by subtracting two proportional to absolute temperature currents. At a supply voltage of 0.35 V, the total power consumption is 585 μW. In different process corners, in the proposed LNA with PVT compensator, gain and noise figure (NF) variations are reduced 10.3 and 4.6 times, respectively, compared to a conventional LNA with constant bias. With a 20% deviation in the supply voltage, the gain and noise NF variations decrease 6.5 and 34 times, respectively.     

Design of low power,high speed 4 bit binary to Gray converter with 8 × 4 barrel shifter using nano dimensional MOS transistor for arithmetical,logical and telecommunication circuit and system application

In this work the design of 4 bit binary to Gray code converter circuit with 8 × 4 barrel shifter has been carried out. The circuit has been designed using metal oxide semiconductor (MOS) transistor. The verification of the functionality of the circuits has been performed using Tanner-SPICE software. Power consumption and speed are the major design metrics for very large scale integrated circuit. In this work the average power consumption and gate delay analysis of 4 bit binary to Gray converter with 8 × 4 barrel shifter has been carried out using nano dimensional MOS transistor having channel length of 150 nm. Power consumption, delay analysis has been carried out for different set of supply voltage. It has been observed that power consumption of the 4 bit binary to Gray converter with 8 × 4 barrel shifter has been reduced by reducing the power supply voltage V_DD. The power consumption and delay offers by the circuit is very less. At 1 V V_DD, power consumption and delay are 0.15 μW and 52.7 ps respectively. Therefore the circuit is suited for low power and high speed application in the area of arithmetical, logical and telecommunication.

     

基于BiCMOS工艺可修调的高精度低温度系数带隙基准源设计

设计了一种利用电阻比值校正一阶温度系数带隙基准电路的非线性温度特性来实现低温度系数的高精度低温度系数带隙基准源;同时设置了修调电路提高基准电压的输出精度.该带隙基准源采用0.8μm BiCMOS(Bipolar-CMOS)工艺进行流片,带隙基准电路所占面积大小为0.04 mm2.测试结果表明:在5 V电源电压下,在温度-40℃～125℃范围内,基准电压的温度系数为1.2×10-5/℃,基准电流的温度系数为3.77×10-4/℃;电源电压在4.0 V～7.0 V之间变化时,基准电压的变化量为0.4 mV,电源调整率为0.13 mV/V;基准电流的变化量为变化量约为0.02μA,电源调整率为6.7 nA/V.     

基于E类功放质谱射频的电源设计与优化

现场质谱仪在野外长时间续航,要求低功耗、高工作效率、宽范围扫描电压的射频电源予以支持。为满足这些要求,设计了基于 E 类功放模型的射频电源。使用 ADS 设计π型阻抗匹配网络,通过 Multisim联合仿真,对已设计的匹配网络进行参数优化,提高工作效率。与其它射频电源相比,采用单管 E 类开关功放,在简化设计、提升效率、提高射频扫描电压方面更具优势,并能够有效提高质谱仪的质量数扫描范围,增强质谱仪器的现场检测能力,具有十分广泛的应用前景和实际意义。     

高精度电流偏置电路的设计

提出了一款应用于RF无线收发芯片的高精度电流偏置电路。综合考虑功耗、面积和失调电压对基准电压的影响,设计了一款符合实际应用的带隙基准电路。并以带隙基准电路作基准电流源的偏置,采用电压电流转换器结构设计了具有高电源电压抑制比（PSRR）的基准电流源。电流镜采用辅助运放的设计方法来提高电流镜的输出阻抗,减小沟道调制效应对输出的基准电流的影响,从而提高输出基准电流的精度。采用0．35μzmCMOS工艺设计芯片版图,版图面积为0．18mm^2。提取寄生参数（PEX）仿真结果表明,该电路在-55℃～＋90℃范围内的温度系数为15．5ppm／℃,室温下基准电压为1．2035V;在低频段电流源的电源抑制比为90dB;在外接电阻从1kΩ～400kΩ变化时,输出基准电流误差范围是0．0001μA。     

An analog CMOS central pattern generator for interlimb coordination in quadruped locomotion.

This paper proposes a neuromorphic analog CMOS controller for interlimb coordination in quadruped locomotion. Animal locomotion, such as walking, running, swimming, and flying, is based on periodic rhythmic movements. These rhythmic movements are driven by the biological neural network, called the central pattern generator (CPG). In recent years, many researchers have applied CPG to locomotion controllers in robotics. However, most of these have been developed with digital processors and, thus, have several problems, such as high power consumption. In order to overcome such problems, a CPG controller with analog CMOS circuit is proposed. Since the CMOS transistors in the circuit operate in their subthreshold region and under low supply voltage, the controller can reduce power consumption. Moreover, low-cost production and miniaturization of controllers are expected. We have shown through computer simulation, such circuit has the capability to generate several periodic rhythmic patterns and transitions between their patterns promptly.     

Parameter optimization of an on-chip voltage reference circuitusing evolutionary programming

This paper presents an application of evolutionary programming to parameter optimization in the design of a voltage reference circuit. Designing circuits consists of two steps: topological design and parameter determination. After designing a topology suitable for the circuit, the designer selects an appropriate value for each circuit element from a circuit analysis and his experience. This step is difficult and time consuming because the designer must consider many factors simultaneously. As more precise circuits are required, parameter optimization becomes more complex. The voltage reference circuit, which requires a precise reference voltage independent of power fluctuation and temperature change, is such an example. In this paper, evolutionary programming is used as an effective method of finding good parameter values for the elements of the voltage reference circuit. Simulation results show that this method provides good performance and can be used as an effective method for circuit design     

基于电流控制模式的低压、高PSRR基准源

基于可调电流控制模式设计出一种低压、高电源抑制比的带隙基准电压源电路。采用电流控制模式和多反馈环路,提高电路的整体电源抑制比;通过电阻分压的方式,使电路达到低压,同时提供偏压,简化偏置电路。采用0.5μmCMOS N阱工艺,电路可在电源电压为1.5V时正常工作。使用Cadence Spectre进行仿真结果表明,低频时电源抑制比(PSRR)高达107dB。-10℃～125℃温度范围内,平均温度系数约7.17ppm/℃,功耗仅为0.525mW。此电路能有效地抑制制程变异。