A self‐reset ambient‐light sensor system for low‐temperature polycrystalline‐silicon active‐matrix displays

Abstract— A new digital ambient‐light sensor system has been designed and fabricated on a glass substrate using a conventional low‐temperature polycrystalline‐silicon (LTPS) technology. In the proposed system, analog‐to‐digital conversion (ADC) is performed in the time domain instead of the voltage domain and is combined with a light‐detection process. The proposed system employs self‐reset architecture and requires only one comparator for n‐bit digital output. Because the complex analog circuitry is eliminated from the system, it can be readily integrated on the glass substrate.     

Digital‐to‐analog converter with gamma correction on glass substrate for TFT‐panel applications

Abstract— Low‐temperature polysilicon (LTPS) technology has a tendency towards integrating all circuits on glass substrate. However, the poly‐Si TFTs suffered poor uniformity with large variations in the device characteristics due to a narrow laser process window for producing large‐grained poly‐Si TFTs. The device variation is a serious problem for circuit realization on the LCD panel, so how to design reliable on‐panel circuits is a challenge for system‐on‐panel (SOP) applications. In this work, a 6‐bit R‐string digital‐to‐analog converter (DAC) with gamma correction on glass substrate for TFT‐panel applications is proposed. The proposed circuit, which is composed of a folded R‐string circuit, a segmented digital decoder, and reordering of the decoding circuit, has been designed and fabricated in a 3‐μm LTPS technology. The area of the new proposed DAC circuit is effectively reduced to about one‐sixth compared to that of the conventional circuit for the same LTPS process.     

Design and implementation of readout circuit on glass substrate with digital correction for touch‐panel applications

Abstract— A readout circuit on glass substrate with digital correction, which contains a transconductance amplifier, counter, and digital correction circuit, has been designed for touch‐panel applications for 3‐μm low‐temperature polysilicon (LTPS) technology. The voltage difference as a result of a change in capacitance due to a touch event is converted to current by a transconductance amplifier. By charging and discharging the capacitor in the counter, the counter displays different digital‐output codes according to touch or non‐touch events. Furthermore, not only can the touch or non‐touch event be distinguished, but also the influence of LTPS process variation can be compensated by a digital correction circuit in the proposed readout circuit.     

Peripheral circuit designs using low‐temperature p‐type poly‐Si thin‐film transistors

Abstract— P‐type low‐temperature (450°C) polycrystalline‐silicon thin‐film‐transistor circuits for peripheral driver integration in active‐matrix displays are proposed and verified. A low‐voltage (5 V) driven poly‐Si scan driver is designed by employing a level shifter and shift register. A source driver for six‐bit digital interface is proposed, and the building blocks such as latch, DAC, and analog buffer are described. The latch samples and holds the digital bits (D and D') without an output voltage loss. A new source‐follower type analog buffer is developed and exhibits a small offset deviation regardless of the V_TH variation of the buffer TFT. The simulation and measurement results ensure that the proposed circuits were successfully designed for p‐type panel integration.     

Active stylus‐touch discrimination scheme based on anomaly detection algorithm

This paper proposes an anomaly detection (AD) algorithm that can discriminate stylus‐touch based on capacitive touch screen panel. The digital value acquired from an analog‐to‐digital converter (ADC) are transferred to an autoencoder including an encoder and a decoder. While the encoder classifies only two classes of a no‐touch and a finger‐touch, the decoder reconstructs the similar sequence to the input one according to the encoder's decision. Because the touch sequences caused by the stylus are not trained, the large difference between input and output sequences is used to discriminate the stylus‐touch from finger‐touch and no‐touch. The proposed method is evaluated by means of an 8‐inch capacitive touch panel, an AD touch detection board, and a stylus board. At the sequence length of 16 touch samples, the measured bit error rate (BER) of less than 10^?6 for each touch case is equivalent to the previous support vector machine (SVM) scheme whereas the number of multipliers is dramatically reduced to 16, compared with 400 of the previous SVM method.     

Digital time‐modulation pixel memory circuit in LTPS technology

Abstract— A digital time‐modulation pixel memory circuit on glass substrate has been designed and verified for a 3‐μm low‐temperature polysilicon (LTPS) technology. From the experimental results, the proposed circuit can generate 4‐bit digital codes and the corresponding inversion data with a time‐modulation technique. While the liquid‐crystal‐display (LCD) panel operates in the still mode, which means the same image is displayed on the panel, a data driver for an LCD panel is not required to provide the image data of the frame by the proposed pixel memory circuit. This pixel memory circuit can store the frame data and generate its corresponding inversion data to refresh a static image without activating the data driver circuit. Therefore, the power consumption of a data driver can be reduced in the LCD panel.     

Nanoscale triple-gate FinFET design considerations based on an analytical model of short-channel effects

In this paper,a three-dimensional(3-D)analytical model for short-channel effects(SCEs)in a nanoscale triple-gate(TG)FinFET is derived based on solving a boundary value problem using the 3-D Poisson’s equation.This model is validated using 3-D numerical simulations(TCAD Sentaurus).Results show that SCEs in a TG FinFET can be controlled by reducing either the fin thickness(D)or height(H).On the other hand,when fixing the drive capability of turn-on current,i.e.fixing the total width of the conductive channel,and changing the ratio of D and H,there exists a case where SCEs are worst,and SCEs can be reduced by either increasing or decreasing the ratio from the worst case.This SCEs model can be used to predict the minimum channel length(Lmin)of a device when D,H,and tox are fixed,while keeping SCEs at a tolerable level.Based on the analytical model,the insights into the physics of SCEs in nanoscale TG FinFET are discussed,and design considerations are investigated.     

A novel pixel memory using integrated voltage‐loss‐compensation (VLC) circuit for ultra‐low‐power TFT‐LCDs

Abstract— A novel pixel memory using an integrated voltage‐loss‐compensation (VLC) circuit has been proposed for ultra‐low‐power TFT‐LCDs, which can increase the number of gray‐scale levels for a single subpixel using an analog voltage gray‐scale technique. The new pixel with a VLC circuit is integrated under a small reflective electrode in a high‐transmissive aperture‐ratio (39%) 3.17‐in. HVGA transflective panel by using a standard low‐temperature‐polysilicon process based on 1.5‐μm rules. No additional process steps are required. The VLC circuit in each pixel enables simultaneous refresh with a very small change in voltage, resulting in a two‐orders‐of‐magnitude reduction in circuit power for a 64‐color image display. The advanced transflective TFT‐LCD using the newly proposed pixel can display high‐quality multi‐color images anytime and anywhere, due to its low power consumption and good outdoor readability.     

A small‐area and low‐power data driver IC using two‐stage DAC with a capacitor array for active matrix flat‐panel displays

A small‐area and low‐power data driver integrated circuit (IC) using a two‐stage digital‐to‐analog converter (DAC) with a capacitor array is proposed for active matrix flat‐panel displays. The proposed data driver IC employs a capacitor array in the two‐stage DAC so as to reduce the DAC area and eliminate the need for a resistor string, which has high‐power consumption. To verify the proposed two‐stage DAC, a 20‐channel data driver IC with the proposed 10‐bit two‐stage DAC was fabricated using a 0.18‐μm complementary metal–oxide–semiconductor process with 1.8 and 6 V complementary metal–oxide–semiconductor devices. The proposed 10‐bit two‐stage DAC occupies only 43.8% of the area of a conventional 10‐bit two‐stage DAC. The measurement results show that the differential nonlinearity and integral nonlinearity are +0.58/?0.52 least significant bit and +0.62/?0.59 least significant bit, respectively. The measured interchannel deviation of the voltage outputs is 8.8 mV, and the measured power consumption of the 20‐channel data driver IC is reduced to 7.1 mW, which is less than half of the power consumed by the conventional one.     

An area‐ratio gray‐scale method to achieve image uniformity in TFT‐LEPDs

Abstract— An area‐ratio gray‐scale method (ARG) has been developed for low‐temperature‐polysilicon thin‐film‐transistor‐driven light‐emitting‐polymer displays (LTPS TFT‐LEPDs). A pixel consists of plural sub‐pixels, which are controlled to be in either an on‐state or off‐state. The gray scale is acquired by selecting the number of the on‐state sub‐pixels, that is, the ratio of the light‐emitting area. One advantage of the ARG is to improve image uniformity. In the on‐state, since TFT resistance is negligible, the current is determined by the LEP diode resistance. Therefore, the TFT characteristic deviation has no effect on the current. Moreover, the dimensions of each sub‐pixel are the same, and the shapes of the sub‐pixel are circular in order to improve their uniformity. As a result, the image becomes uniform. Another advantage of the ARG is to achieve digital operation, which makes interfacing easy. A digital‐analog converter (DAC) automatically exists in the sub‐pixel and the naked eye.     

数字测量系统中传感器温度补偿的一种新方法

提出一种对传感器温度系数的校正新方法——采用二次方程校正法和温度补偿算法相结合的温度校正方法。该算法简单可靠、易实现。将A/D转换器的数字输出量和环境温度T都作为微控制器(MCU)的输入,经MCU处理运算后,获得准确的传感器测量值。     

Projection‐based head‐tracking 3‐D displays

Abstract— This paper describes the construction and operation of four 3‐D displays in which each display produces two images for each eye and thus fits into the category of projection‐based binocular stereoscopic displays. The four 3‐D displays described are pico‐projector‐based, liquid‐ crystal—on—silicon (LCOS) conventional projector‐based, 120‐Hz digital‐light‐processor (DLP) projector‐ based, and the HELIUM3D system. In the first three displays, images are produced on a direct‐view LCD whose conventional backlight is replaced with a projection illumination source that is controlled by a multi‐user head tracker; novel steering optics direct the projector output to regions referred to as exit pupils located at the viewers' eyes. In the HELIUM3D display, the image information is supplied by a horizontally scanned, fast, light valve whose output is controlled by a spatial light modulator (SLM) to direct images to the appropriate viewers' eyes. The current statu s and the multimodal potential of the HELIUM3D display are described.     

基于FPGA的Σ-ΔADC转换器的设计和实现

针对瞬时采样方法只适合变频器模拟量比较平滑且采样频率较高的场合和平均值采样法要求采样频率高、运算速度快的问题,设计了一种基于FPGA的Σ-ΔADC转换器,介绍了Σ-ΔADC转换器的结构原理和Sinc3滤波器的设计。该转换器将Σ-Δ调制器和FPGA有效结合,既提高了采样精度,也提高了模拟信号传输的抗干扰能力及检测装置耐压的能力。实验验证了该转换器的正确性。     

10‐bit source driver with resistor‐resistor‐string digital‐to‐analog converter

Abstract— A 10‐bit gray‐scale source driver using a resistor‐resistor‐string digital‐to‐analog converter (RR‐DAC) is proposed for a TFT‐LCD source driver. The 10‐bit RR‐DAC consists of an 8‐bit resistor‐string DAC and a two‐bit resistor‐string DAC without an intermediate unity‐gain buffer to isolate the parallel‐connected resistor string. The output deviation of the proposed source driver is less than ±3 mV. The chip area of the proposed 10‐bit source driver with an RR‐DAC is increased to 29% of that of an 8‐bit source driver.     

一种估计模拟分解滤波器组系数偏差的算法

模拟器件工艺偏差是制约混合滤波器组模拟数字转换器系统信号重构精度的主要原因,准确地得到模拟分解滤波器组传递函数是完成信号重构的首要条件.为解决上述问题,本文提出一种估计传递函数系数偏差的算法.该算法根据输入信号的信息以及信号通过模拟滤波器组后的采样数据,便可以准确地估计出偏差范围在±20%的模拟滤波器传递函数系数的偏差值.实验中分别采用2阶和3阶模拟滤波器传递函数模型,其谐振频率的估计值与理想偏差值的标准偏差分别为1.10%和0.56%.将估计值应用于单通路滤波混合滤波器组系统进行仿真,输出信号可以达到14位精度,完成了系统重构功能,仿真验证了该算法的可行性.     

A 13‐bit universal column driver for various displays of OLED and LCD

A universal column driver is implemented in a 0.13‐µm high‐voltage CMOS process for not only TFT‐LCD but also OLED applications. The proposed column driver employs 13‐bit linear DAC to cover all gamma curves of display applications and address‐based configuration for intra‐ panel interface protocol to support both TV and IT applications. Measured results demonstrate the average voltage of output channels (AVO) is under 1mv, which satisfies 1‐LSB resolution at 18.5V of AVDD.     

Asymptotic rejection of sinusoidal disturbances based voltage balance control in back‐to‐back power converters

This paper addresses the imbalance problem of the dc‐link capacitor voltages in the three‐level diode‐clamped back‐to‐back power converter. In order to cope with it, a mathematical analysis of the capacitor voltage difference dynamics, based on a continuous model of the converter, is first carried out. It leads to an approximated model that contains explicitly several sinusoidal functions of time. In view of this result, the voltage imbalance phenomenon can be addressed as an output regulation problem, considering the sinusoidal functions of time as exogenous disturbances. Thus, a novel approach to deal with the mentioned problem in the back‐to‐back converter is presented. Then, the particular features of the disturbances are used to design several controllers. They all follow an asymptotic disturbance rejection approach. In this way, the estimates of the disturbances are used to apply a control law that cancels them while regulating the capacitor voltage balance as well. Finally, the performance of the proposed control laws is evaluated, presenting the simulation results obtained when the different controllers are implemented. Copyright © 2013 John Wiley & Sons, Ltd.     

高精度电容式MEMS加速度计系统设计

在传统Σ-Δ架构基础上,引入了低精度高速模/数转换器(ADC),将前置放大器输出的模拟电压信号转换为数字信号,有利于简化电容式微电子机械系统(MEMS)加速度计系统模拟接口电路设计.在嵌入ADC的MEMS加速度系统中,采用过采样平均数字算法对信号进行估计,有效降低系统对前置放大器噪声性能的需求,利于实现低功耗和高精度的设计目标.仿真结果表明:与未采用过采样平均技术相比,当前置放大器输出等效噪声大于1μV/Hz时,系统的信噪比(SNR)提高了约10dB.     

Toward sub‐micron oxide thin‐film transistors for digital holography

High‐performance 2‐μm‐channel oxide thin‐film transistors (TFT) on glass substrate for a 7‐μm‐pixel‐pitch spatial light modulator panel for digital holography applications were fabricated using a two‐step source/drain etching process. It showed a μ_FE of 45.5 cm²/Vs, SS of 0.10 V/dec, and Von of near zero voltage. Furthermore, we succeeded in the demonstration of sub‐micron TFTs, which is an indispensable route to next‐generation spatial light modulation devices with near 1‐μm pixel pitch. The issue of short‐channel transistors for display applications is also introduced. Finally, the digital holographic demonstration results based on the fabricated backplane are presented.     

A complete UMTS transmitter using BAW filters and duplexer: A 90‐nm CMOS digital RF signal generator and a 0.25‐μm BiCMOS power amplifier

A complete UMTS transmitter is proposed. It is composed of a radiofrequency (RF) signal generator, a power stage, and a bulk acoustic wave (BAW) duplexer. The 90‐nm CMOS digital RF signal generator is based on a third‐order delta‐sigma modulator using innovative design techniques to increase work frequency and a BAW filter to get rid of out‐of‐band quantization noise. The filter exhibits very high rejection, 3 dB of insertion losses at 1.95 GHz for a 3% fractional bandwidth. The 0.25‐μm BiCMOS power stage feeds a BAW duplexer that allows to share a common between W‐CDMA emission and reception. This 4 × 4 mm² duplexer, built with flip‐chipped BAW on glass substrate, ensures good isolation. The full transmitter measurements show the compliance with respect to spurious emissions in the different frequency bands and an EVM measurement at the state of the art (<5%). © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2011.