An Exponential Lower Bound for the Size of Monotone Real Circuits

We prove a lower bound, exponential in the eighth root of the input length, on the size of monotone arithmetic circuits that solve an NP problem related to clique detection. The result is more general than the famous lower bound of Razborov and Andreev, because the gates of the circuit are allowed to compute arbitrary monotone binary real-valued functions (including AND and OR). Our proof is relatively simple and direct and uses the method of counting bottlenecks. The generalization was proved independently by Pudlák using a different method, who also showed that the result can be used to obtain an exponential lower bound on the size of unrestricted cutting plane proofs in the propositional calculus.     

On the computational power of winner-take-all

This article initiates a rigorous theoretical analysis of the computational power of circuits that employ modules for computing winner-take-all. Computational models that involve competitive stages have so far been neglected in computational complexity theory, although they are widely used in computational brain models, artificial neural networks, and analog VLSI. Our theoretical analysis shows that winner-take-all is a surprisingly powerful computational module in comparison with threshold gates (also referred to as McCulloch-Pitts neurons) and sigmoidal gates. We prove an optimal quadratic lower bound for computing winner-take-all in any feedforward circuit consisting of threshold gates. In addition we show that arbitrary continuous functions can be approximated by circuits employing a single soft winner-take-all gate as their only nonlinear operation. Our theoretical analysis also provides answers to two basic questions raised by neurophysiologists in view of the well-known asymmetry between excitatory and inhibitory connections in cortical circuits: how much computational power of neural networks is lost if only positive weights are employed in weighted sums and how much adaptive capability is lost if only the positive weights are subject to plasticity.     

On the Incompressibility of Monotone DNFs

We prove optimal lower bounds for multilinear circuits and for monotone circuits with bounded depth. These lower bounds state that, in order to compute certain functions, these circuits need exactly as many OR gates as the respective DNFs. The proofs exploit a property of the functions that is based solely on prime implicant structure. Due to this feature, the lower bounds proved also hold for approximations of the considered functions that are similar to slice functions. Known lower bound arguments cannot handle these kinds of approximations. In order to show limitations of our approach, we prove that cliques of size n - 1 can be detected in a graph with n vertices by monotone formulas with O(log n) OR gates. Our lower bound for multilinear circuits improves a lower bound due to Borodin, Razborov and Smolensky for nondeterministic read-once branching programs computing the clique function.     

Learning a circuit by injecting values

We propose a new model for exact learning of acyclic circuits using experiments in which chosen values may be assigned to an arbitrary subset of wires internal to the circuit, but only the value of the circuit's single output wire may be observed. We give polynomial time algorithms to learn (1) arbitrary circuits with logarithmic depth and constant fan-in and (2) Boolean circuits of constant depth and unbounded fan-in over AND, OR, and NOT gates. Thus, both AC0 and NC1 circuits are learnable in polynomial time in this model. Negative results show that some restrictions on depth, fan-in and gate types are necessary: exponentially many experiments are required to learn AND/OR circuits of unbounded depth and fan-in; it is NP-hard to learn AND/OR circuits of unbounded depth and fan-in 2; and it is NP-hard to learn circuits of constant depth and unbounded fan-in over AND, OR, and threshold gates, even when the target circuit is known to contain at most one threshold gate and that threshold gate has threshold 2. We also consider the effect of adding an oracle for behavioral equivalence. In this case there are polynomial-time algorithms to learn arbitrary circuits of constant fan-in and unbounded depth and to learn Boolean circuits with arbitrary fan-in and unbounded depth over AND, OR, and NOT gates. A corollary is that these two classes are PAC-learnable if experiments are available. Finally, we consider an extension of the model called the synchronous model. We show that an even more general class of circuits are learnable in this model. In particular, we are able to learn circuits with cycles.     

On the computational power of threshold circuits with sparse activity

Circuits composed of threshold gates (McCulloch-Pitts neurons, or perceptrons) are simplified models of neural circuits with the advantage that they are theoretically more tractable than their biological counterparts. However, when such threshold circuits are designed to perform a specific computational task, they usually differ in one important respect from computations in the brain: they require very high activity. On average every second threshold gate fires (sets a 1 as output) during a computation. By contrast, the activity of neurons in the brain is much sparser, with only about 1% of neurons firing. This mismatch between threshold and neuronal circuits is due to the particular complexity measures (circuit size and circuit depth) that have been minimized in previous threshold circuit constructions. In this letter, we investigate a new complexity measure for threshold circuits, energy complexity, whose minimization yields computations with sparse activity. We prove that all computations by threshold circuits of polynomial size with entropy O(log n) can be restructured so that their energy complexity is reduced to a level near the entropy of circuit states. This entropy of circuit states is a novel circuit complexity measure, which is of interest not only in the context of threshold circuits but for circuit complexity in general. As an example of how this measure can be applied, we show that any polynomial size threshold circuit with entropy O(log n) can be simulated by a polynomial size threshold circuit of depth 3. Our results demonstrate that the structure of circuits that result from a minimization of their energy complexity is quite different from the structure that results from a minimization of previously considered complexity measures, and potentially closer to the structure of neural circuits in the nervous system. In particular, different pathways are activated in these circuits for different classes of inputs. This letter shows that such circuits with sparse activity have a surprisingly large computational power.     

三值量子基本门及其对量子Fourier变换的电路实现

理论上可以把量子基本门组合在一起来实现任何量子电路和构建可伸缩的量子计算机。但由于构建量子线路的量子基本门数量庞大,要正确控制这些量子门十分困难。因此,如何减少构建量子线路的基本门数量是一个非常重要和非常有意义的课题。提出采用三值量子态系统构建量子计算机,并给出了一组三值量子基本门的功能定义、算子矩阵和量子线路图。定义的基本门主要包括三值量子非门、三值控制非门、三值Hadamard门、三值量子交换门和三值控制CR_k门等。通过把量子Fourier变换推广到三值量子态,成功运用部分三值量子基本门构建出能实现量子Fourier变换的量子线路。通过定量分析发现,三值量子Fourier变换的线路复杂度比二值情况降低了至少50%,表明三值量子基本门在降低量子计算线路复杂度方面具有巨大优势。     

Upper and lower bounds for some depth-3 circuit classes

We investigate the complexity of depth-3 threshold circuits with majority gates at the output, possibly negated AND gates at level two, and MOD _m gates at level one. We show that the fan-in of the AND gates can be reduced toO(logn) in the case wherem is unbounded, and to a constant in the case wherem is constant. We then use these upper bounds to derive exponential lower bounds for this class of circuits. In the unboundedm case, this yields a new proof of a lower bound of Grolmusz; in the constantm case, our result sharpens his lower bound. In addition, we prove an exponential lower bound if OR gates are also permitted on level two andm is a constant prime power.Dedicated to the memory of Roman Smolensky     

Can large fanin circuits perform reliable computations in the presence of faults?

For ordinary circuits with a fixed upper bound on the fanin of its gates it has been shown that logarithmic redundancy is necessary and sufficient to overcome random hardware faults (noise). Here, we consider the same question for unbounded fanin circuits which in the fault-free case can compute Boolean functions in sublogarithmic depth. Now the details of the fault model become more important. One may assume that only gates, resp. only wires may deliver wrong values, or that both gates and wires may behave faulty. The fault tolerance depends on the types of gates that are used, and whether the error probabilities are known exactly or only an upper bound for them. Concerning the first distinction the two most important models are circuits consisting of and- and or-gates with arbitrarily many inputs, and circuits built from the more general type of threshold gates. We will show that in case of faulty and/or-circuits as well as threshold circuits an increase of fanin and size cannot be traded for a depth reduction if the error probabilities are unknown. Gates with large fanin are of no use if errors may occur. Circuits of arbitrary size, but fixed depth can compute only a tiny subset of all Boolean functions reliably. Only in case of threshold circuits and exactly known error probabilities redundancy is able to compensate faults. We describe a transformation from fault-free to fault-tolerant circuits that is optimal with respect to depth keeping the circuit size polynomial.     

Majority gates vs. general weighted threshold gates

In this paper we study small depth circuits that contain threshold gates (with or without weights) and parity gates. All circuits we consider are of polynomial size. We prove several results which complete the work on characterizing possible inclusions between many classes defined by small depth circuits. These results are the following:

Monotone circuits for monotone weighted threshold functions

Weighted threshold functions with positive weights are a natural generalization of unweighted threshold functions. These functions are clearly monotone. However, the naive way of computing them is adding the weights of the satisfied variables and checking if the sum is greater than the threshold; this algorithm is inherently non-monotone since addition is a non-monotone function. In this work we by-pass this addition step and construct a polynomial size logarithmic depth unbounded fan-in monotone circuit for every weighted threshold function, i.e., we show that weighted threshold functions are in mAC¹. (To the best of our knowledge, prior to our work no polynomial monotone circuits were known for weighted threshold functions.)Our monotone circuits are applicable for the cryptographic tool of secret sharing schemes. Using general results for compiling monotone circuits (Yao, 1989) and monotone formulae (Benaloh and Leichter, 1990) into secret sharing schemes, we get secret sharing schemes for every weighted threshold access structure. Specifically, we get: (1) information-theoretic secret sharing schemes where the size of each share is quasi-polynomial in the number of users, and (2) computational secret sharing schemes where the size of each share is polynomial in the number of users.     

Improving the average delay of sorting

In previous work we have introduced an average case measure for the time complexity of Boolean circuits. Instead of fixed circuit depth, for each input we take the minimal number of time steps necessary to perform the computation for that particular input using gates that forward their output values as soon as possible. This measure is called delay. Based on it, the complexity of a whole class of functions that can be described as prefix computations has been analysed in detail.     

The depth of monotone Boolean functions with multi input “AND” and “OR” gates

The problem of maximum depth of monotone Boolean functions is investigated when k-input AND and OR gates are used for realisation.     

The Complexity of the Descriptiveness of Boolean Circuits over Different Sets of Gates

Any Boolean function can be defined by a Boolean circuit, provided we may use sufficiently strong functions in its gates. On the other hand, what Boolean functions can be defined depends on these gate functions: Each set B of gate functions defines the class of Boolean functions that can be defined by circuits over B. Although these classes have been known since the 1920s, their computational complexity was never investigated.In this paper we will study how difficult it is to decide for a Boolean function f and a class B, whether f is in B.Moreover, we will provide such a decision algorithm with additional information: How difficult is it to decide whether or not f is in B, provided we already know a circuit for f, but with gates from another class A? Given such a circuit, we know that f is in A. Is the problem harder if we do not have a concrete representation for f, but still know that it is from A? For nearly all possible combinations, we show that this is not the case, and that the problem is either in P or coNP-complete.     

Limiting negations in non-deterministic circuits

The minimum number of NOT gates in a Boolean circuit computing a Boolean function f is called the inversion complexity of f. In 1958, Markov determined the inversion complexity of every Boolean function and, in particular, proved that log₂(n+1) NOT gates are sufficient to compute any Boolean function on n variables. In this paper, we consider circuits computing non-deterministically and determine the inversion complexity of every Boolean function. In particular, we prove that one NOT gate is sufficient to compute any Boolean function in non-deterministic circuits if we can use an arbitrary number of guess inputs.     

On figures of merit in reversible and quantum logic designs

Five figures of merit including number of gates, quantum cost, number of constant inputs, number of garbage outputs, and delay are used casually in the literature to compare the performance of different reversible or quantum logic circuits. In this paper we propose new definitions and enhancements, and identify similarities between these figures of merit. We evaluate these measures to show their strength and weakness. Instead of the number of gates, we introduce the weighted number of gates, where a weighting factor is assigned to each quantum or reversible gate, based on its type, size and technology. We compare the quantum cost with weighted number of gates of a circuit and show three major differences between these measures. It is proved that it is not possible to define a universal reversible logic gate without adding constant inputs. We prove that there is an optimum value for number of constant inputs to obtain a circuit with minimum quantum cost. Some reversible logic benchmarks have been synthesized using Toffoli and Fredkin gates to obtain their optimum values of number of constant inputs. We show that the garbage outputs can also be used to decrease the quantum cost of the circuit. A new definition of delay in quantum and reversible logic circuits is proposed for music line style representation. We also propose a procedure to calculate the delay of a circuit, based on the quantum cost and the depth of the circuit. The results of this research show that to achieve a fair comparison among designs, figures of merit should be considered more thoroughly.      

On the minimum number of negations leading to super-polynomial savings

We show that an explicit sequence of monotone functions can be computed by Boolean circuits with polynomial (in n) number of And, Or and Not gates, but every such circuit must use at least logn−O(loglogn) Not gates. This is almost optimal because results of Markov [J. ACM 5 (1958) 331] and Fisher [Lecture Notes in Comput. Sci., Vol. 33, Springer, 1974, p. 71] imply that, with only small increase of the total number of gates, any circuit in n variables can be simulated by a circuit with at most ⌈log(n+1)⌉ Not gates.     

Circuits and multi-party protocols

Using multi-party communication techniques, we prove that depth-3 circuits with a threshold gate at the top, arbitrary symmetric gates at the next level, and fan-in k MOD _m gates at the bottom need exponential size to compute the k-wise inner product function of Babai, Nisan and Szegedy, where m is an odd positive integer satisfying . This is one of the rare lower-bound results involving MOD _m gates with non-prime power moduli.?Exponential gap theorems are also presented between the multi-party communication complexities of closely related functions. Received: January 5, 1994     

Linear nearest neighbor optimization in quantum circuits: a multiobjective perspective

Several current implementations of quantum circuits rely on the linear nearest neighbor restriction, which only allows interaction between adjacent qubits. Most methods that address the process of converting a generic circuit to an equivalent circuit which satisfies this restriction, minimize the number of additional SWAP gates required by this process. Moreover, most methods which address this problem are designed for 1D circuits. Considering the new and promising proposals for 2D quantum circuits, what we propose is a new perspective on this problem, namely that it can be seen as a multiobjective optimization problem. To test our hypothesis, we developed a multiobjective evolutionary algorithm that solves this problem by considering two objectives: minimizing the size of the 2D grid where the circuit is placed, and minimizing the number of additional SWAP gates. Of the methods designed for 2D circuits, only one considers different grid sizes which are much larger than strictly necessary. Consequently, our algorithm makes considerations which other methods do not make, since it naturally finds the grid which requires fewer SWAP gates for the circuit conversion, whether it is one-dimensional or two-dimensional. Our experimental results indicate that allowing a larger grid size results in fewer additional SWAP gates in about 73% of the tested circuits. Additionally, the average improvement we found when using larger grid sizes is about 30%, while the best improvement over using the smallest possible grid is 63.8%.     

Demand-driven logic simulation using a network of loosely coupled processors

Logic simulation is used extensively in the design of digital systems for the purpose of studying the behaviour of circuits under various conditions and for verifying the required performance of circuits. There is considerable interest in methods which reduce the simulation time during the design process. In this paper, we investigate how this can be achieved by simulating the action of logic circuits using a network of loosely coupled processors. Circuits modelled as directed graphs comprising clocked sequential components and (unclocked) arbitrary combinational logic gates can be partitioned into separate tasks each consisting of a sequential component with an associated network of combinational components. We present cost functions for evaluating a task subject to probabilistic assumptions about the functioning of the circuits. The circuit evaluation method used in the simulation process is significant. We apply lazy evaluation, a demand-driven evaluation strategy in which signals in the circuit are evaluated on a ‘need to do' basis, resulting in a considerable saving in circuit simulation time. We achieve distributed logic simulation using a network of workstations and show from experimental results that by using such a configuration, we essentially obtain a single computation engine which can be used to obtain speedups in circuit simulation when compared with uniprocessor simulation systems. Interprocess communications between tasks on different workstations proceed via remote procedure calls while local communications between tasks take place via shared memory. The method of partitioning used in the circuit model ensures that communications between tasks take place only at defined times in the simulation sequence.     

Polynomial certificates for propositional classes

This paper studies the complexity of learning classes of expressions in propositional logic from equivalence queries and membership queries. In particular, we focus on bounding the number of queries that are required to learn the class ignoring computational complexity. This quantity is known to be captured by a combinatorial measure of concept classes known as the certificate complexity. The paper gives new constructions of polynomial size certificates for monotone expressions in conjunctive normal form (CNF), for unate CNF functions where each variable affects the function either positively or negatively but not both ways, and for Horn CNF functions. Lower bounds on certificate size for these classes are derived showing that for some parameter settings the new certificate constructions are optimal. Finally, the paper gives an exponential lower bound on the certificate size for a natural generalization of these classes known as renamable Horn CNF functions, thus implying that the class is not learnable from a polynomial number of queries.