An iterative merging algorithm for soft rectangle packing and its extension for application of fixed-outline floorplanning of soft modules

We address an important variant of the rectangle packing problem, the soft rectangle packing problem, and explore its problem extension for the fixed-outline floorplanning with soft modules. For the soft rectangle packing problem with zero deadspace, we present an iterative merging packing algorithm that merges all the rectangles into a final composite rectangle in a bottom-up order by iteratively merging two rectangles with the least areas into a composite rectangle, and then shapes and places each pair of sibling rectangles based on the dimensions and position of their composite rectangle in an up-bottom order. We prove that the proposed algorithm can guarantee feasible layout under some conditions, which are weaker as compared with a well-known zero-dead-space packing algorithm. We then provide a deadspace distribution strategy, which can systematically assign deadspace to modules, to extend the iterative merging packing algorithm to deal with soft packing problem with deadspace. For the fixed-outline floorplanning with soft modules problem, we propose an iterative merging packing based hierarchical partitioning algorithm, which adopts a general hierarchical partitioning framework as proposed in the popular PATOMA floorplanner. The framework uses a recursive bipartitioning method to partition the original problem into a set of subproblems, where each subproblem is a soft rectangle packing problem and how to solve the subproblem plays a key role in the final efficiency of the floorplanner. Different from the PATOMA that adopts the zero-dead-space packing algorithm, we adopt our proposed iterative merging packing algorithm for the subproblems. Experiments on the IBM-HB benchmarks show that the proposed packing algorithm is more effective than the zero-dead-space packing algorithm, and experiments on the GSRC benchmarks show that our floorplanning algorithm outperforms three state-of-the-art floorplanners PATOMA, DeFer and UFO, reducing wirelength by 0.2%, 4.0% and 2.3%, respectively.     

Corner block list representation and its application with boundary constraints

Floorplanning is a critical phase in physical design of VLSI circuits. The stochastic optimization method is widely used to handle this NP-hard problem. The key to the floorplanning algorithm based on stochastic optimization is to encode the floorplan structure properly. In this paper, corner block list (CBL)-a new efficient topological representation for non-slicing floorplan-is proposed with applications to VLSI floorplan. Given a corner block list, it takes only linear time to construct the floorplan. In floorplanning of typical VLSI design, some blocks are required to satisfy some constraints in the final packing. Boundary constraint is one kind of those constraints to pack some blocks along the pre-specified boundaries of the final chip so that the blocks are easier to be connected to certain I/O pads. We implement the boundary constraint algorithm for general floorplan by extending CBL. Our contribution is to find the necessary and sufficient characterization of the blocks along the boundary repre     

A modified simulated annealing algorithm and an excessive area model for floorplanning using fixed-outline constraints

Outline-free floorplanning focuses on area and wirelength reductions, which are usually meaningless, since they can hardly satisfy modern design requirements. We concentrate on a more difficult and useful issue, fixed-outline floorplanning. This issue imposes fixed-outline constraints on the outline-free floorplanning, making the physical design more interesting and challenging. The contributions of this paper are primarily twofold. First, a modified simulated annealing (MSA) algorithm is proposed. In the beginning of the evolutionary process, a new attenuation formula is used to decrease the temperature slowly, to enhance MSA’s global searching capacity. After a period of time, the traditional attenuation formula is employed to decrease the temperature rapidly, to maintain MSA’s local searching capacity. Second, an excessive area model is designed to guide MSA to find feasible solutions readily. This can save much time for refining feasible solutions. Additionally, B*-tree representation is known as a very useful method for characterizing floorplanning. Therefore, it is employed to perform a perturbing operation for MSA. Finally, six groups of benchmark instances with different dead spaces and aspect ratios—circuits n10, n30, n50, n100, n200, and n300—are chosen to demonstrate the efficiency of our proposed method on fixed-outline floorplanning. Compared to several existing methods, the proposed method is more efficient in obtaining desirable objective function values associated with the chip area, wirelength, and fixed-outline constraints.     

一种基于加强三维模型细节的形状分布检索算法*

基于形状分布算法提出了一种加强细节检索的算法。该算法首先将经过预处理的模型分割为N个子模块并分别进行特征提取,然后构造每个子模块的形状分布直方图,最后通过比较子模块的相似度来计算模型的相似度。该算法相比形状分布算法比较准确地计算出了模型间的相似性,有效地提高了细节的分辨,解决了外形相近但细节不同的问题。     

利用公共子序列求解固定边框布图问题

提出一种新的固定边框的布图算法．该算法采用SP表示方法,以公共子序列为基础,在随机搜索过程中限定布图宽度的变化,从而使减小芯片面积的目标与固定边框的目标在一定程度上取得一致．与现有的固定边框布图算法相比,文中算法在边框更紧凑、宽长比更大的条件下具有更高的成功率和更短的运行时间．此外,文中算法在布图初始阶段就可以对固定边框的合理性进行评估,避免了因给定的边框不合理而带来的时间上的浪费．     

一种用于片上网络布图规划的改进模拟退火与粒子群混合算法

智能优化算法作为解决大规模集成电路芯片设计中布图规划问题的经典方法已被研究多年。结合异构三维片上网络布图问题的具体特点,采用B*-tree间接描述布图问题中的解结构,针对模拟退火收敛速度慢、优化效率低的缺点,对搜索策略和概率性的劣向转移作出了改进,并将改进后的模拟退火思想引入粒子群优化算法中,使结合后的算法结合了粒子群并行计算的特点和模拟退火能够实现全局优化的特点。通过仿真实验验证,所提出的该混合改进算法在解决布图问题中要优于传统模拟退火算法。     

应用于三维集成电路解析式布局的层分配算法

层分配是解析式三维集成电路布局算法中的关键一步。解析式布局需要通过层分配将连续的三维空间中的单元划分到二维的芯片层上,这个过程会破坏之前三维空间中得到的连续解。为了实现从优化的三维布局到合法的多层二维结构的平滑过渡,提出一种使用最小代价流的层分配方法,尽可能地继承三维优化结果,保护解空间。将此层分配算法嵌入到多层次的解析式三维集成电路布局算法中,以总线长和穿透硅通孔数目的加权总和为目标,面积密度为约束条件,对比当前其他三维布局算法,该算法得到较好的线长结果、穿透硅通孔数量和运行时间。     

A heuristic block-loading algorithm based on multi-layer search for the container loading problem

This paper presents an efficient heuristic block-loading algorithm based on multi-layer search for the three-dimensional container loading problem. First, a basic heuristic block-loading algorithm is introduced. This algorithm loads one block, determined by a block selecting algorithm, in one packing phase, according to a fixed strategy, until no blocks are available. Second, the concept of composite block is introduced, the difference between traditional block and composite block being that composite block can contain multiple types of boxes in one block under some restrictions. Third, based on the depth-first search algorithm, a multi-layer search algorithm is developed for determining the selected block in each packing phase, and making this result closer to the optimal solution. Computational results on a classic data set show that the proposed algorithm outperforms the best known algorithm in almost all the test data.     

结合垂直通孔分配的层次式三维混合布局算法

采用层次式方法,分而治之,减小了电路的设计规模,非常适用于大规模的混合模式布局,并且在布局阶段结合了垂直通孔的分配问题.布局阶段的通孔分配问题不仅使得三维布局问题得以简化,而且为布线做好了准备,减少了后面的调整,是布线阶段垂直通孔分配问题的良好指导.提出了2种垂直通孔分配算法:比较精确的匈牙利近似算法;比较快速的邻域搜索方法.将这2种算法与层次式三维混合模式布局流程紧密结合,有效地解决了三维混合模式布局问题.     

General Floorplans with L/T-Shaped Blocks Using Corner Block List

With the recent advent of deep submicron technology and new packing schemes, the components in the integrated circuit are often not rectangular. On the basis of the representation of Corner Block List （CBL）, we propose a new method of handling rectilinear blocks. In this paper, the handling of the rectilinear blocks is simplified by transforming the L/T- shaped block problem into the Mign-abutment constraint problem. We devise the block rejoining process and block alignment operation for forming the L/T-shaped blocks into their original configurations. The shape flexibility of the soft blocks, and the rotation and reflection of L/T-shaped blocks are exploited to obtain a tight packing. The empty rooms are introduced to the process of block rejoining. The efficiency and effectiveness of the proposed method are demonstrated by the experimental results on a set of some benchmark examples.     

Fixed-outline floorplanning using robust evolutionary search

Typical floorplanning concerns a series of objectives, such as area, wirelength, and routability, etc., with various aspect ratios of modules in a free-outline regime. However, in a hierarchical design flow for very large ASICs and SoCs, a floorplan can be completely useless for a situation where its outline is dissatisfied. In this paper, we study the fixed-outline floorplanning problem that is more applicable to the hierarchical design style. We develop an efficient algorithm based on robust evolutionary search and achieve substantially improved success rate. We also propose a new approach to handle soft modules to further adjust the generated floorplan to fit into the prescribed chip outline. The effectiveness of our methods is demonstrated on several large cases of MCNC and GSRC benchmarks.     

3D floorplanning of low-power and area-efficient Network-on-Chip architecture

Network-on-Chip (NoC) architectures have been adopted by chip multi-processors (CMPs) as a flexible solution to the increasing delay in the deep sub-micron regime. However, the shrinking feature size limits the performance of NoCs due to power and area constraints. In this paper, we propose three 3D floorplanning methods for a Triplet-based Hierarchical Interconnection Network (THIN) which is a new high performance NoC. The proposed floorplanning methods use both Manhattan and Y-architecture routing architectures so as to improve the performance, reduce the power consumption and area requirement of THIN. A cycle accurate simulator was developed based on Noxim NoC simulator and ORION 2.0 energy model. The proposed floorplanning methods show up to 24.69% energy and 8.84% area reduction at best compared with 3D Mesh. Our analysis concludes that THIN is not only a feasible but also a low-power and area-efficient NoC at physical level.     

Self-adaptive sampling rate assignment and image reconstruction via combination of structured sparsity and non-local total variation priors

Compressive sensing (CS) is an emerging approach for acquisition of sparse or compressible signals. For natural images, block compressive sensing (BCS) has been designed to reduce the size of sensing matrix and the complexity of sampling and reconstruction. On the other hand, image blocks with varying structures are too different to share the same sampling rate and sensing matrix. Motivated by this, a novel framework of adaptive acquisition and reconstruction is proposed to assign sampling rate adaptively. The framework contains three aspects. First, a small part of sampling rate is employed to pre-sense each block and a novel approach is proposed to estimate its compressibility only from pre-sensed measurements. Next, two assignment schemes are proposed to assign the other part of the sampling rate adaptively to each block based on its estimated compressibility. A higher sampling rate is assigned to incompressible blocks but a lower one to compressible ones. The sensing matrix is constructed based on the assigned sampling rates. The pre-sensed measurements and the adaptive ones are concatenated to form the final measurements. Finally, it is proposed that the reconstruction is modeled as a multi-objects optimization problem which involves the structured sparsity and the non-local total variation prior together. It is simplified into a 3-stage alternating optimization problem and is solved by an augmented Lagrangian method. Experiments on four categories of real natural images and medicine images demonstrate that the proposed framework captures local and nonlocal structures and outperforms the state-of-the-art methods.     

Hierarchical congregated ant system for bottom-up VLSI placements

A new perturbation method, called Hierarchical-Congregated Ant System (H-CAS) has been proposed to perform the variable-order bottom-up placement for VLSI. H-CAS exploits the concept of ant colonies, where each ant will generate the perturbation based on differences in dimensions of the VLSI modules in hard modules floorplanning and differences in area of the VLSI modules in soft modules floorplanning. In this paper, it is mathematically proved that the area-based two-dimensional cost function for hard modules floorplanning problem can be reduced to the difference-based one dimensional cost function which avoids local optima problems. Lack of global view is a major drawback in the conventional bottom-up hierarchy, and hence, ants in the H-CAS are made to introduce global information at every level of bottom-up hierarchy. A new relative whitespace formula for bottom-up hierarchy is derived mathematically and the H-CAS embeds it in its unique update formula. The ants in H-CAS are able to communicate among themselves and update the pheromone trails when they reach the destination. Then, the ants will congregate, share their experiences and construct a new pheromone trails that belong to this newly constructed group. The congregation of at least two ants and/or ant consortiums would lead to reduction in subsequent search space and complexity. H-CAS gives the best-so-far near optimal solutions and yields low standard deviations of areas involving 9–600 blocks based on Microelectronics Center of North Carolina (MCNC) and Giga scale Systems Research Center (GSRC) benchmarks. The results obtained establish that H-CAS is a high performance placer in respect of scaling, convergence, precision, stability, and reliability. The above claims are based on the comparisons with the other floorplanning algorithms as depicted graphically.     

An efficient heuristic algorithm for arbitrary shaped rectilinear block packing problem

Arbitrary shaped rectilinear block packing problem is a problem of packing a series of rectilinear blocks into a larger rectangular container, where arbitrary shaped rectilinear block is a polygonal block whose interior angle is either 90° or 270°. This problem involves many industrial applications, such as VLSI design, timber cutting, textile industry and layout of newspaper. Many algorithms based on different strategies have been presented to solve it. In this paper, we proposed an efficient heuristic algorithm which is based on principles of corner-occupying action and caving degree describing the quality of packing action. The proposed algorithm is tested on six instances from literatures and the results are rather satisfying. The computational results demonstrate that the proposed algorithm is rather efficient for solving the arbitrary shaped rectilinear block packing problem.     

基于运动筛选和3D卷积的视频早期烟雾检测

To solve the problem of high false alarm and high missed detection in the complex environment of early smoke detection based on video, a method based on motion extraction of suspected areas is proposed and a multi-scale 3D convolutional neural network with input of 6 frames（6M3DC） is designed for video smoke detection. Firstly, the motion regions are obtained through the background difference model after average filtering and the positions of the block in which the motion regions are located are calculated, and then the motion blocks are extracted by color judgment and mean HASH algorithm and the nonconforming blocks are updated to the background image. Finally, by combining the suspected blocks of the same region of 6 consecutive frames as the input for the 3D convolutional neural network for detection, blocks detected as smoke are marked and non-smoke blocks are updated to the background image. The experimental results show that the algorithm is adaptive to slow moving smoke and can detect smoke in complex environment.     

基于对可编程逻辑块建模的FPGA通用装箱算法

装箱是FPGA工艺映射中的最后一步流程。该文提出了一种全新的对FPGA可编程逻辑块进行功能级建模的方法，并给出了基于此建模的通用性装箱算法FDUPack。实验中应用该建模方法对几种不同类型的FPGA的逻辑块进行建模，并使用装箱算法将大量的测试电路装箱到这些不同的逻辑块中，经过与已有的针对某一特定结构的装箱算法比较，该算法体现了很好的通用性。     

Efficient implementations of construction heuristics for the rectilinear block packing problem

The rectilinear block packing problem is a problem of packing a set of rectilinear blocks into a larger rectangular container, where a rectilinear block is a polygonal block whose interior angle is either 90° or 270°. There exist many applications of this problem, such as VLSI design, timber/glass cutting, and newspaper layout. In this paper, we design efficient implementations of two construction heuristics for rectilinear block packing. The proposed algorithms are tested on a series of instances, which are generated from nine benchmark instances. The computational results show that the proposed algorithms are especially efficient for large instances with repeated shapes.     

求解二维矩形Packing面积最小化问题的动态归约算法

二维矩形Packing 面积最小化问题(rectangle packing area minimization problem,简称RPAMP)是具有NP难度的高复杂度的布局优化问题,也是大规模集成电路设计中floorplanning 问题的一个核心问题.通过动态构造矩形框的宽和高,将求解一个RPAMP 转化为求解一组二维矩形Packing 判定问题(rectangle packing decision problem,简称RPDP).在求解RPDP 的最大适配度算法的基础上,进一步考虑了当前动作对全局紧凑性的影响,评估了当前动作对局部空间的损害程度,设计了求解RPDP 的最小损害度算法.然后,结合矩形框宽、高的动态构造方法,设计得到求解RPAMP 的最终算法.对15 个相关的RPAMP 算例(包括著名的MCNC 算例和GSRC 算例)进行了测试.更新了其中9 个算例的最好记录,另有2 个与当前的最好记录持平.得到了98.50%的平均填充率,将国内外文献中已见报道的最高平均填充率提高了0.85%.     

三维矩形块布局的序列三元组编码方法

解空间的序列对编码方法是解二维矩形体聚块布局问题的完整且有限(P-admissible)的编码方法.它产生于直观的分划过程(gridding procedure).受二维序列对编码方法的启示,对三维矩形聚块布局问题,也应该存在序列三元组编码方法.然而将直观分划过程直接推广到三维空间是困难的.通过对序列和部分序列的运算和分析,得到了三维矩形块聚块布局的序列三元组编码方法,此编码方法是完整且有限的.