Finding the optimal tradeoff between area and delay in multiple constant multiplications

Over the years many efficient algorithms for the multiplierless design of multiple constant multiplications (MCMs) have been introduced. These algorithms primarily focus on finding the fewest number of addition/subtraction operations that generate the MCM. Although the complexity of an MCM design is decreased by reducing the number of operations, their solutions may not lead to an MCM design with optimal area at gate-level since they do not consider the implementation costs of the operations in hardware. This article introduces two approximate algorithms that aim to optimize the area of the MCM operation by taking into account the gate-level implementation of each addition and subtraction operation which realizes a constant multiplication. To find the optimal tradeoff between area and delay, the proposed algorithms are further extended to find an MCM design with optimal area under a delay constraint. Experimental results clearly indicate that the solutions of the proposed algorithms lead to significantly better MCM designs at gate-level when compared to those obtained by the solutions of algorithms designed for the optimization of the number of operations.     

Graph-based evolutionary design of arithmetic circuits

We present an efficient graph-based evolutionary optimization technique, called evolutionary graph generation (EGG), and the proposed approach is applied to the design of combinational and sequential arithmetic circuits based on parallel counter-tree architecture. The fundamental idea of EGG is to employ general circuit graphs as individuals and manipulate the circuit graphs directly using new evolutionary graph operations without encoding the graphs into other indirect representations, such as the bit strings used in genetic algorithm (GA) proposed by Holland (1992) and trees used in genetic programming (GP) proposed by Koza et al. (1997). In this paper, the EGG system is applied to the design of constant-coefficient multipliers and the design of bit-serial data-parallel adders. The results demonstrate the potential capability of EGG to solve the practical design problems for arithmetic circuits with limited knowledge of computer arithmetic algorithms. The proposed EGG system can help to simplify and speed up the process of designing arithmetic circuits and can produce better solutions to the given problem     

Designing generic algorithms for operations research

Design solutions have been proposed to implement generic data structures, however such techniques dedicated to algorithms are not well known. This article discusses various recurrent problems encountered when designing reusable, extensible algorithms for operations research. It explains how to use object‐oriented concepts and the notion of genericity to design algorithms that are independent of the data structures and the algorithms they use, but that can still interact deeply with them. An object‐oriented design is sometimes considered to be less efficient than a classical one, and operations research is one of these scientific fields where efficiency really matters. Hence, the main goal of this article is to explain how to design algorithms that are both generic and efficient. It also discusses specific recurring design issues for operations research software and proposes solutions that improve the genericity of the algorithms. Copyright © 2005 John Wiley & Sons, Ltd.     

An on-chip signal suppression countermeasure to power analysis attacks

There are several attacks that exploit the presence of side channels in hardware implementations of cryptographic algorithms to extract secret data. Differential power analysis (DPA) and simple power analysis (SPA) attacks sense the power consumption of the hardware to extract the secret cryptographic key. These attacks either directly examine the power traces or carry out statistical operations on the power traces obtained from the hardware while executing the cryptographic algorithm. This paper presents a circuit that can be added to crypto-hardware to suppress information leakage through the power supply pin side channel. We discuss the design, simulation results and the limitations of the suppression circuit. We show that this countermeasure significantly increases the number of power trace samples required to undertake a DPA attack. The countermeasure does not require any assumptions about the design of the hardware under protection.     

Partial-DNA cyclic memory for bio-inspired electronic cell

Genome memory is an important aspect of electronic cells. Here, a novel genome memory structure called partial-DNA cyclic memory is proposed, in which cells only store a portion of the system’s entire DNA. The stored gene number is independent of the scale of embryonic array and of the target circuit, and can be set according to actual demand in the design process. Genes can be transferred in the cell and the embryonics array through intracellular and intercellular gene cyclic and non-cyclic shifts, and based on this process the embryonic array’s functional differentiation and self-repair can be achieved. In particular, lost genes caused by faulty cells can be recovered through gene updating based on the remaining normal neighbor cells during the self-repair process. A reliability model of the proposed memory structure is built considering the gene updating method, and depending on the implementations of the memory, the hardware overhead is modeled. Based on the reliability model and hardware overhead model, we can find that the memory can achieve high reliability with relatively few gene backups and with low hardware overhead. Theoretical analysis and a simulation experiment show that the new genome memory structure not only achieves functional differentiation and self-repair of the embryonics array, but also ensures system reliability while reducing hardware overhead. This has significant value in engineering applications, allowing the proposed genome memory structure to be used to design larger scale self-repair chips.     

Modeling Combinational Circuits Using Linear Word-level Structures

In many applications of circuit design and synthesis, it is natural and in some instances essential to manipulate logic functions and model circuits using word-level representations and arithmetic operations in contrast to bit-level representations and logic operations. This paper reviews linear word-level structures and formulates their properties for combinational circuit modeling. The paper addresses the following problem: given a library of gates with their corresponding word-level representations such as linear arithmetic expressions or respective graph structures, find a word-level model of an arbitrary combinational circuit/netlist using that library of gates and minimizing memory allocation and time delay requirements. We present a comprehensive study on linearization assuming various circuit processing strategies. In particular, we develop a new approach to manipulate linear word-level representations by means of cascades. The practical applicability of linear structures and developed algorithms is strengthen by considering the problem of timing analysis. All this is supported by the experimental study on benchmark circuits.     

Efficient editing of solid models by exploiting structural and spatial locality

Computer aided design systems based on solid modellers must provide fast visual feedback to users when objects are edited. This implies that boundary representations must be updated rapidly, because displays typically are generated in current-generation modellers from face, edge and vertex data.This paper describes algorithms for updating a boundary representation when an object's constructive solid geometry (CSG) representation is edited. The algorithms exploit the structural (representational) locality inherent in most object modifications by taking advantage of previously computed boundary representations for (sub-) objects that are not affected by the editing operations. They also exploit spatial locality by re-computing boundaries only within the spatial region where changes can occur. The algorithms are efficient, and are guaranteed to produce valid solids because they are based on CSG.     

Design principles of adaptive control systems for telerobots

An approach to design telerobots with variable parameters was previously presented [Slutski, Presence 6 (3), 255–267], which is intended to solve manipulation problems when fast transportation operations are combined with high precision positioning operations. Manipulator gain was used as a parameter for the flexible control of the system characteristics that introduced an additional channel of parameter adjustment into the system. This article presents design features of these systems that are based on the fact that a specific kind of adaptive algorithms obtained causes a special design for system hand controllers. The efficiency of these on-line systems with sufficiently simple control algorithms is shown with the help of semi-natural simulation and investigation of actual industrial robot control.     

小面积高性能的SHA-1/SHA-256/SM3IP复用电路的设计

Hash算法的快速发展导致了两个问题,一个是旧算法与新算法在应用于产品时更新换代的问题,另一个是基于应用环境的安全性选择不同算法时的复用问题。为解决这两个问题,实现了SHA-1/SHA-256/SM3算法的IP复用电路,电路采用循环展开方式,并加入流水线的设计,在支持多种算法的同时,还具有小面积高性能的优势。首先,基于Xilinx Virtex-6FPGA对电路设计进行性能分析,电路共占用776Slice单元,最大吞吐率可以达到0.964Gbps。然后,采用SMIC 0.13μm CMOS工艺实现了该设计,最后电路的面积是30.6k门,比单独实现三种算法的电路面积总和减小了41.7%,工作频率是177.62 MHz,最大吞吐率达到1.34Gbps。     

Goalie: A Space Efficient System for VLSI Artwork Analysis

Advances in VLSI have resulted in more and more complex circuitry, fueling the need for programs that analyze IC mask artwork. This article describes Goalie, an artwork analysis system, by explaining the algorithms used to support circuit extraction, Boolean geometric operations, connectivity analysis, capacitance measurement and design checking. Tests on several systems have shown that Goalie runs at least as fast as algorithms currently in use, but it requires less main memory, so large layouts can be handled on small computers, or even on personal workstations.     

A graph-theoretic model for optimizing queries involving methods

Traditional algorithms for optimizing the execution order of joins are no more valid when selections and projections involve methods and become very expensive operations. Selections and projections could be even more costly than joins such that they are pulled above joins, rather than pushed down in a query tree. In this paper, we take a fundamental look at how to approach query optimization from a top-down design perspective, rather than trying to force one model to fit into another. We present a graph model which is designed to characterize execution plans. Each edge and each vertex of the graph is assigned a weight to model execution plans. We also design algorithms that use these weights to optimize the execution order of operations. A cost model of these algorithms is developed. Experiments are conducted on the basis of this cost model. The results show that our algorithms are superior to similar work proposed in the literature. Received 20 April 1999 / Accepted 9 August 2000 Published online 20 April 2001     

Joint operations algorithm for large-scale global optimization

Large-scale global optimization (LSGO) is a very important but thorny task in optimization domain, which widely exists in management and engineering problems. In order to strengthen the effectiveness of meta-heuristic algorithms when handling LSGO problems, we propose a novel meta-heuristic algorithm, which is inspired by the joint operations strategy of multiple military units and called joint operations algorithm (JOA). The overall framework of the proposed algorithm involves three main operations: offensive, defensive and regroup operations. In JOA, offensive operations and defensive operations are used to balance the exploration ability and exploitation ability, and regroup operations is applied to alleviate the problem of premature convergence. To evaluate the performance of the proposed algorithm, we compare JOA with six excellent meta-heuristic algorithms on twenty LSGO benchmark functions of IEEE CEC 2010 special session and four real-life problems. The experimental results show that JOA performs steadily, and it has the best overall performance among the seven compared algorithms.     

Implicit matrix multiplication with maximum accuracy on various transputer networks

The majority of numerical algorithms employs floating-point vector and matrix operations. On a parallel computer these algorithms should be solved fastand reliably in order to avoid a time-consuming error analysis. The XSC-languages (high-level language extensions for eXtended Scientific Computation) are well-suited for this purpose since they support the design of numerical algorithms delivering correct and automatically verified results. This goal is attained by an arithmetic with maximum accuracy (especially for vector and matrix operations), highly accurate standard functions, and exact evaluation of dot product expressions. Within theESPRIT Parallel Computing Action, one XSC-language, PASCAL-XSC, was implemented on a Supercluster Transputer System under the operating system HELIOS. Parallel algorithms for computationally intensive and maximally accurate matrix operations were implemented and tested on various transputer architectures. We will sketch some features of these architectures and present some benchmarks for the algorithms used. These algorithms form a parallel C runtime library of PASCAL-XSC (or any other XSC-language that uses a C runtime library) and are called automatically. This can be considered a basis for implicit parallelization in an XSC-language.     

Hitest: A Knowledge-Based Test Generation System

Efforts to develop computer-based automatic test generation for digital circuits have been generally unsuccessful, except in the case of combinational circuitry. Current ATPG methods for sequential circuits often require a considerable amount of computer time and generate unstructured test waveforms of limited value. Experienced human test programmers, on the other hand, appear to have little difficulty in generating high-quality tests for complex sequential circuits when they have a good understanding of how the circuit operates. This article considers the causes of failure in automatic test generation algorithms and describes a new system called Hitest. This system lets the computer use human understanding of circuit operations to generate more effective tests.     

Fault Tolerance Using Dynamic Reconfiguration on the POEtic Tissue

Fault tolerance is a crucial operational aspect of biological systems and the self-repair capabilities of complex organisms far exceeds that of even the most advanced electronic devices. While many of the processes used by nature to achieve fault tolerance cannot easily be applied to silicon-based systems, in this paper we show that mechanisms loosely inspired by the operation of multicellular organisms can be transported to electronic systems to provide self-repair capabilities. Features such as dynamic routing, reconfiguration, and on-chip reprogramming can be invaluable for the realization of adaptive hardware systems and for the design of highly complex systems based on the kind of unreliable components that are likely to be introduced in the not-too-distant future. In this paper, we describe the implementation of fault tolerant features that address error detection and recovery through dynamic routing, reconfiguration, and on-chip reprogramming in a novel application specific integrated circuit. We take inspiration from three biological models: phylogenesis, ontogenesis, and epigenesis (hence the POE in POEtic). As in nature, our approach is based on a set of separate and complementary techniques that exploit the novel mechanisms provided by our device in the particular context of fault tolerance.     

Scheduler-oriented algorithms to improve human–machine cooperation in transportation scheduling support systems

A decision support system designed to enhance human–machine interaction in transportation scheduling is proposed. We aim to integrate human factors and ergonomics from the beginning of the design phase and to propose a system fitted with enough flexibility to be able to deal with the characteristics of a dynamic context such as transportation scheduling. In this interdisciplinary approach, a link is done between problem solving methods (operations research technics and data classification algorithms) and human–machine interaction (solving control modes). A set of scheduler-oriented algorithms favoring human–machine cooperation for problem solving is proposed. Some of these algorithms have been efficiently tested on instances of the literature. Finally, an original framework aiming to assist scheduler in constraint relaxation when the problem becomes infeasible is proposed and evaluated.     

Nature inspired algorithms to optimize robot workcell layouts

Multi-objective layout optimization methods for the conceptual design of robot cellular manufacturing systems are proposed in this paper. Robot cellular manufacturing systems utilize one or more flexible robots which can carry out a large number of operations, and can conduct flexible assemble processes. The layout design stage of such manufacturing systems is especially important since fundamental performances of the manufacturing system under consideration are determined at this stage. Layout area, operation time and manipulability of robot are the three important criteria when it comes to designing manufacturing system. The use of nature inspired algorithms are not extensively explored to optimize robot workcell layouts. The contribution in this paper is the use of five nature-inspired algorithms, viz. genetic algorithm (GA), differential evolution (DE), artificial bee colony (ABC), charge search system (CSS) and particle swarm optimization (PSO) algorithms and to optimize the three design criteria simultaneously. Non-dominated sorting genetic algorithm-II is used to handle multiple objectives and to obtain pareto solutions for the problems considered. The performance of sequence pair and B*-Tree layout representation schemes are also evaluated. It is found that sequence pair scheme performs better than B*-Tree representation and it is used in the algorithms. Numerical examples are provided to illustrate the effectiveness and usefulness of the proposed methods. It is observed that PSO performs better over the other algorithms in terms of solution quality.     

系统异构冗余容错设计研究

提出了一种新的三模异构冗余自修复系统的设计方法,设计出了异构评价函数。利用演化硬件具有自适应与自修复的功能,实现了具有N模冗余特性的三模冗余电路。首先,利用遗传算法进化出3个原始功能电路;然后,每进化出一个具有相同功能的电路进行一次非相似度评价,选择出非相似度最大的3个电路保留,并进行应用。当3个异构电路中有一个出错后,对故障电路屏蔽,可进化修复该出错电路,并重新投入运行。从而大大地提高了容错性能,且具有体积小、成本低、功耗小、不影响系统正常运行等优点。利用现场可编程逻辑门阵列(FPGA)对二位比较器进行容错设计验证,分析比较了非相似度评价在异构设计中的作用与影响,实验结果证明了新方法的可行性和电路的高度可靠性。     

Efficient data parallel algorithms for multidimensional array operations based on the EKMR scheme for distributed memory multicomputers

Array operations are useful in a large number of important scientific codes, such as molecular dynamics, finite element methods, climate modeling, atmosphere and ocean sciences, etc. In our previous work, we have proposed a scheme of extended Karnaugh map representation (EKMR) for multidimensional array representation. We have shown that sequential multidimensional array operation algorithms based on the EKMR scheme have better performance than those based on the traditional matrix representation (TMR) scheme. Since parallel multidimensional array operations have been an extensively investigated problem, we present efficient data parallel algorithms for multidimensional array operations based on the EKMR scheme for distributed memory multicomputers. In a data parallel programming paradigm, in general, we distribute array elements to processors based on various distribution schemes, do local computation in each processor, and collect computation results from each processor. Based on the row, column, and 2D mesh distribution schemes, we design data parallel algorithms for matrix-matrix addition and matrix-matrix multiplication array operations in both TMR and EKMR schemes for multidimensional arrays. We also design data parallel algorithms for six Fortran 90 array intrinsic functions: All, Maxval, Merge, Pack, Sum, and Cshift. We compare the time of the data distribution, the local computation, and the result collection phases of these array operations based on the TMR and the EKMR schemes. The experimental results show that algorithms based on the EKMR scheme outperform those based on the TMR scheme for all test cases.