功率MOSFET寄生电容劣化对开关瞬态响应的影响

为解决功率MOSFET寄生电容劣化影响寿命的问题,在MOSFET非线性模型基础上,深入分析MOSFET寄生电容参数和开关管瞬态响应信号之间的关系,推导了各参数和瞬态响应之间的关系表达式,并用Saber仿真实验进行验证。由于栅极对MOSFET的性能影响至关重要,所以此次实验分析了和栅极相关的栅源电容Cgs和栅漏电容Cgd。结果表明,在寄生参数相同劣化程度时,栅源电容对瞬态响应的影响达到7.08%,而栅漏电容近似只有1.6%。栅源电容的劣化更大程度上影响瞬态响应,为MOSFET劣化提供了新的研究思路。     

IGBT全桥穿通特性及退化分析

绝缘栅双极型晶体管(IGBT)在桥式电路中的穿通现象会使得同一桥臂的两个IGBT同时导通,发生短路烧毁。利用Simulink软件对IGBT电路进行仿真分析,通过实验电路对IGBT实际工作进行测试及比较,探讨了母线电压、栅极电阻、栅-射极间并联电容对IGBT感应栅压的影响;并对桥式结构中IGBT各电参数的退化情况进行详细地分析,可得:母线电压对感应栅压的大小基本无影响;栅极电阻与感应栅压呈正相关;栅-射极间并联电容越大,感应栅压越小;集电极漏电流和通态电阻退化明显。并根据分析讨论结果,给出优化方案,对提高桥式结构中IGBT的可靠性有着重要意义。     

空间电容式分压装置高压探头电容稳定性的研究

运用模拟电荷法和有限元分析软件ANSYS对空间电容式分压装置的电容特性进行了数值计算,并对几种典型因素的影响进行了模拟计算.计算表明,在一定的环境条件下,这种分压装置能够提供较好的电容稳定性.     

面向低压高频开关应用的功率JFET的功耗

提出了一种埋氧化物槽栅双极模式功率JFET(BTB-JFET),其面向低压高频开关应用。首次通过仿真对BTB-JFET、常规的槽栅双极模式JFET(TB-JFET)和槽栅MOSFET(T-MOSFET)等20V级的功率开关器件在高频应用时的功率损耗进行了比较。仿真中借鉴现有的高性能T-MOSFET的结构尺寸,并采用了感性负载电路对器件进行静态以及混合模式的电特性仿真,结果表明,常开型BTB-JFET与TB-JFET相比,零偏压时栅漏电容CGD减小25%;当工作频率为1MHz和2MHz时常开型TB-JFET与T-MOSFET相比总功耗分别降低了14%和19%,而常开型BTB-JFET较TB-JFET的总功耗又进一步降低了6%。仿真结果还表明,在不同工作频率下,常闭型JFET的性能都不如T-MOSFET。样管初步测试结果证明,常开型BTB-JFET与TB-JFET相比,零偏压时栅漏电容CGD减小45%,与仿真结果相一致。     

一种电流型D类功放高频自激驱动电路

为了解决物理美容设备中电流型D类功放自激驱动栅源电压过高的问题,设计了一种实用电流型D类功放的高频自激驱动电路。通过改变电路中直流偏置电压、MOS管驱动级的电容、漏源间的电容以及两管漏极间电容、供电电压的方法,解决驱动栅源电压过高的问题。通过理论和试验分析,完成电路的设计。通过试验,做到了栅源电压不超过±30V,谐振频率可以达到2MHz左右。该电路具有分离元件少,结构简单,效率高等优点。将该电路实际应用到一款物理美容设备中时,达到了很好的消脂、美白、嫩肤效果。     

同轴结构半径突变处补偿电容的计算分析

若同轴结构的横向尺寸远小于电磁波的波长,半径突变处电场畸变的影响可以等效为一个补偿电容。利用分离变量法,推导出了同轴结构半径突变处补偿电容的精确计算模型,计算分析了半径变化对补偿电容值的影响规律,并与有限元软件对比,验证了计算模型的正确性。同时讨论了平行平板结构尺寸突变处补偿电容计算公式近似应用于同轴结构时的适用性,并给出了一个计算实例分析补偿电容对时域波形的影响。     

基于回转器-电容模型的变压器漏感的研究

回转器-电容模型是一种较新的描述磁性元件的电路模型.本文根据能量相等的基本原理推导变压器漏感在回转器-电容模型中的表现形式.文中具体给出了几种典型变压器的漏感能量求法,并对应回转器-电容模型给出了表征漏磁通的漏磁导电容值的求法;讨论了变压器绕组采用交错换位绕法后漏磁通发生的变化.通过一个立式变压器、平面变压器验证了漏磁导电容计算方法的有效性.     

多极少槽永磁同步电动机齿顶漏磁的计算与分析

多极少槽永磁同步电动机其磁场分布比较复杂,不仅存在传统意义上的极间漏磁和端部漏磁,还包括齿顶漏磁,因此准确计算该类电机的漏磁因数非常重要。本文应用Ansoft软件对多极少槽电动机的磁场进行模拟,得出了齿顶漏磁的分布情况,总结出了含有齿顶漏磁的永磁同步电动机漏磁因数的计算方法,计算结果与试验值比较吻合。     

排汽缸与末级叶片耦合流动的整周数值模拟

使用CFD数值模拟软件CFX对某型号汽轮机的低压排汽缸和末级叶栅耦合流动进行整周数值计算。与单独计算排汽缸流场相比,排汽缸和末级叶栅耦合计算考虑了末级排汽对排汽缸内流场的影响。耦合计算的叶栅流道计算域可以采用单通道建模,也可以采用整周建模。与单通道叶栅建模相比,整周耦合计算能够减小周期性交界面引起的参数传递误差。因此,整周耦合计算能够模拟出更接近实际应用的排汽缸进口压力和速度分布,从而获得更加准确的排汽缸内流动情况,进一步提高排汽缸性能预估的准确度。     

极槽数相近的永磁同步电动机漏磁因数分析与计算

永磁同步电动机的漏磁因数对电动机中永磁材料的利用率、抗去磁能力和电动机的性能有较大的影响.对于永磁电动机不仅存在传统意义上的极间漏磁和端部漏磁,还包括齿顶漏磁,因此准确计算极槽数相近的电动机的漏磁因数非常重要.利用Ansoft软件对极槽数相近的电动机的磁场进行模拟,研究了齿顶漏磁的分布情况,总结出漏磁因数的计算方法.计算数值与试验值比较吻合.     

Controlling the ON-resistance in SOI LDMOS using parasitic bipolar junction transistor

We present a new parasitic bipolar junction transistor (BJT) enhanced silicon on insulator (SOI) laterally double diffused metal oxide semiconductor (LDMOS), called BJT enhanced LDMOS (BE-LDMOS). The proposed device utilizes the parasitic BJT present in an LDMOS to increase the drain current for a given gate voltage, resulting in a reduction in the ON-resistance by 26.2 % and improving the switching speed by 7.8 % for BE-LDMOS as compared to the comparable LDMOS. These improvements are without degradation in other performance parameters such as off state breakdown voltage and transconductance. The process steps for fabricating BE-LDMOS are same as that for LDMOS except for an additional metal contact.     

Characterization of Total Safe Operating Area of Lateral DMOS Transistors

The total safe operating area (SOA) of LDMOS transistors is discussed. It is shown that the transistors are subjected to different kinds of stresses, yielding a combination of electrical and thermal degradation and/or failure modes. A methodology to build the total SOA for LDMOS transistors is highlighted and is experimentally verified on a 40-V LDMOS implemented in a     

A modified LDMOS device with improved ESD protection performance

A modified lateral‐diffusion metal–oxide–semiconductor (MLDMOS) device with improved electrostatic discharge (ESD) protection performance is proposed for high‐voltage ESD protection. In comparison with the traditional LDMOS and the LDMOS with an embedded silicon‐controlled rectifier (LDMOS‐SCR), the proposed device has better ESD robustness and higher holding voltage. By optimizing key parameters, such as the spacing between the drain and the poly gate, the effective channel length, and the number of fingers, the MLDMOS can achieve a maximum failure current over 80 mA/µm, which is larger than that of LDMOS‐SCR. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

ESD robustness improvement for integrated DMOS transistors —the different gate‐voltage dependence of It2 between VDMOS and LDMOS transistors

This paper presents the device‐level electrostatic discharge (ESD) robustness improvement for integrated vertical double‐diffused MOS (VDMOS) and lateral double‐diffused MOS (LDMOS) transistors by changing device structure. The ESD robustness of VDMOS transistor was improved by preventing current concentration and that of LDMOS transistor was improved by relaxing the electric field under the LOCOS oxide. We found the different gate‐voltage dependence of the second breakdown current (I_t2) between VDMOS and LDMOS transistors. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

分布式源场极板结构射频LDMOS器件的设计

为了减小射频LDMOS器件中场极板寄生电容,提出一种具有分布式源场极板结构的射频LDMOs器件,给出了器件结构及工艺流程。借助微波EDA软件AWR对场极板进行了三维电磁仿真优化设计。仿真及测试结果表明,所设计的分布式源场极板结构在不影响器件击穿电压的条件下,能有效减小LDMOS器件寄生电容,提升器件增益、效率及线性度等射频性能。     

Safe Operating Area Considerations for Integrated Trench-Based Power Devices

This paper discusses the hot-carrier and electrical safe operating area (SOA) of trench-based integrated power devices. The hot-carrier SOA is determined by the avalanche current, exhibiting a maximum at intermediate drain voltage. The initial hot-carrier degradation is dependent on the crystal plane on which the gate oxide is grown. During hot-carrier stress, interface states are formed in the device's accumulation region. No channel degradation is observed. The electrical SOA of the trench-based MOS (TB-MOS) is much larger than a comparable lateral DMOS (LDMOS) or vertical DMOS (VDMOS). Even for 100-ns pulses, the TB-MOS exhibits electrothermal effects, contrary to LDMOS and VDMOS. Finally, the intrinsic gate oxide quality of the trench gate oxide is reported on. It is proven that the oxide time-dependent dielectric breakdown is determined by the thinnest oxide along the trench sidewall.      

A new technique to measure the thermal resistance of LDMOS transistors

This paper introduces a new dc technique for the extraction of the thermal resistance of LDMOS transistors. The new extraction method has distinctive advantages over existing techniques: 1) it is based on dc measurements of the I-V output curves at different ambient temperatures, thus requiring only very standard and inexpensive equipment, with the exception of a stable and accurate temperature control; 2) it does not need any special layout or test structure, nor any knowledge of the physical structure of the device under test; and 3) it can be applied to both packaged and on-wafer FETs. We applied the new technique to LDMOS transistors with a wide range of gate widths, namely, 2.68-84.42 mm, obtaining well-behaved and consistent results. A comparison of the new method with a standard extraction technique based on short-pulse measurements at different ambient temperatures showed substantial agreement between the two.     

A novel deep gate power MOSFET in partial SOI technology for achieving high breakdown voltage and low lattice temperature

We propose a novel deep gate lateral double diffused metal-oxide-semiconductor (LDMOS) field-effect transistor in partial silicon-on-insulator (PSOI) technology for achieving high breakdown voltage and reduced power dissipation. In the proposed device, an N⁺ well is inserted in the buried oxide under the drain region. By optimizing the N⁺ well and the lateral distance between the buried oxide and the left side of the device, the electric field is modified. Therefore, the breakdown voltage improves. Also, the PSOI technology used in the proposed structure has a significant effect on reducing the lattice temperature. Our simulation results show that the proposed structure improves the breakdown voltage by about 67.5% and reduces the specific on-resistance by about 20% in comparison with a conventional LDMOS.

     

An embedded β-Ga2O3 layer in a SOI-LDMOS to improve breakdown voltage

Journal of Computational Electronics - In this work, we present a novel silicon-on-insulator (SOI) laterally diffused metal–oxide–semiconductor (LDMOS) using β-Ga2O3 material...     

A TCAD approach for non-linear evaluation of microwave power transistor and its experimental verification by LDMOS

A simulation technique is developed in TCAD to study the non-linear behavior of RF power transistor. The technique is based on semiconductor transport equations to swot up the overall non-linearity’s occurring in RF power transistor. Computational load-pull simulation technique (CLP) developed in our group, is further extended to study the non-linear effects inside the transistor structure by conventional two-tone RF signals, and initial simulations were done in time domain. The technique is helpful to detect, understand the phenomena and its mechanism which can be resolved and improve the transistor performance. By this technique, the third order intermodulation distortion (IMD₃) was observed at different power levels. The technique was successfully implemented on a laterally-diffused field effect transistor (LDMOS). The value of IMD₃ obtained is −22 dBc at 1-dB compression point (P _{1 dB}) while at 10 dB back off the value increases to −36 dBc. Simulation results were experimentally verified by fabricating a power amplifier with the similar LDMOS transistor.