0.5‐V fractional‐order companding filters

Novel configurations of fractional‐order filter topologies, realized through the employment of the concept of companding filtering, are introduced in this paper. As a first step, the design procedure is presented in a systematic algorithmic way, while in the next step, the basic building blocks of sinh‐domain and log‐domain integrators are presented. Because of the employment of metal–oxide–semiconductor (MOS) transistors operated in the subthreshold region, the derived filter structures offer the capability for operation in an ultra‐low‐voltage environment. In addition, because of the offered resistorless realizations, the proposed topologies are reconfigurable, in the sense that the order of the filter could be chosen through appropriate bias current sources. The performance of the derived fractional‐order filters has been evaluated through simulation and comparison results using the Analog Design Environment of the Cadence software and MOS transistor parameters provided by the Taiwan Semiconductor Manufacturing Company (TSMC) 180‐nm complementary MOS (CMOS) process. Copyright © 2014 John Wiley & Sons, Ltd.     

Balanced Gm‐C filters with improved linearity and power efficiency

A novel G_m‐C filter design technique is presented. It is based on floating‐gate metal oxide semiconductor (FGMOS) transistors and consists in a topological rearrangement of conventional fully differential G_m‐C structures without modifying the employed transconductors at transistor level. The proposed method allows decreasing the number of active elements (transconductors) of the filter. Moreover, high linearity is obtained at low and medium frequencies of the pass band. Drawbacks inherent to the use of FGMOS transistors are analyzed, such as large occupied area, high sensitivity to mismatch, or parasitic zeros in transfer functions. The features of the proposed technique are fully exploited in all‐pole G_m‐C filter design, specially implementing unity gain Butterworth transfer functions. Thus, two low‐power second‐order Butterworth G_m‐C filters have been designed and fabricated to compare the proposed FGMOS technique with their equivalent topologies obtained by a conventional design method. Measurement results for a test chip prototype in a 0.5‐µm standard complementary MOS process are presented, confirming the advantages of the proposed FGMOS design technique. Copyright © 2014 John Wiley & Sons, Ltd.     

Simple and accurate approaches to implement the complex trans‐conductance suited for time‐domain simulators for small‐signal and large‐signal table‐based models

This paper focuses on the implementation of table‐based models of high‐frequency transistors for time‐domain simulators at microwave and mm‐wave frequencies. In this frequency range, the channel is not capable of responding to the excitation instantaneously therefore, a delay‐time exists between the channel response and the channel excitation. This delay is represented by a complex trans‐conductance in terms of circuit elements. The high‐frequency models of transistors are required to have the implementation of complex trans‐conductance, where the complex part accounts mathematically for the delay‐time between the channel response and the channel excitation. This paper presents simple and accurate approaches to incorporate the complex trans‐conductance in both small‐signal and large‐signal table‐based models for time‐domain simulators (MOS‐AK International Meeting. Eindhoven, Netherlands, April 2008). Implementation approach for each model, small‐signal and large‐signal, is presented in separated sections. In the first step, the delay is realized by the introduction of an ideal transmission line between the channel excitation and the channel response. As transmission lines are not generally suitable for time‐domain simulations, a lumped element equivalent network is introduced in the second step. The latter approach is fully compatible with time‐domain simulators but frequency limitation, determined by the delay‐time value itself, is introduced. Then the implementation of the complex trans‐conductance in large‐signal model is introduced. In terms of large‐signal behavior, delay‐time is important to achieve a non‐quasi static model. Yet again there is limitation in terms of the frequency range that is determined by the delay value itself. The methodology is illustrated on the small‐signal and the large‐signal equivalent circuit of a Multi‐Fin MOSFET transistor. Simulations are carried out by Cadence Spectre and Agilent ADS simulators, and comparisons are carried out between the simulation results and the measurements. Copyright © 2010 John Wiley & Sons, Ltd.     

An equivalent‐circuit modelling on vertical and horizontal integrations for MOS flat‐band voltage simulation

The fixed oxide charge will cause the MOS capacitor (MOS‐C) flat‐band voltage to shift. We can observe the potential distribution to determine the MOS‐C flat‐band voltage. However, the potential distribution can be obtained from the integration of the electric field distribution. The integration of the electric field distribution is classified into the vertical and horizontal integrations. In this paper, we use the equivalent‐circuit model to demonstrate the flat‐band voltage of the non‐ideal MOS‐C. The equivalent‐circuit model of Poisson's equation includes two fixed charges Q′_f1 and Q′_f2 in the oxide layer region. Because the horizontal integration method is the superposition method, the equivalent‐circuit model for the horizontal integration is divided into 3 types. Hence, the flat‐band voltage for the horizontal integration is equal to the sum of the V_G1, V_G2, and V_G3 for the flat‐band condition. By comparison, the simulation results of the horizontal integration method approximate to the vertical integration method. Copyright © 2006 John Wiley & Sons, Ltd.     

Modeling the threshold voltage of PNIN SSOI tunnel field‐effect transistor

In this paper, a physically based analytical threshold voltage model for PNIN strained‐silicon‐on‐insulator tunnel field‐effect transistor (PNIN SSOI TFET) is proposed by solving the two‐dimensional (2D) Poisson equation in narrow N⁺ layer and intrinsic region. In the proposed model, the effect of strain (in terms of equivalent Ge mole fraction), narrow N⁺ layer and gate dielectric, and so on, is being considered. The validity of the proposed model is verified by comparing the model results with 2D device simulation results. It is demonstrated that the proposed model can correctly predicts the trends in threshold voltage with varying the device parameters. This proposed model can be effectively used to design, simulate, and fabricate the PNIN SSOI TFETs with the desired performance. Copyright © 2015 John Wiley & Sons, Ltd.     

Minimal two‐transistor multifunction filter design

This paper presents a comprehensive method and analysis on the design of two‐transistor multi‐output filters where three possible functions are simultaneously available. Although two transistors are employed at its core, proper biasing does not require additional passive components. A total of thirteen valid second‐order filters are reported, and several of them are experimentally tested using discrete transistors as well as simulated using Spectre in a BiCMOS process. A fully differential realization of a MOS‐C band‐pass filter, based on one of the structures found, is designed and then used to realize a fourth‐order Chebyshev band‐pass filter. Copyright © 2017 John Wiley & Sons, Ltd.     

Experimental comparison of phase‐noise in cross‐coupled RC‐ and LC‐oscillators

Relaxation RC‐oscillators are notorious for their poor phase‐noise performance. However, there are reasons to expect a phase‐noise reduction in quadrature oscillators obtained by cross‐coupling two relaxation oscillators. We present measurements on 5 GHz oscillators, which show that in RC‐oscillators the coupling reduces both the phase‐noise and quadrature error, whereas in LC‐oscillators the coupling reduces the quadrature error, but increases the phase‐noise. A comparison using standard figures of merit indicates that quadrature RC‐oscillators may be a viable alternative to LC‐oscillators when area and cost are to be minimized. Copyright © 2009 John Wiley & Sons, Ltd.     

Modelling,design and realization of micromachined millimetre‐wave band‐pass filters

This paper describes the design, the realization and the experimental characterization of a micromachined band‐pass filter with a working frequency of 38GHz. The synthesis of the structure has been carried out by means of the image parameter representation of two‐port networks. A coupled line coplanar configuration has been adopted for the filtering network. The good agreement between theoretical and experimental results demonstrates the validity of the proposed design approach. Copyright © 2003 John Wiley & Sons, Ltd.     

Numerical characterization of nonlinear oscillatory waves in a composite right‐ and left‐handed traveling‐wave field‐effect transistor

A specialized type of traveling‐wave field‐effect transistor, the gate and drain lines of which have composite right‐ and left‐handed structures, is considered as the platform to support nonlinear oscillatory waves. The cubic–quintic complex Ginzburg–Landau equation is obtained by application of the reductive perturbation method, by which we quantify the homogeneous oscillations including the property of the Andronov–Hopf bifurcation point, oscillation frequency, and amplitude. Several numerical calculations follow to validate the Ginzburg–Landau equation‐based analysis. Finally, the dynamics of numerically obtained stationary flat‐top pulses are discussed. Copyright © 2016 John Wiley & Sons, Ltd.     

MTL‐based implementation of current‐mode CMOS RMS‐to‐DC converters

In this paper, systematic implementation of current‐mode RMS‐to‐DC converters based upon MOS translinear (MTL) principle, utilizing symmetric cascoded MTL cell (SCMC) is proposed. Theory of operation and mathematical analysis of both explicit (direct) and implicit (indirect) techniques for realization of SCMC‐based RMS‐to‐DC converters are discussed. The SCMC includes a folded MTL loop and realizes an MTL equation. MTL principle utilizes the square law characteristics of saturated MOS transistors to realize square‐root domain (SRD) functions. The SCMC is constructed by two connected cascoded current mirrors and has a compact, symmetric, and multi‐purpose structure, with capability of implementing the circuits into the programmable and configurable structures. The proposed RMS‐to‐DC converters utilize the SCMC along with a configurable current mirror array. The required squaring and square‐rooting functions are realized using the SCMC, after proper configuration of the current mirror array. The proposed circuits have been implemented using a reconfigurable architecture fabricated in a 0.5 µm CMOS technology. Copyright © 2014 John Wiley & Sons, Ltd.     

Soft computing‐based approach for optimal design of on‐chip comparator and folded‐cascode op‐amp using colliding bodies optimization

This paper presents an efficient approach for the optimal designs of two analog circuits, namely complementary metal oxide semiconductor) two‐stage comparator with p‐channel metal oxide semiconductor input driver and n‐channel input and folded‐cascode operational amplifier using a recently proposed meta‐heuristic‐based optimization algorithm named as colliding bodies optimization (CBO). It is a multi‐agent algorithm that does not depend upon any internal control parameter, making the algorithm extremely simple. The main objective of this paper is to optimize the metal oxide semiconductor (MOS) transistors' sizes using CBO in order to reduce the areas occupied by the circuits and to get better performance parameters of the circuits. Simulation Program with Integrated Circuit Emphasis simulation has been carried out by using the optimal values of MOS transistors' sizes and other design parameters to validate that CBO‐based design is satisfying the desired specifications. Simulation results demonstrate that the design specifications are closely met and the required functionalities are achieved. The simulation results also confirm that the CBO‐based approach is superior to the other algorithms in terms of MOS area and performance parameters like gain, power dissipation, etc., for the examples considered. Copyright © 2016 John Wiley & Sons, Ltd.     

On the two‐port network analysis of common amplifier topologies

Using two‐port network transmission parameters, we derive exact expressions for the voltage/current gains and the input/output impedances of common amplifier topologies. The derived expressions are valid both for BJT and MOS‐based amplifiers and are independent of any particular small signal transistor model. Copyright © 2009 John Wiley & Sons, Ltd.     

Observer design for neutral‐type neural networks with discrete and distributed time‐varying delays

This paper is concerned with the problem of state estimation for a class of neural networks with discrete and distributed interval time‐varying delays. We propose a new approach of nonlinear estimator design for the class of neutral‐type neural networks. By constructing a newly augmented Lyapunov‐Krasovskii functional, we establish sufficient conditions to guarantee the estimation error dynamics to be globally exponentially stable. The obtained results are formulated in terms of linear matrix inequalities (LMIs), which can be easily verified by the MATLAB LMI control toolbox. Then, the desired estimators gain matrix is characterized in terms of the solution to these LMIs. Three numerical examples are given to show the effectiveness of the proposed design method.     

Adaptive finite‐dimensional optimal linear filtering of nD smooth Gaussian random fields

This paper deals with the optimal filtering problem of nD sampled, Gaussian random fields. The filtering algorithm is based on a state‐space signal model analytically derived from the assumption that the continuous Gaussian random field can be well approximated, almost everywhere, by a continuously differentiable nD surface. An appealing feature of the proposed optimal filter is that it is not based on nD strip processing schemes. The filtering algorithm has a structure which is recursive both with respect to the point‐to‐point scanning procedure of the sampled field and to the dimensionality of the estimate computed at each point. This greatly reduces the numerical complexity of the filtering scheme. The filtering algorithm requires the knowledge of some statistical parameters of the random field. For a greater generality, a procedure for the adaptive estimation of these parameters is also provided. Numerical results are reported to illustrate the applicability and performance of the proposed filter. Copyright © 2006 John Wiley & Sons, Ltd.     

Filter & hold: a mixed continuous‐/discrete‐time technique for time‐constant scaling

The work reported in this paper introduces a periodic switching technique applied to continuous‐time filters, whose outcome is an equivalent filter with scaled time‐constants. The principle behind the method is based on a procedure that extends the integration time by periodically interrupting the normal integration of the filter. The net result is an up scaling of the time constant, inversely proportional to the switching duty‐cycle. This is particularly suitable for reducing the area occupied by passive devices in integrated circuits, as well as to accurately calibrate the filter dynamics. Previous works have been following this concept in an entirely continuous‐time perspective, either focusing on specific circuits or using approximations to provide an extended analysis. This paper includes input/output sampling to derive a closed‐form representation for the scaling technique herein coined as ‘Filter & Hold’ (F&H). A detailed mathematical analysis is described, demonstrating that the F&H concept represents an exact filtering solution. Simulation results and experimental measurements are provided to further validate the theoretical analysis for an F&H vector‐filter prototype. Copyright © 2014 John Wiley & Sons, Ltd.     

DC–3 GHz low‐noise,flat‐gain‐response,and high‐linearity amplifier

This paper describes the design, fabrication, and testing of a DC–3 GHz ultra‐wideband low‐noise amplifier (LNA) using Avago ATF‐54143 enhanced‐mode pseudomorphic high‐electron mobility transistor. Negative feedback network is introduced to ensure unconditional stability of the LNA over the full waveband. Simulation results show that the LNA provides a gain varying between 14.872 and 14.052 dB, a noise figure (NF) of less than 2.2 dB, and voltage standing wave ratios (VSWRs) approaching 2. A high simulated output third‐order intercept point (OIP₃) of >30.2 dBm is achieved. In contrast, in 1‐dB bandwidth of DC–3 GHz, the measured gain is nominal at 13.10 dB. The obtained NF changes in a small range of 2–2.178 dB, and the measured VSWRs are no more than 1.64, which are better than obtained from simulation results. At the same time, OIP₃ at 1, 2, and 3 GHz is 30.3, 29.13, and 29.34 dBm, respectively, while the output at the 1‐dB compression point (P _1dB ) is 15.43, 14.83, and 14.33 dBm, respectively. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

An approach to model high‐frequency distortion in negative‐feedback amplifiers

In this paper, we present an analytical approach to study the harmonic distortion in the frequency domain of operational amplifiers (opamps) embedded in a nonlinear feedback network. The analysis is based on a frequency‐domain block scheme that models the opamp with one block and the feedback network with two blocks, but it is demonstrated that only one feedback block needs to be characterized for the two basic inverting and non‐inverting configurations. The obtained closed‐form expressions extend our understanding of nonlinear frequency behaviour in feedback opamp circuits. Indeed, they give the contribution of each network component to the output distortion. As an instructive example, we analysed second‐ and third‐order harmonic distortion of an active‐RC inverting lossy integrator having all the components nonlinear. The accuracy of the proposed method is confirmed by comparison with computer simulations at transistor level. Copyright © 2006 John Wiley & Sons, Ltd.     

State‐space equations of regular and strictly topologically degenerate linear lumped time‐invariant networks: the multiport method

A new complete approach to the multiport formulation of the state‐space equations of uniquely solvable regular or strictly topologically degenerate linear lumped time‐invariant networks is presented. It is based on a Gedankenexperiment during which the topological structure of the original network is manipulated in various ways. The final method requires one to calculate the describing matrices of three homogeneous multiports (i.e. a capacitive, an inductive and a resistive one), which are obtained from the network of interest in a very simple manner. As a by‐product, the equivalent partitioned network is also derived. As an example of application, the state‐space equations of a fourth‐order strictly topologically degenerate network are provided. Copyright © 2001 John Wiley & Sons. Ltd.     

Neural‐network‐based finite‐time H∞ control for extended Markov jump nonlinear systems

This paper presents a neural‐network‐based finite‐time H_∞ control design technique for a class of extended Markov jump nonlinear systems. The considered stochastic character is described by a Markov process, but with only partially known transition jump rates. The sufficient conditions for the existence of the desired controller are derived in terms of linear matrix inequalities such that the closed‐loop system trajectory stays within a prescribed bound in a fixed time interval and has a guaranteed H_∞ noise attenuation performance for all admissible uncertainties and approximation errors of the neural networks. A numerical example is used to illustrate the effectiveness of the developed theoretic results. Copyright © 2009 John Wiley & Sons, Ltd.