A low‐voltage band‐gap reference circuit with second‐order analyses

A new band‐gap reference (BGR) circuit employing sub‐threshold current is proposed for low‐voltage operations. By employing the fraction of V_BE and the sub‐threshold current source, the proposed BGR circuit with chip area of 0.029mm² was fabricated in the standard 0.18µm CMOS triple‐well technology. It generates reference voltage of 170 mV with power consumption of 2.4µW at supply voltage of 1 V. The agreement between simulation and measurement shows that the variations of reference voltage are 1.3 mV for temperatures from ?20 to 100^°C, and 1.1 mV per volt for supply voltage from 0.95 to 2.5 V, respectively. Copyright © 2010 John Wiley & Sons, Ltd.     

A CMOS voltage regulator for passive RFID tag ICs

A low‐power voltage regulator for passive RFID tag ICs is proposed in this paper. It consists of a self‐biased mutually compensated voltage reference, a low dropout (LDO) voltage regulation circuit and a power‐on‐reset (POR) circuit. It is fabricated in a commercial 0.18?µm CMOS technology and applied to a passive UHF RFID tag IC. The total quiescent current is 700 nA under a 1.8‐V supply. The output voltage of the regulator is 1.45 V with load capability of 50 µA. The temperature coefficients of the voltage reference and the output voltage are only 9 and 43 ppm/^°C, respectively. A POR signal with width pulse of 150 ns is generated for the digital part in the tag IC. Copyright © 2010 John Wiley & Sons, Ltd.     

A linear,ultra wideband,low‐power, 2.1–5 GHz,VCO

A linear, Ultra Wideband, low‐power VCO, suitable for UWB‐FM applications is proposed, forming the main part of a UWB‐FM transmitter. The VCO is designed in TSMC 90thinspacenm digital CMOS process and includes a Source‐Coupled Multivibrator, used as current‐controlled oscillator (CCO) which generates output frequencies between 2.1 and 5 GHz and a voltage‐to‐current (V‐to‐I) converter which translates the VCO input voltage modulation signal to current. Two single‐ended inverter buffers are employed to drive either a differential or a single‐ended UWB antenna. The presented VCO is designed for 1 V power supply and exhibits a linear tuning range of 2.1–5 GHz, a differential output power of ?7.83 dBm±0.78 dB and low power consumption of 8.26 mW, including the output buffers, at the maximum oscillation frequency. It is optimized for a very high ratio of tuning range (81.69%) over power consumption equal to 9.95 dB. The desired frequency band of 3.1–5 GHz for UWB‐FM applications is covered for the entire industrial temperature range (?40 to 125^°C). Copyright © 2010 John Wiley & Sons, Ltd.     

A 0.75‐V, 4‐μW, 15‐ppm/°C, 190 °C temperature range,voltage reference

A low‐voltage, low‐power, low‐area, wide‐temperature‐range CMOS voltage reference is presented. The proposed reference circuit achieves a measured temperature drift of 15 ppm/°C for an extremely wide temperature range of 190 °C (?60 to 130 °C) while consuming only 4 μW at 0.75 V. It performs a high‐order curvature correction of the reference voltage while consisting of only CMOS transistors operating in subthreshold and polysilicon resistors, without utilizing any diodes or external components such as compensating capacitors. A trade‐off of this circuit topology, in its current form, is the high line sensitivity. The design was fabricated using TowerJazz semiconductor's 0.18‐µm standard CMOS technology and occupies an area of 0.039 mm². The proposed reference circuit is suitable for high‐precision, low‐energy‐budget applications, such as mobile systems, wearable electronics, and energy harvesting systems. Copyright © 2015 John Wiley & Sons, Ltd.     

A high‐order curvature‐corrected CMOS bandgap voltage reference with constant current technique

A high‐order curvature‐corrected complementary metal–oxide–semiconductor (CMOS) bandgap voltage reference (BGR), utilizing the temperature‐dependent resistor and constant current technique, is presented. Considering the process variation, a resistor trimming network is introduced in this work. The circuit is implemented in a standard 0.35‐µm CMOS process. The measurement results have confirmed that the proposed BGR operates with a supply voltage of 1.8 V, consuming 45 μW at room temperature (25 °C), and the temperature coefficient of the output voltage reference is about 5.5 ppm/°C from −40 °C to 125 °C. The measured power supply rejection ratio is −38.8 dB at 1 kHz. The BGR is compatible with low‐voltage and low‐power circuit design when the structure of operational amplifiers and all the devices in the proposed bandgap reference are properly designed. Copyright © 2012 John Wiley & Sons, Ltd.     

A picopower temperature‐compensated,subthreshold CMOS voltage reference

A voltage reference consisting of only two nMOS transistors with different threshold voltages is presented. Measurements performed on 23 samples from a single batch show a mean reference voltage of 275.4 mV. The subthreshold conduction and the low number of transistors enable to achieve a mean power consumption of only 40 pW. The minimum supply voltage is 0.45 V, which coincides with the lowest value reported so far. The mean TC in the temperature range from 0 to 120 °C is 105.4 ppm/°C, while the mean line sensitivity is 0.46%/V in the supply voltage range 0.45–1.8 V. The occupied area is 0.018 mm². The power supply rejection rate without any filtering capacitor is ?48 dB at 20 Hz and ?29.2 dB at 10 kHz. Thanks to large area transistors and to a careful layout, the coefficient of variation of the reference voltage is only 0.62%. We introduce as a new figure of merit, the voltage temperature parameter (VTP), which gives a direct measure of the overall percentage variation of the reference voltage on the typical 2D domain of supply voltage and temperature. For the proposed circuit, the average VTP is 1.70% with a standard deviation of 0.21%. In order to investigate the effect of transistor area on process variability, a 4X replica of the proposed configuration has been fabricated and tested as well. Except for LS, the 4X replica doesn't exhibit any appreciable improvement with respect to the basic voltage reference. Copyright © 2013 John Wiley & Sons, Ltd.     

A portable class of 3‐transistor current references with low‐power sub‐0.5 V operation

This work proposes a new class of current references based on only 3 transistors that allows sub‐0.5 V operation. The circuit consists of a 2‐transistor block that generates a proportional‐to‐absolute‐temperature or a complementary‐to‐absolute‐temperature voltage and a load transistor. The idea of a 3T current reference is validated by circuit simulations for different complementary metal‐oxide‐semiconductor technologies and by experimental measurements on a large set of test chips fabricated with a commercial 0.18 μm complementary metal‐oxide‐semiconductor process. As compared to the state‐of‐art competitors, the 3T current reference exhibits competitive performance in terms of temperature coefficient (578 ppm/°C), line sensitivity (3.9%/V), and power consumption (213 nW) and presents a reduction by a factor of 2 to 3 in terms of minimum operating voltage (0.45 V) and an improvement of 1 to 2 orders of magnitude in terms of area occupation (750 μm²). In spite of the extremely reduced silicon area, the fabricated chips exhibit low‐process sensitivity (2.7%). A digital trimming solution to significantly reduce the process sensitivity is also presented and validated by simulations.     

Short‐circuit current calculation and performance requirement of HVDC breakers for MMC‐MTDC systems

To evaluate the performance requirement of high‐voltage direct current (HVDC) breakers for modular multilevel converter (MMC)‐MTDC (multi‐terminal high voltage direct current) systems with high efficiency, the equivalent model for calculating the maximum short‐circuit current is presented in this paper. First, the short‐circuit current is decomposed into the steady‐state component and the fault component according to its physical dynamics. Second, the steady‐state component is determined by solving the direct current (DC) network; the fault component is calculated by an equivalent network in which the converters are replaced by a reactance, a resistance, and a capacitance in series. Then, the complete procedure for evaluating the performance requirement of HVDC breakers is described based on short‐circuit current calculation. Verifications have been carried out based on a three‐terminal 800 MW/±400 kV bipolar MMC‐MTDC system. The results show that the proposed methodology is efficient and effective. Lastly, based on the same system, the performance requirement of HVDC breakers and the influence by the sub‐module (SM) capacitance and the smoothing reactor have been studied with the proposed methodology. © 2015 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Noise‐immune dual‐rail dynamic circuit for wide fan‐in gates in asynchronous designs

Dual‐rail dynamic logic circuits can provide inverting and noninverting outputs, especially for asynchronous designs, to implement complicated gates at the cost of approximately doubling the area and power consumption. In this paper, a new dual‐rail dynamic circuit is proposed which has lower die area consumption and higher noise immunity without dramatic speed degradation for even wide fan‐in gates for asynchronous circuits. The main idea in the proposed circuit is that voltage due to the current of the pulldown network (PDN) is compared with the reference voltage to provide two complementary outputs. The reference voltage almost corresponds to the leakage current of the PDN with all transistors being off. The proposed circuit is compared with conventional dual‐rail circuits such as differential domino logic and differential cross‐coupled domino logic. Simulation results for 32‐bit‐wide OR gates designed using high‐performance 16‐nm predictive technology model demonstrate significant performance advantages such as 66% power reduction and at least 2.86× noise‐immunity improvement at the same delay compared to the differential domino circuits. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A very low complexity IR‐UWB transmitter with BPSK modulation for balanced antenna

A very low complexity impulse radio‐ultrawideband (IR‐UWB) transmitter suitable for balanced antenna is presented. This all‐digital transmitter employs the binary phase‐shift keying (BPSK) modulation scheme and eliminates the need for a balun. Also, a new Gaussian monocycle pulse generator is proposed which is used as impulse transmitted signal. The transmitter circuit was designed in 0.18‐μm complementary metal–oxide–semiconductor technology. The post‐simulation results show that the core chip size was only 0.02 mm². The output amplitude pulse yielded 150 mV peak‐to‐peak under a supply voltage of 1.8 V. Simulation results show that the transmitter consumes 8.5 pJ/pulse for 200‐MHz pulse repeating frequency. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

0.3‐V bulk‐driven programmable gain amplifier in 0.18‐µm CMOS

A new solution for an ultra low voltage bulk‐driven programmable gain amplifier (PGA) is described in the paper. While implemented in a standard n‐well 0.18‐µm complementary metal–oxide–semiconductor (CMOS) process, the circuit operates from 0.3 V supply, and its voltage gain can be regulated from 0 to 18 dB with 6‐dB steps. At minimum gain, the PGA offers nearly rail‐to‐rail input/output swing and the input referred thermal noise of 2.37 μV/Hz^1/2, which results in a 63‐dB dynamic range (DR). Besides, the total power consumption is 96 nW, the signal bandwidth is 2.95 kHz at 5‐pF load capacitance and the third‐order input intercept point (IIP₃) is 1.62 V. The circuit performance was simulated with LTspice. Copyright © 2016 John Wiley & Sons, Ltd.     

A 5‐GHz energy‐efficient tunable pulse generator for ultra‐wideband applications using a variable attenuator for pulse shaping

A new energy‐efficient tunable pulse generator is presented in this paper using 0.13‐µm CMOS technology for short‐range high‐data‐rate 3.1–10.6 GHz ultra‐wideband applications. A ring oscillator consisting of current‐starved CMOS inverters is quickly switched on and off for the duration of the pulse, and the amplitude envelope is shaped with a variable passive CMOS attenuator. The variable passive attenuator is controlled using an impulse that is created by a low‐power glitch generator (CMOS NOR gate). The glitch generator combines the falling edge of the clock and its delayed inverse, allowing the duration of the impulse to be changed over a wide range (500–900 ps) by varying the delay between the edges. The pulses generated with this technique can provide a sharp frequency roll off with high out‐of‐band rejection to help meet the Federal Communications Commission mask. The entire circuit operates in switched mode with a low average power consumption of less than 3.8 mW at 910 MHz pulse repetition frequency or below 4.2 pJ of energy per pulse. It occupies a total area of 725 × 600 µm² including bonding pads and decoupling capacitors, and the active circuit area is only 360 × 200 µm². Copyright © 2011 John Wiley & Sons, Ltd.     

Low temperature coefficient and low line sensitivity subthreshold curvature-compensated voltage reference

A high-order curvature-compensated subthreshold voltage reference is proposed in this paper. The proposed curvature-compensated voltage reference consists of two supply-independent first-order voltage references and a curvature compensation circuit. The supply-independent first-order voltage reference uses a negative feedback loop which improves the line sensitivity and eliminates the demand of operational amplifier, whereas the curvature compensation circuit provides high-order temperature-compensated output reference voltage. The proposed curvature-compensated voltage reference provides an output reference voltage of 118.54 mV with a temperature coefficient of 21.5 ppm/°C over a wide temperature range of −60°C to 120°C . The power supply rejection ratio and line sensitivity are observed as −68.64 dB (for the frequency range of 1 Hz to 100 Hz) and 0.035%/V (for the supply voltage varies from 0.85 V to 2.5 V), respectively. The values of output noise at the frequencies of 1 kHz and 10 kHz without using any capacitive filter are obtained as 179.13 nV/ √ Hz and 123.87 nV/ √ Hz , respectively.     

A Novel Driving and Protection Circuit for Reverse-Blocking IGBT Used in Matrix Converter

A novel drive and protection circuit for reverse-blocking insulated gate bipolar transistor (RB-IGBT) is proposed in this paper. For the drive circuit, a dynamic current source is introduced to reduce the turn-on and turn-off transients. Meanwhile, the di/dt of the collector current and the dv/dt of the collector-emitter voltage are strictly restricted, so do the respective stresses. The drive circuit consists of a conventional push-pull driver and two controllable current sources-a current generator and a current sink. These two current sources work in switching transitions. For the protection circuit, a novel collector current detecting circuit suitable for RB-IGBT is proposed. This method detects the collector current by sensing collector-emitter voltage of the device. Further study shows that this method can be used to acquire the current signs in commutation transitions of matrix converter. A series of experiments has been carried out concerning the proposed drive and protection circuit and the experimental setup; results as well as detailed analysis are presented     

A novel active auxiliary circuit for efficiency enhancement integrated with synchronous buck converter

In this paper, a novel auxiliary circuit is introduced for the synchronous buck converter. This auxiliary circuit provides zero‐current, zero‐voltage switching conditions for the main and synchronous switches while providing zero‐current condition for the auxiliary switch and diodes. The proposed active auxiliary circuit integrated with synchronous buck converter that emanates to zero‐voltage transition (ZVT)–zero‐current transition (ZCT) pulse width‐modulated (PWM) synchronous buck converter is analyzed, and its operating modes are presented. The additional voltage and current stresses on main, synchronous and auxiliary switches get decimated because of the resonance of the auxiliary circuit that acts for a small segment of time in the proposed converter. The important design feature of soft‐switching converters is the placement of resonant components that mollifies the switching and conduction losses. With the advent of ZVT–ZCT switching, there is an increase in the switching frequency that declines the resonant component values in the converters and also constricts the switching losses. The characteristics of the proposed converter are verified with the simulation in the Power Sim (PSIM) software co‐simulated with MATLAB/SIMULINK environment and implemented experimentally. Copyright © 2016 John Wiley & Sons, Ltd.     

A waveform generator circuit for extra low‐frequency CMOS micro‐power applications

This paper presents a novel low‐power CMOS extra low‐frequency (ELF) waveform generator based on an operational trans‐conductance amplifier (OTA). The generator has been designed and fabricated using 2.5‐V devices available in 130‐nm IBM CMOS technology with a ±1.2‐V voltage supply. Using the same topology, two sets of device dimensions and circuit components are designed and fabricated for comparing relative performance, silicon area and power dissipation. The first design consumes 691 μW, while the second design consumes 943 μW using the same voltage supply. This low‐power performance enables the circuit to be used in many micro‐power applications. ELF oscillation is achieved for the two designs being around 3.95 Hz and 3.90 Hz, respectively, with negligible waveform distortion. The measured frequencies agree well with the simulation results. The first design is found to provide overall optimal performance compared to the second design at the expense of higher silicon area. Copyright © 2015 John Wiley & Sons, Ltd.     

A sub‐1 V nanopower temperature‐compensated sub‐threshold CMOS voltage reference with 0.065%/V line sensitivity

We present the design of a nanopower sub‐threshold CMOS voltage reference and the measurements performed over a set of more than 70 samples fabricated in 0.18 µm CMOS technology. The circuit provides a temperature‐compensated reference voltage of 259 mV with an extremely low line sensitivity of only 0.065% at the price of a less effective temperature compensation. The voltage reference properly works with a supply voltage down to 0.6 V and with a power dissipation of only 22.3 nW. Very similar performance has been obtained with and without the inclusion of the start‐up circuit. Copyright © 2013 John Wiley & Sons, Ltd.     

基于仿人智能控制算法的温度控制器设计

针对科学实验中对温度控制的需要,设计了一种基于仿人智能控制算法的温度控制器。该控制器以STC89C58单片机作为控制核心,采用热电阻Pt100、满幅运放TLC2262、3端可调恒流源LM334和12位串行模数转换器ADS1286构成温度测量电路,继电器作为执行元件控制加热器,为了提高温度测量的精度,采用REF2940作为模数转换器和信号调理电路中的基准电压。该控制器通过按键设定温度值,1602液晶实时显示温度设定值和实际温度值。水温控制实验表明,温度控制范围为40~80℃、精度为0.5℃,且不存在大的超调,控制效果良好。     

A 0.008‐mm2, 35‐μW, 8.87‐ps‐resolution CMOS time‐to‐digital converter using dual‐slope architecture

This paper presents a high resolution time‐to‐digital converter (TDC) for low‐area applications. To achieve both high resolution and low circuit area, we propose a dual‐slope voltage‐domain TDC, which is composed of a time‐to‐voltage converter (TVC) and an analog‐to‐digital converter (ADC). In the TVC, a current source and a capacitor are used to make the circuit as simple as possible. For the same reason, a single‐slope ADC, which is commonly used for compact area ADC applications, is adapted and optimized. Because the main non‐linearity occurs in the current source of the TVC and the ramp generator of the ADC, a double gain‐boosting current source is applied to overcome the low output impedance of the current source in the sub‐100‐nm CMOS process. The prototype TDC is implemented using a 65‐nm CMOS process, and occupies only 0.008 mm². The measurement result shows a dynamic range with an 8‐bit 8.86‐ps resolution and an integrated non‐linearity of ±1.25 LSB. Copyright © 2016 John Wiley & Sons, Ltd.     

Analysis and effective controller design for the cascaded H‐bridge multilevel APF with adaptive signal processing algorithms

The cascaded H‐bridge (CHB) multilevel inverter is being recognized as the most suitable topology for high‐power medium‐voltage power quality conditioning applications. This paper presents mathematical modeling and effective controller design methodology for the CHB‐based active power filters (APFs), which achieves dynamic reactive power and harmonic compensation. The most crucial problems in CHB‐APF control are the simultaneous requirements of both accurate harmonic current compensation and the dc‐link voltage stabilization among the H‐bridges, which is the prerequisite for the stable operation of CHB‐APF. To achieve dc‐link stabilization, a novel voltage balancing algorithm is proposed by splitting the dc‐link voltage control task into two parts, namely, the average voltage control and the voltage balancing control, where the sine and cosine functions of the phase angle of the fundamental component of the grid voltage are used, respectively. To ensure accurate phase tracking, a novel phase‐locked loop (PLL) is proposed by using the adaptive linear neural network (ADALINE), where the grid voltage background distortion is also taken into account. The superior performance of the ADALINE‐PLL is validated by comparison with the existing PLLs in literatures. Furthermore, the proportional‐resonant (PR) controller is used for the reference current tracking. A separate ADALINE algorithm is applied for reference current generation (RCG) for the CHB‐APF. The excellent performance of the ADALINE‐based RCG scheme is verified by comparison with the existing RCG schemes, namely, the low‐pass filter approach and the single‐phase p ? qmethod. The experimental results on the three modules CHB‐APF are presented, which verifies the effectiveness of the proposed control algorithms. Copyright © 2011 John Wiley & Sons, Ltd.