Performance of ferroelectric based tunable capacitors as a function of electrode geometry

Abstract

High quality Ba_0.4Sr_0.6TiO₃ and SrTiO₃ films were grown by Pulsed Laser Deposition on single crystal LaAlO₃ and MgO substrates. Temperature dependencies of the dielectric constant and loss tangent of the films were studied using planar interdigitated test capacitors with various electrode geometries. The temperature where the maximum or “peak” capacitance occurs (T_p and referred to as the “peak temperature”) is found to depend on the electrode geometry in these films. As much as 40 K difference in T_p was observed between the STO test capacitors with 5 μm and 40 μm gaps between electrodes. Interface built-in electric field and metal-ferroelectric thermal mismatch strain are considered as possible explanation of the effect of electrode geometry on peak temperature of the capacitors.     

圆环线匝构成的平面共模EMI滤波器的特性研究

平面LC线圈是组成平面EMI滤波器的基本单元,其匝间寄生电容及所用磁心磁导率的非线性对滤波器的高频性能有重要影响。本文首次提出环形平面LC线圈结构,并对矩形和环形平面LC线圈进行了3D有限元仿真,通过对比其特性确定了环形LC线圈作为组成EMI滤波器的基本组成单元,并基于该结构实现了平面共模EMI滤波器。考虑了匝间寄生电容、相邻导体间的互感及有效磁导率的非线性,建立了环形LC线圈的等效集中参数电路,利用节点电压法求解了当其连接成低通滤波器时的插入损耗。基于环形平面LC线圈设计了一台平面共模滤波器样机,计算与实验对比显示,匝间寄生电容和磁导率的非线性对滤波器的高频性能有重要影响。     

CIRCUIT MODELS FOR POLYPHASE INDUCTION MACHINES

ABSTRACT

For many years, induction machines operating in the balanced steady state have been represented for analysis by the conventional “T” form of equivalent circuit. Simplification of this circuit to expedite analysis has normally involved approximation This paper presents a number oE simplified equivalent circuits which preserve the accuracy of the “T” circuit and to some extent improve on it by more appropriate representation of saturation and core loss. Experimental confirmation of this improvement is included. The new circuits are denoted as “T” and “inverse-T” because of their inductance configuration.     

变压器缩尺模型声功率测量方法比较

建立一个变压器缩尺模型,在半消声室环境下,以PULSE声振采集系统为测量分析平台,输出并采集各工况下测点的噪声数据。通过比较GB/T 1094.10—2003《电力变压器 第10部分：声级测定》与GB 6882—86 《声学 噪声源声功率级的测定：消声室和半消声室精密法》2种标准测量计算的变压器辐射声功率,验证了工程测量标准GB/T 1094.10—2003的准确性和稳定性,研究了不同声学边界条件对声功率测量结果的影响。实验结果表明：防火墙对变压器辐射声功率有一定影响;不同声学边界条件下,2种测试标准声功率测量结果非常接近,且差值都在1 dB以内,表明工程测量标准GB/T 1094.10—2003的准确性和稳定性很高。     

Analysis of Hourly Demand Data before and after the 2011 Tohoku Earthquake

On March 11, 2011, the power system suffered heavy damage from the huge earthquake and tsunami in the Tohoku region. This paper describes the change of features included in the time series of open demand data for the disaster of 3/11/2011. The demand data are separated into three sections: one for the “predisaster” analysis from April 2008 to February 2011, the second for the “during‐disaster” survey from March to May 2011, and the last for the “postdisaster” analysis from June 2011 to March 2013. We distinguished the periodic components of daily, weekly, and seasonal fluctuation among the demand time series by applying a newly developed procedure, the quasi‐ideal moving average method. Some significant changes were observed in the statistics of the predisaster and postdisaster periodic component analysis. The change in temperature sensitivity was also surveyed by using open weather data for Sendai.     

Ferroelectric nonvolatile logic

Abstract

This paper describes the design of nonvolatile logic elements using ferroelectric materials. Two separate approaches are discussed. The first approach involves shadowing a CMOS latch or flip-flop with a single bit 2T/2C ferroelectric memory. The second approach offers improved density by integrating ferroelectric capacitors within the logic element. Both designs employ non-switching ferroelectric capacitors to establish the optimum bit line load in the absence of sufficient parasitic capacitance. The paper further describes low-voltage and wide-voltage design techniques used to realize 2.7 – 5.5V products on a “5-volt” ferroelectric process. These same techniques allow 1.8V ferroelectric memory products to be designed using the upcoming generation of production ready “3-volt” ferroelectric materials. Layout effects are discussed, as well as bit/cell ratio optimization.     

A T‐LCLC type immittance converter

“Immittance converter” is short for “impedance–admittance converter.” The immittance converter has an input impedance that is proportional to the admittance of the load connected across output terminals. In this converter, the output current is proportional to the input voltage and the input current is proportional to the output voltage. Consequently, it converts a constant voltage source into a constant current source and a constant current source into a constant voltage source. It is well known that the quarter‐wavelength transmission line shows immittance conversion characteristics. However, it has very long line length for the switching frequency, and is not suitable for power electronics application. Thus, we proposed immittance converters that consist of lumped elements L, C and show improved immittance conversion characteristics at a resonant frequency. In this paper, we propose a T‐LCLC‐type immittance converter, which has the transitive configuration and both advantages of T‐LCL‐ and π‐CLC‐type immittance converters. We show voltage–current transformation characteristics and frequency characteristics and efficiency characteristics of the T‐LCLC immittance converter. These characteristics were determined analytically and experimentally. © 2002 Wiley Periodicals, Inc. Electr Eng Jpn, 142(3): 57–63, 2003; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.10095     

P‐channel logic 2 T eDRAM macro with high retention bit architecture

This study presents a novel approach which enhances the data retention capability of PMOS gain cell based embedded DRAM. The proposed circuit technique utilizes a parasitic capacitance between the cell storage node and the common n‐well body. During the write operation, an up‐down voltage transition to the n‐well increases the cell storage retention time without using any optional devices. It also results in much high immunity against the write “1” disturbance. Measured and simulated results from an 8192‐wordx8‐bit eDRAM macro implemented in a 0.13‐μm generic CMOS process exhibit 58% increased retention time and approximately 3.6 times stronger write disturbance immunity over the conventional design.     

A Fail-safe Logic Operator Using an Insulated Planar Transformer

A fail-safe logic circuit must switch the output signal to the logical value “0” when an operation circuit fails. A transformer has such favorable characteristics for fail-safe logic circuits as only the magnetic flux change is transmitted and a superposition of magnetic flux is realized. Thus those characteristics arc applied to a failsafe logic operator. A new fail-safe logic operator using an insulated planar transformer was developed for a fail-safe majority operation and a fail-safe interlocking. In this paper, the principle, structure, design and fundamental characteristics of the new fail-safe logic operator are described.     

Thermal analysis of multi‐finger GaInP collector‐up heterojunction bipolar transistors with miniature heat‐dissipation packaging structures

We build up a finite element modeling (FEM) approach to analyze the thermal performance of collector‐up (C‐up) heterojunction bipolar transistor (HBTs) with a heat‐dissipation via configuration. Highly compact heat‐dissipation packaging structures of GaInP/GaAs C‐up HBTs have been designed and evaluated systematically. In this work, we devise the 2‐D and 3‐D models to simulate the actual devices and to investigate the temperature distribution behavior. Results from 2‐D model indicate that the large heat‐dissipation via configuration can be further reduced by 29% to meet the requirement of HBT‐based small high‐power amplifiers (HPAs) for the cellular phones. Furthermore, the demonstrated results show that the maximum temperature within the collector calculated from 3‐D model is lower than that from 2‐D model. In the 3‐D analysis, it is revealed that the configuration can be reduced by 32%. Therefore, thinning the heat‐dissipation via constructed underneath the GaInP/GaAs C‐up HBT should be helpful for miniaturization of HBT‐based HPAs in future mobile communication systems. Copyright © 2009 John Wiley & Sons, Ltd.     

智能网和智能业务

智能网IN（Intelligent Network)是一种能快速、方便、灵活、有效地生成和实现各种新业务的通信体系,它是在传统通信基础上发展起来的。因为IN采用提“业务控制”结构,而综合业务数字网ISDN（Integrated Service Digital Network)采用的是“业务接入”结构,所以IN比ISDN优越。为了使从事电力通信网工作的技术人员了解智能网IN,采用简单描述方法介绍智能网IN的基本概念和结构,以及我国信息产业部规范的以下7种智能业务：（1）300业务;（2）600业务;（3）800业务;（4）通用个人通信UPT业务;（5）电话投票VOT（Televoting)业务;（6）广域集中化小交换机WAC（Wide Area Centrex)业务;（7）大众呼叫MAS（Mass Calling)业务。     

输电阻塞管理的灵敏度分析模型及算法

在电力市场环境下，系统的运行方式将更加多变，发生输电阻塞的概率大为增加。文中提出了一种利用灵敏度分析进行实时阻塞管理的数学模型及算法，即在出现阻塞时，根据注入功率与支路潮流的灵敏度来削减对阻塞影响最大的发电出力或负荷，从而有效地消除阻塞。针对阻塞管理的实时性要求及阻塞只与局部电网有关的特点，采用部分求逆及稀疏矢量法等措施，使算法快速、实用。最后通过算例系统的计算，验证了所提算法的正确性和有效性。     

A new approach to an individual‐phase reactive power compensator for nonsinusoidal and unbalanced three‐phase systems

Many researchers have attempted to clarify the definitions of active power, reactive power, active current, reactive current, etc. for unbalanced and nonsinusoidal three‐phase situations. The so‐called pq theory has given a new definition of instantaneous reactive power, and it has been discussed and developed by many authors. In this paper, the merits and demerits of the instantaneous reactive power compensator are discussed. It is shown theoretically that applying instantaneous reactive power compensation to unbalanced three‐phase systems has a serious disadvantage in that it causes third‐order harmonic currents on the source side, which problem cannot be avoided. To overcome this problem the authors propose a new approach, and name it the “quasi‐instantaneous” reactive power compensator. It compensates individual‐phase reactive currents. The basic principles of the quasi‐instantaneous reactive current compensator are discussed in detail, and its validity is confirmed using digital simulation. In particular the authors show that the power factor of each phase becomes unity on the source side, but the source currents remain unbalanced when the proposed method is applied. © 2002 Wiley Periodicals, Inc. Electr Eng Jpn, 139(3): 73–81, 2002; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.1162     

H级燃机电厂低位侧排汽汽轮发电机岛区域布置设计

广州增城燃气冷热电三联供项目是国内率先投运的H级燃气—蒸汽联合循环机组工程。机组采用“1+1”多轴方案,配置低位布置的西门子SGT5-8000H型燃机和低位布置、侧排汽的西门子SST5-5000型汽机。设计院与主机厂进行了深入协作,开发并成功实施了“H级联合循环低位多轴双跨联合主厂房”方案,该方案规避了单纯对称或简单顺列布置的弊端,成为该类型机组新的优化“典型布置”方案。本文对该创新方案实施的难点之一“低位侧排汽汽轮发电机岛区域的布置设计”的特点进行论述。     

基于“负参数”理论的EMI滤波器寄生参数的双重消除

EMI滤波器是抑制传导电磁干扰的有效器件,但分立元件的自有寄生参数对其高频段性能有重要影响。本文利用两个同侧耦合电感器等效出"负电感"和在电感器中心处连接电容器等效出"负电容"的方法,消除滤波器中的寄生电感和寄生电容。为有效控制二次寄生参数对消除效果的影响,设计了一种新型平面"消除器"和双线并绕串联结构的电感器,其中前者为上、下交错排列的PCB导线构成的圆形线圈,采用3D有限元法计算了两交错线圈的互感,为设计该类消除器提供了一种数值计算方法;后者通过高耦合度的线圈中间节点与地之间接一4倍于寄生电容的电容器,可有效消除电感器的一次及二次寄生电容。将此类具有消除器的元件应用于EMI共模滤波器,以此消除对应的寄生参数,实验表明滤波器的高频性能得到了明显改善。     

应用于平面EMI滤波器集成LC元件寄生电容的提取

为有效预估和分析平面EMI滤波器的高频特性,必须考虑平面电感的寄生电容对滤波器高频性能的影响.本文分别建立了应用于平面EMI滤波器集成LC元件的2D和3D有限元静电场模型来计算各匝间的寄生电容,由此得到PCB导线组成的多匝平面绕组的集总参数模型,进一步得到平面绕组的等效并联电容.讨论了介电常数对匝间电容的影响,并分析了...     

新能源侧储能配置技术研究综述

构建以新能源为主体的新型电力系统,是能源电力行业服务碳达峰、碳中和的重要责任和使命.电网对于新能源的要求逐渐从"友好并网"提升至"友好并网+主动支撑",新能源侧标配储能成为大势所趋.储能配置是储能应用领域的前端工作,目前储能成本仍然较高,如何实现最优的储能配置是首要需解决的问题.综述并归纳了目前国内外在新能源侧储能应用...     

Comparison between different implementations of the 3D FLASH sequence for knee cartilage quantification

Objective

To compare several sequence implementations of the 3D FLASH sequence in the context of quantitative cartilage imaging.

Materials and methods

Test–retest coronal fast low angle shot (FLASH) sequences with water excitation were acquired in knees of 12 healthy participants, using two 1.5?T scanners from the same manufacturer. On one of the scanners, the FLASH was additionally compared with a FLASH VIBE, 75% with 100% slice resolution, a non-selective with a conventional spatial pulse, and “asymmetric echo allowed” with “not allowed”.

Results

Implementations of the FLASH showed systematic differences of up to 3.3%, but these were not statistically significant. Precision errors were similar between protocols, but tended to be smallest for the FLASH VIBE with 100% slice resolution (0.6–6.7%). In the medial tibia cartilage volume and thickness differed significantly (P?Conclusion Using a validated FLASH sequence, one can reduce slice resolution to 75% and allow asymmetric echo without sacrificing precision, in order to reduce the total acquisition time. However, in longitudinal studies, the scanner and the specific sequence implementation should be kept constant between baseline and follow-up, in order to avoid systematic off-sets in the measurements.     

Ferroelectric La-Sr-Co-O/Pb-La-Zr-Ti-O/La-Sr-Co-O heterostructures on silicon

Abstract

Ferroelectric Pb_0.9La_0.1Zr_0.2Ti_0.8O₃ (PLZT) thin film capacitors with symmetrical La-Sr-Co-O top and bottom electrodes have been grown on [001] Si with a Yttria stabilized zirconia (YSZ) buffer layer and on SiO₂Si substrates. A layered perovskite “template” layer (300–500 Å thick), grown between the YSZ buffer layer or the SiO₂ layer and the bottom La-Sr-Co-O electrode, is critical for obtaining the required orientation of the subsequent layers. The fatigue, retention and aging characteristics of these new structures are quite desirable for nonvolatile memory operation. Preliminary studies show that this ferroelectric performance obtained in large (50–100 μm diameter) capacitors can be replicated in smaller capacitors (down to 4 μm diameter) processed by ion milling.