基于多相滤波结构的Zoom FFT及其FPGA实现

针对传统Zoom FFT算法运算量大、处理速度低的缺点,本文提出了一种适合于FPGA芯片实现Zoom FFT算法的结构,对这种结构进行了设计并用FPGA实现了该结构。在硬件实现时,改进了传统的多相滤波器的硬件实现方法,并将改进的多相滤波器和DDS技术应用到Zoom FFT的设计中。设计实例和硬件测试结果表明,这种结构与传统的Zoom FFT实现方法相比,占用FPGA资源少,处理速度快。     

基于FPGA的电压闪变测量模块的设计与优化

电压闪变作为电能质量一项重要指标,国际电工委员会(IEC)为其提供了专门的测量模型。系统采用可编程逻辑器件FPGA作为数字处理核心,在ICE标准下,设计并优化了电压闪变的测量模块,主要包括IIR型数字滤波器的设计和实现,并用MATLAB和Modelsim对模型进行了仿真,验证了模块正确性和准确性,最后运用系统进行实际测量,分析了测量误差并对误差进行分段校正,提高了测量精度。     

基于FPGA的GHz宽带中频数字采集系统的设计

针对大带宽复杂电磁信号的测试分析,介绍了一种基于FPGA的GHz带宽中频数字采集系统的设计,论述了系统的硬件总体设计和信号处理算法设计方案。采集系统ADC以1.6GHz采样率对中频信号进行采样,然后通过FPGA进行数字信号处理,通过对传统多相滤波算法的改进,设计了FPGA的高速大带宽信号的数字滤波方案,并采用多路并行处理的方法设计了高速数字正交混频算法,实现了最大为640 MHz的分析带宽和带内多路信号分析的功能。     

Low-complexity distributed parallel processor for 2D IIR broadband beam plane-wave filters

Real-time systolic-array-based implementations of VLSI two-dimensional (2D) infinite-impulse-response (IIR) frequency-planar beam plane-wave filters have potentially wide applications in the filtering of spatio-temporal RF broadband plane waves based on their directions of arrival (DOAs). Distributed-parallel-processor (DPP) implementations of the systolic arrays allow synchronous sampling of the 2D input signal array, but because of the direct-form structure they have high circuit complexity. To address the high-complexity problem, the differential-form 2D z-domain transfer function is employed here to obtain a novel DPP systolic-array-based filter architecture. Differential operators are obtained by applying elemental predistortion to the passive LR prototype filter network using series-connected negative-resistance elements. The proposed systolic 2D IIR architecture is implemented on a single Xilinx Virtex-4 Xc4v Sx35-10ff668 FPGA chip. Two examples of broadband plane-wave filtering supporting N = 32 and N = 64 sensors are reported. On-chip test results are achieved using stable real-time tests at frame sample frequencies of up to 90MHz as well as stepped hardware cosimulation in conjunction with a parallel-operating MATLAB/Simulink simulation.     

基于FPGA的飞行校验多模信号采集与处理设计

针对仪表着陆系统(ILS)、甚高频全向信标(VOR)等的飞行校验需求,设计了一种基于FPGA的多模信号采集与处理系统。选用普通导航接收机接收信号,以FPGA作为逻辑和时序控制核心。系统包含了模拟信号调理和A/D转换、无线电系统总线(RSB)接口、ARINC 429总线接口、USB总线接口等的相应软硬件设计,首次在国内提出RSB软硬件实现方案。根据ILS与VOR的信号特点,并且分析了FPGA有限字长的影响,设计了数字滤波器,实现了在FPGA上的校验信号处理。经过验证,设计能够为飞行校验平台提供有效的数据,并且具备较强的可移植性,符合要求。     

数字信号处理系统的硬件加速设计

数字信号处理是信号检测与分析领域使用的主要方法之一。首先阐述了振动信号处理系统的原理,给出了数字信号处理部分的嵌入式系统设计方案。在此基础上围绕FFT和FIR模块重点论述了如何利用Xilinx公司的ISE和EDK工具完成FIR和FFT硬件加速模块的设计,综合后系统频率达到157MHz。最后通过设计相应实验在FPGA开发板硬件平台完成系统功能和运行速率的验证,从而发现采用硬件加速模块的系统运行时间显著下降。     

Retinal blood vessel segmentation for macula detachment surgery monitoring instruments

In recent years image processing has improved detection and diagnosis in medical application. Image processing applications are now embedded in medical instruments such as MRI and CT. In the case of retinopathy, fast extraction of blood vessels can allow the physician to view injury regions during surgery. Macula detachment surgeries, or computer‐aided intraocular surgeries, require precise and real‐time knowledge of the vasculature during the operation. Use of artificial neural network has produced good results in image processing applications, but its implementation may not be suitable for real‐time applications in small, embedded hardware. Because of error resiliency of the neural network, its structure can be pruned and simplified. In this paper an efficient hardware implementation of neural network for retinal vessel segmentation is proposed. We simplify the neural network structure in such a way that the accuracy of the results is not altered significantly. Simulation results and FPGA implementation show that our proposed network has low complexity and can be applied for segmentation of retinal vessels with acceptable accuracy. This makes the proposed method a good candidate to be implemented in any device such as a binocular indirect ophthalmoscope.     

Reconfigurable architecture of VDF filter for multidimensional data

In this paper, we present a hardware reconfigurable architecture of vector directional filter (VDF) and an experimental validation based on HW/SW implementation context. An FPGA with a Nios II processor combines the benefits of a programmable logic component as well as a microprocessor. VDF is very useful in multidimensional data (such as color images) for noise removal and details preservation. Comparative results between simulations of ANSI‐C and hardware implementation are given. An estimate method of nonlinear function is presented and serves as an approximation for the appropriate hardware implementation on FPGA. Finally, to verify the functionality of the implementation, a validation state using FPGA platform has been performed. This validation demonstrated that our implementation hardware system speeds up the filtering process as well as preserving a high data quality (image quality). Copyright © 2012 John Wiley & Sons, Ltd.     

基于FPGA的模糊PID控制在下肢外骨骼中的应用研究

针对下肢外骨骼机器人的助力需求,提出了一种基于Verilog HDL硬件描述语言,FPGA（现场可编程逻辑门阵列）实现的自适应模糊PID控制系统设计方法,应用于下肢外骨骼机器人关节的驱动控制。首先,通过MATLAB/Simulink系统仿真软件,进行算法模型仿真,检验算法的稳定性及参数的准确性。再以Quartus II为开发平台,完成自适应模糊PID控制器的Verilog HDL分层设计,基于FPGA芯片EP4CE10F17C8来具体实现及验证。实验结果表明模糊PID控制可更快的达到稳定状态,超调量约降低4.7%,且通过FPGA来实现控制算法更好地满足了下肢外骨骼机器人的控制需求。     

Peptide Mass Fingerprinting Using Field-Programmable Gate Arrays

The reconfigurable computing paradigm, which exploits the flexibility and versatility of field-programmable gate arrays (FPGAs), has emerged as a powerful solution for speeding up time-critical algorithms. This paper describes a reconfigurable computing solution for processing raw mass spectrometric data generated by MALDI-TOF instruments. The hardware-implemented algorithms for denoising, baseline correction, peak identification, and deisotoping, running on a Xilinx Virtex-2 FPGA at 180 MHz, generate a mass fingerprint that is over 100 times faster than an equivalent algorithm written in C, running on a Dual 3-GHz Xeon server. The results obtained using the FPGA implementation are virtually identical to those generated by a commercial software package MassLynx.      

基于FPGA的频谱分析系统研究与实现

针对音频信号分析,提出了一种基于 FPGA 的频谱分析系统,该设计基于 FFT 和 CORDIC 算法;讨论在FPGA上进行高达4096点的定点 FFT 运算和基于CORDIC算法的复数求模运算的系统架构和实现过程。通过Modelsim仿真,同MATLAB运算结果比较,本频谱计算方案的相对误差均值为4．11％。利用MCU进行信号采样与AD转换,并通过SPI接口将数据发送给FPGA进行频谱分析。当采样频率为60 kHz时,本系统辨识的频率范围为14．65 Hz～30 kHz ,频率分辨率为14．65 Hz。对实际硬件系统进行频谱分析测试,成功实现对输入的音频信号的频谱计算。     

An FPGA implementation of hard‐wired sequence control system based on PLC software

Although a programmable logic controller (PLC) has been widely adopted for the sequence control of industrial machinery, its performance does not always satisfy the recent requirements in large and highly responsive systems. With the state‐of‐the‐art field programmable gate array (FPGA) technology, it is possible to implement a control program with hard‐wired logic for higher response and reduced implementation cost/space. This approach is also worthwhile for transmigration of legacy PLC software into forthcoming FPGA‐based control hardware. This study presents a systematic method to implement a hard‐wired sequence control from PLC software. PLC instructions are converted into VHDL codes, and then implemented as logic circuit with various peripheral functions. Productive PLC programs were examined with Mitsubishi Electric FX2N PLC and Altera Stratix II FPGA, and were shown to fit into a common FPGA chip. A straightforward Sequential design was estimated to be 184 times faster than PLC, while a performance‐oriented Flat design was estimated to be 44 times faster than Sequential design (i.e., 8050 times faster than PLC). A practical perfect layer winder system was actually built and successfully operated with our FPGA control board, whose logic design was implemented with our tools. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Prototype hardware realization of the DSTATCOM for reactive power compensation

This paper presents the hardware prototype implementation of a hysteresis current controller (HCC) based DSTATCOM for reactive power compensation. To compensate the desired amount of reactive power, the amount of current to be injected is calculated using the instantaneous reactive power theory. The reactive component of load current is set as the reference current. The VSC is operated in the closed-loop to supply the reference current. If the VSC supplies this reference current, the DSTATCOM is said to supply the required reactive power when connected to the grid. The performance of the DSTATCOM for reactive power compensation is studied in the prototype hardware using the field programmable gate array (FPGA) controller. The issues associated with the implementation of hardware prototype are discussed and the experimental setup is found to compensate the reactive power. The Spartan-3A DSP FPGA controller is programmed using the system generator feature in the MATLAB.     

高速并行内插倍数可变的成形滤波器设计

提出了一种适合数字通信的码速率和内插倍数可变的并行结构数字基带成形滤波器的设计方法,使用MATLAB,软件进行了仿真和系数生成,并在以FPGA为核心的硬件平台上完成了实现和验证。在QuartusII软件中使用其内部嵌入式逻辑分析仪观察了不同符号速率成形后的符号波形,波形平滑均满足设计要求。采用这种方法实现的成形滤波器具有很强的灵活性,符合数字通信软件无线电的趋势。     

基于FPGA的FIR滤波器FFT与DA算法的比较

本文利用FPGA实现了基于FFT算法与DA的FIR滤波器,在此基础上进行了规模和速度上的改进。通过MATLAB与MAX PLUSⅡ的联合仿真,验证了FPGA的实现方案是可行的和高效的。比较了两种算法在资源消耗以及速度方面各自的优越性。结果表明,采用基于DA蝶形处理器的并行FFT算法实现的64阶FIR滤波器使用了1869个LC,基于规模改进DA实现的同阶FIR滤波器使用了1428个LC,前者的使用资源多但速度优于后者。     

流水线双模CORDIC算法的FPGA实现

CORDIC算法将复杂的算术运算转化为简单的加法和移位操作,然后逐次逼近结果.这种方法很好地兼顾了精度、速度和硬件复杂度,它与VLSI技术的结合对DSP算法的硬件实现具有极大的意义,因而在数字信号处理领域得到了广泛应用.本文首先简要介绍了CORDIC算法的原理,然后详细描述了双模CORDIC算法的模式控制和范围扩展,并且基于FPGA实现了流水线双模CORDIC算法,给出了综合结果,最后下载到FPGA开发板中验证通过.这些结果表明,本算法具有良好的性能,并且已经应用到OFDM系统的频率偏移校正中.     

行波故障定位系统中数据采集卡的设计与实现

提出一种用于行波故障定位系统的高速、高精度、多通道同步数据采集卡的设计和实现方法。首先给出了采集卡的总体结构及工作原理,然后详细介绍了采集卡硬件和软件的设计和实现思路。硬件以现场可编程门阵列(field programmable gate array,FPGA)为中央处理器,以高速、高精度、低功耗的模数转换器为信号转换单元,配备先进先出高速缓存,同步动态随机存储器和全球定位系统同步时钟接收模块。软件主要包括FPGA编程和外部设备互连PCI总线驱动程序。该采集卡能实现每路100 MHz的采样速率和16位高精度3路模拟输入的同步采集,并为采集的数据附加时标,可有效解决故障行波的高速、高精度数据采集问题。     

基于MATLAB的合并单元实验装置的研究

根据IEC60044 8标准对合并单元的定义,从合并单元的功能入手,用MATLAB软件模拟现场电力系统的多路故障信息,并通过以太网按照FT3帧格式将多路信号发送给合并单元,而以FPGA为硬件核心的合并单元对接收到的多路信号进行处理,最后通过以太网发送到二次侧设备对接收到的数据进行实时显示。针对此实验平台的研究主要描述了各模块的结构与功能：包括了MATLAB发送模块、FPGA接收与光纤发送模块以及曼彻斯特编解码与数据显示的模块。搭建硬件平台并给出了软件的测试结果。     

基于FPGA的浮点FIR滤波器设计

针对定点FIR滤波器的精度和稳定性不高,且高阶FIR滤波器资源开销大的弊端,在FPGA上提出和设计了一种基于浮点运算的FIR滤波器。采用该浮点FIR滤波器,不仅能有效的降低因定点FIR滤波器权系数量化所引入的误差,同时还不会增加额外的硬件开销。在解调国内某型激光陀螺信号时,该滤波器取得了不俗的表现,同时该滤波器具有可移植性强,应用灵活等特点。     

频谱分析仪全数字中频设计研究与实现

介绍了频谱分析仪的全数字中频的设计方案和工作原理,重点讨论了数据抽取造成的频谱扩散在设计中的考虑、CIC滤波器的截短误差与传递、数字滤波器的响应时延与扫描Bucket的修正等设计技术,这对实现接收机全数字中频设计具有重要意义。给出了数字中频设计的细节和实现方法,采用所述技术方案和设计方法,实现了1Hz～3MHz分辨率带宽（RBW）;带宽准确度±2％;RBW转换误差0．05dB;矩形系数优于1／4;全跨度扫频时间为50ms等性能指标。并且,还节省了FPGA资源、提高了扫频精度,设计结果满足高性能频谱分析仪的设计需求。