Implementation of an in‐field CMOS frequency division multiplexer for 9.4 T magnetic resonance applications

This paper introduces the implementation of an application‐specific complementary metal oxide semiconductor frequency division multiplexer as a novel solution to interface magnetic resonance (MR) phased arrays of micro‐detectors to an image‐processing unit, thus reducing the complexity and space issues associated with MR detector arrays. The frequency multiplexer, in a compact 3 × 4 mm silicon die, is designed to operate at 400 MHz, which is the Larmor frequency of ¹H protons in a 9.4‐T MR imaging system. The system implements eight channels, where each channel consists of a low‐noise amplifier, a frequency mixer, and a band‐pass filter. The maximum gain of an individual channel after the band‐pass filter stage is 38 dB. The suppression of the local oscillator ranges from 40 to ?51 dB, and the maximum coupling between channels is ?39 dB. The input dynamic range of an individual channel is 8 mV. Each channel consumes 54 mA from a 3.3‐V source. The chip operates without errors within a high 9.4‐T magnetic field. Copyright © 2014 John Wiley & Sons, Ltd.     

A 7.5‐μW 0.08‐mm2 single‐ended SC delta‐sigma ADC for acoustic sensor applications

This study presents an ultra‐low‐power, small‐size, 1‐bit, single‐ended, and switched‐capacitor (SC) delta‐sigma analog‐to‐digital converter (ADC) for wireless acoustic sensor nodes. This wireless sensor node has a delta‐sigma ADC that converts the sensed signal to a digital signal for convenient data processing and emphasizes the features of small size and low‐power consumption. The chip area of the delta‐sigma ADC is dominated by the capacitor; therefore, a novel common‐mode (CM) controlling technique with only transistors is proposed. This ADC achieves an extremely small size of 0.08 mm² in a 130‐nm CMOS process. The conventional operational transconductance amplifiers (OTAs) are replaced by inverters in the weak inversion region to achieve high power efficiency. At 4‐MHz sampling frequency and 0.7‐V power supply voltage, the delta‐sigma ADC achieves a 55.8‐dB signal‐to‐noise‐plus‐distortion ratio (SNDR) and a 298‐fJ/step figure‐of‐merit (FOM) in a signal bandwidth of 25 kHz, while consuming only 7.5 μW of power. Copyright © 2015 John Wiley & Sons, Ltd.     

Design and implementation of a hybrid DPWM under 50 ps resolution based on general‐purpose FPGA

High‐resolution pulse width modulators are used widely in different fields of electrical engineering, such as dimming of light‐emitting diode (LED) lighting, motor control, RF modulators, audio amplifiers, and switch‐mode power supplies. To realize a high‐resolution digital pulse‐width modulator (DPWM) in a limited inner system clock, a simple implementation of a hybrid DPWM with the resolution under 50 ps based on a general‐purpose field‐programmable gate array (FPGA) is described. The multiplexer device implementing the fast carry‐chain path and an AND gate controlling the selection input are used as a delay unit. The manual routing or placement is not required in the proposed approach, which just needs some conditional constraints. Some different conditional constraints influencing the monotonicity and resolution of DPWM are discussed. Finally, a 1 MHz switching frequency DPWM with 40 ps resolution is experimentally demonstrated, with high monotonicity and linearity. Further, a synchronous buck with and without this high‐resolution DPWM is experimentally compared to illustrate the regulation resolution.     

RF modeling of 40‐nm SOI triple‐gate FinFET

These last years, the triple‐gate fin field‐effect transistor (FinFET) has appeared as attractive candidate to pursue the complementary metal‐oxide semiconductor technology roadmap for digital and analog applications. However, the development of analog applications requires models that properly describe the static and RF behaviors as well as the extrinsic parameters related to the three‐dimensional FinFET architecture, in order to establish adequate design strategies. We demonstrate the feasibility of the compact model developed for symmetric doped double‐gate metal‐oxide‐semiconductor field‐effect transistor (symmetric doped double‐gate MOSFET) to reproduce the experimental dc and RF behaviors for 40‐nm technology node Silicon‐on‐Insulator triple‐gate FinFETs. Extrinsic gate capacitances and access extrinsic resistances have been included in order to properly predict the transistor small‐signal behavior, the current gain, and the maximum available power gain cut‐off frequencies. Finally, the improvement of the FinFET RF characteristics by the reduction of the parasitics is addressed. Copyright © 2014 John Wiley & Sons, Ltd.     

A new fast‐lock,low‐jitter,and all‐digital frequency synthesizer for DVB‐T receivers

Lock time and convergence time are the most important challenges in delay‐locked loops (DLLs). In this paper we cover French very high frequency band with a novel all‐digital fast‐lock DLL‐based frequency synthesizer. Because this new architecture uses a digital signal processing unit instead of using phase frequency detector, charge pump, and loop filter in conventional DLL, therefore, it shows better jitter performance, lock time, and convergence speed than previous related works. Optimization methods are used to make input and output signals of the proposed DLL in phase. The proposed architecture is designed to cover all channels of French very high frequency band by choosing number of delay cells in signal path. Simulation has been done for 22–27 delay cells, and f_REF = 16 MHz, which can produce output frequency in range of 176–216 MHz. Locking time is approximately 0.3 µs, which is equal to five clock cycles of reference clock. All of the simulation results show superiority of the proposed structure. Copyright © 2013 John Wiley & Sons, Ltd.     

A 5‐GHz energy‐efficient tunable pulse generator for ultra‐wideband applications using a variable attenuator for pulse shaping

A new energy‐efficient tunable pulse generator is presented in this paper using 0.13‐µm CMOS technology for short‐range high‐data‐rate 3.1–10.6 GHz ultra‐wideband applications. A ring oscillator consisting of current‐starved CMOS inverters is quickly switched on and off for the duration of the pulse, and the amplitude envelope is shaped with a variable passive CMOS attenuator. The variable passive attenuator is controlled using an impulse that is created by a low‐power glitch generator (CMOS NOR gate). The glitch generator combines the falling edge of the clock and its delayed inverse, allowing the duration of the impulse to be changed over a wide range (500–900 ps) by varying the delay between the edges. The pulses generated with this technique can provide a sharp frequency roll off with high out‐of‐band rejection to help meet the Federal Communications Commission mask. The entire circuit operates in switched mode with a low average power consumption of less than 3.8 mW at 910 MHz pulse repetition frequency or below 4.2 pJ of energy per pulse. It occupies a total area of 725 × 600 µm² including bonding pads and decoupling capacitors, and the active circuit area is only 360 × 200 µm². Copyright © 2011 John Wiley & Sons, Ltd.     

High‐tuning‐range CMOS band‐pass IF filter based on a low‐Q cascaded biquad optimization technique

A design procedure for high‐order continuous‐time intermediate‐frequency band‐pass filters based on the cascade of low‐Q biquadratic cells is presented. The approach is well suited for integrated‐circuit fabrication, as it takes into account the maximum capacitance spread dictated by the available technology and maximum acceptable sensitivity to component variations. A trade‐off between noise and maximum linear range is also met. A novel, wide‐tuning‐range transconductor topology is also described. Based on these results, a 10‐pole band‐pass filter for a code division multiple‐access satellite receiver has been designed and tested. The filter provides tunable center frequency (f₀) from 10 to 70 MHz and exhibits a 28‐MHz bandwidth around f₀ = 70 MHz with more than 39‐dB attenuation at f₀/2 and 2f₀. Third‐order harmonic rejection is higher than 60 dB for a 1‐Vpp 70‐MHz input, and equivalent output noise is lower than 1 mV_rms. The circuit is fabricated in a 0.25‐µm complementary metal oxide semiconductor process, and the core consumes 12 mA from a 2.5‐V supply, offering the best current/pole ratio figure. The die area resulted to be 0.9 × 1.1 mm². Copyright © 2014 John Wiley & Sons, Ltd.     

A low‐power,area‐efficient multichannel receiver for micro MRI

A new integrated, low‐noise, low‐power, and area‐efficient multichannel receiver for magnetic resonance imaging (MRI) is described. The proposed receiver presents an alternative technique to overcome the use of multiple receiver front‐ends in parallel MRI. The receiver consists of three main stages: low‐noise pre‐amplifier, quadrature down‐converter, and a band pass filter (BPF). These components are used to receive the nuclear magnetic resonance signals from a 3 × 3 array of micro coils. These signals are combined using frequency domain multiplexing (FDM) method in the pre‐amplifier and BPF stages, then amplified and filtered to remove any out‐of‐band noise before providing it to an analog‐to‐digital converter at the low intermediate frequency stage. The receiver is designed using a 90 nm CMOS technology to operate at the main B₀ magnetic field of 9.4 T, which corresponds to 400 MHz. The receiver has an input referred noise voltage of 1.1 nV/√Hz, a total voltage gain of 87 dB, a power consumption of 69 mA from a 1 V supply voltage, and an area of 305 µm × 530 µm including the reference current and bias voltage circuits. Copyright © 2013 John Wiley & Sons, Ltd.     

Signal separation theory using adaptive arrays

The signal separation technique using adaptive arrays is a new area in array data processing. The model considered in this paper is that of an array consisting of N elements; the number of signal sources, which are separated in spatial location, is M and M ≥ N. In the case of narrow band signals, the pre-envelope form of the incident signal can be obtained from the original signal and its Hilbert transform. The directional bearing-angle matix G is formed in terms of the conventional beam-forming system. By using a special implementation, the inverse matrix of G is derived. Finally, a matrix transform is operated on the received signal so that the output signal is separable, i.e. each output channel has only one incident signal. In the case of wide band signals, the DFT of the input signal or heterodyne is required. The block diagrams of the signal separation technique are given and some important results of this technique are derived. The results of system simulation experiments in digital computers prove that this theory is effective for separating signals.     

A 1–6 GHz analog radio frequency power driver in 90 nm complementary metal‐oxide semiconductor technology for wireless applications

One of the most challenging subsystems for integrated radio frequency (RF) complementary metal‐oxide semiconductor (CMOS) solutions is the power amplifier. A 1–6 GHz RF power driver (RFPD) in 90 nm CMOS technology is presented, which receives signals from on‐chip RF signal chain components at ?12 dBm power levels and produces a 0 dBm signal to on‐chip or off‐chip 50 Ω loads. A unique unit cell design is developed for the RFPD to offset issues associated with very wide multi‐fingered transistors. The RF driver was fabricated as a stand‐alone sub‐circuit on a 90 nm CMOS die with other sub‐circuits. Experimental tests confirmed that the on‐chip RFPD operates up to 6 GHz and is able to drive 50 Ω loads to the desired 0 dBm power level. Spur free dynamic range exceeded 70 dB. The measured power gain was 11.6 dB at 3 GHz. The measured 1 dB compression point and input third‐order intercept point (IIP3) were ?4.7 dBm and ?0.5 dBm, respectively. Also, included are modeling, simulation, and measured results addressing issues associated with interfacing the die to a package with pinouts and the package to a printed circuit test fixture. The simulations were made through direct current (DC), alternating current (AC), and transient analysis with Cadence Analog Design Environment. The stability was also verified on the basis of phase margin simulations from extracted circuit net‐lists. Copyright © 2013 John Wiley & Sons, Ltd.     

A 10 b 25 MS/s 4.8 mW 0.13 µm CMOS ADC with switched‐bias power‐reduction techniques

This paper proposes a 10 b 25 MS/s 4.8 mW 0.13 µm CMOS analog‐to‐digital converter (ADC) for high‐performance portable wireless communication systems, such as digital video broadcasting, digital audio broadcasting, and digital multimedia broadcasting (DMB) systems, simultaneously requiring a low‐voltage, low‐power, and small chip area. A two‐stage pipeline architecture optimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate, while switched‐bias power‐reduction techniques reduce the power consumption of the power‐hungry analog amplifiers. Low‐noise reference currents and voltages are implemented on chip with optional off‐chip voltage references for low‐power system‐on‐a‐chip applications. An optional down‐sampling clock signal selects a sampling rate of 25 or 10 MS/s depending on applications in order to further reduce the power dissipation. The prototype ADC fabricated in a 0.13 µm 1P8M CMOS technology demonstrates a measured peak differential non‐linearity and integral non‐linearity within 0.42 LSB and 0.91 LSB and shows a maximum signal‐to‐noise‐and‐distortion ratio and spurious‐free dynamic range of 56 and 65 dB at all sampling frequencies up to 25 MHz, respectively. The ADC with an active die area of 0.8 mm² consumes 4.8 and 2.4 mW at 25 and 10 MS/s, respectively, with a 1.2 V supply. Copyright © 2008 John Wiley & Sons, Ltd.     

An 11‐μ W, 9‐bit fully differential,cyclic/algorithmic ADC in 0.13 μm CMOS

This paper describes a fully differential, cyclic, analogue‐to‐digital converter (ADC). It utilizes a 4‐bit binary weighted capacitor array to obtain 9‐bit resolution. The ADC uses an operational amplifier to suppress supply voltage variations. The operational amplifier with the slew‐rate detection is used to increase the speed of the ADC. The ADC is fabricated in IBM 0.13 μm CMOS process and occupies 650 × 850μm² active area. At 10 kS/s sampling rate, the ADC consumes 11 μW. In order to test immunity of the ADC on the supply voltage variations, static and dynamic performance of the ADC is measured with triangular supply voltage (V _{D C}  = 1.5 V, V _{A C}  = 200mV _pp, f  = 1 kHz). The measured peak of differential nonlinearity and integral nonlinearity is  + 0.26/ − 0.67 and  + 0.65/ − 0.59, respectively. At 250 Hz, effective number of bit is 8.4 bits, S F D R  = 66.7 dB and S N D R  = 52.6 dB. Copyright © 2016 John Wiley & Sons, Ltd.     

Design of a 1‐GSample/s 9‐b double sampling track‐and‐hold amplifier in BiCMOS technology

This paper gives a detail presentation of a fully pseudo‐differential open‐loop BiCMOS track‐and‐hold amplifier (THA) for 9‐b operation up to 1 GSample/s. The proposed THA not only uses a double sampling technique to increase the achievable sampling frequency by a factor of two, but also employs a linearization technique to reduce the gain dependence of the THA input stage upon the input level. Moreover, timing mismatch between the clock signals of the two interleaved paths is minimized by means of a timing mismatch insensitive clock generator controlled by a common master sampling clock. The post‐layout simulation results using TSMC 75 GHz f_T, 0.35‐µm SiGe BiCMOS technology show that the proposed architecture achieve a signal to noise and distortion ratio of 53.92 dB, equivalent to the effective number of bits of 8.66‐b for 58.11 MHz input frequency at 1 GSample/s. The power dissipation of the whole THA is 161.1 mW. Copyright © 2012 John Wiley & Sons, Ltd.     

A single‐bit continuous‐time delta‐sigma modulator using clock‐jitter and inter‐symbol‐interference suppression technique

This paper presents a technique for mitigating two well‐known DAC non‐idealities in continuous‐time delta‐sigma modulators (CTDSMs), particularly in wide‐band and low over‐sampling‐ratio (OSR) cases. This technique employs a special digital‐to‐analog convertor (DAC) waveform, called modified return‐to‐zero (MRZ), to reduce the time uncertainty effect because of the jittered clock at the sampling time instances and eliminate the effect of inter‐symbol‐interference (ISI) which degrades the modulator performance, especially when non‐return‐to‐zero (NRZ) DAC waveform is chosen in the modulator design. A third‐order single‐bit CTDSM is designed based on the proposed technique and step‐by‐step design procedure at circuit and system levels, considering clock jitter and ISI, is explained. Circuit simulations in 180‐nm CMOS technology show that in the presence of circuit non‐idealities which generate jitter and asymmetrical rise and fall times in the DAC current pulse, signal‐to‐noise‐distortion‐ratio (SNDR) of the proposed modulator is higher than the conventional modulator with NRZ waveform by about 10 dB. In these simulations, clock jitter standard deviation is 0.3% of the sampling period (T_S) and the difference between fall/rise times in the DAC current pulse is 4%T_S. Simulated at 600‐MHz sampling frequency (f_S) with an oversampling ratio (OSR) of 24, SNDR figure of merit (FOM_SNDR) of the proposed modulator in 180‐nm CMOS is 300 fj/conversion. Copyright © 2016 John Wiley & Sons, Ltd.     

A 0.5‐V 5.9‐fJ/conversion‐step SAR ADC in 0.18‐μm CMOS

In this paper, we present a 434‐nW 8‐bit successive approximation register analog‐to‐digital converter (SAR ADC). We mainly consider the optimization of power consumption. A modified split‐capacitor array involving a novel switching scheme is proposed, which reduces the switching power consumption to just 13.8 for the single‐ended scheme without any losses in performance. Based on the SMIC CMOS 0.1 μm EEPROM 2P4M process, the simulation results show that at 0.5 V supply voltage, 300 kS/s sample frequency, and 4.98 kHz input frequency, the ADC achieves an signal‐to‐noise‐plus‐distortion ratio (SNDR) of 49.58 dB and effective number of bits (ENOB) of 7.94, and consumes 434 nW, resulting in a figure of merit of 5.9 fJ/conversion step. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A 0.008‐mm2, 35‐μW, 8.87‐ps‐resolution CMOS time‐to‐digital converter using dual‐slope architecture

This paper presents a high resolution time‐to‐digital converter (TDC) for low‐area applications. To achieve both high resolution and low circuit area, we propose a dual‐slope voltage‐domain TDC, which is composed of a time‐to‐voltage converter (TVC) and an analog‐to‐digital converter (ADC). In the TVC, a current source and a capacitor are used to make the circuit as simple as possible. For the same reason, a single‐slope ADC, which is commonly used for compact area ADC applications, is adapted and optimized. Because the main non‐linearity occurs in the current source of the TVC and the ramp generator of the ADC, a double gain‐boosting current source is applied to overcome the low output impedance of the current source in the sub‐100‐nm CMOS process. The prototype TDC is implemented using a 65‐nm CMOS process, and occupies only 0.008 mm². The measurement result shows a dynamic range with an 8‐bit 8.86‐ps resolution and an integrated non‐linearity of ±1.25 LSB. Copyright © 2016 John Wiley & Sons, Ltd.     

A low‐power delay stage ring VCO based on wrap‐gate CNTFET technology for X‐band satellite communication applications

Over the past few years, with lower power consumption, reasonable layout area, and the ease of integration with standard circuit design technologies compared to the other counterparts, delay stage ring voltage‐controlled oscillators (VCOs) have been in the limelight of microelectronics scientists. However, few efforts have focused on representing high‐performance delay stage ring VCOs in the deep nanometric regime. In this regard, by virtue of outstanding electrical properties of carbon nanotube wrap‐gate transistors, this work aims to propose a carbon nanotube field‐effect transistor (CNTFET)–based delay stage ring VCO. After performing rigorous simulations, the proposed ring VCO which has been designed by 10‐nm gate‐all‐around (GAA) CNTFET technology shows suitable electrical performance metrics. The simulation results demonstrate that the proposed GAA‐CNTFET‐based ring VCO consumes 85.176 μW at with a 6.12‐ to 10.42‐GHz frequency tuning range. At the worst‐case noise conditions, the proposed design presents ‐90.747 dBc/Hz phase noise at 1 MHz offset frequency. With occupying 1.414 μm² physical area, the proposed VCO is appropriate for the ultracompact nanoscale radio frequency apparatus. Our simulation results accentuate that with further improvements and commercializing the fabrication techniques for CNTFET transistors, the proposed GAA‐CNTFET‐based VCO can be considered as a potential candidate for X‐band satellite communication applications.     

2D‐DOA estimation performance using split vertical linear and circular arrays

This paper presents a new approach to reduce the computational complexity in two‐dimensional (2D) matrix pencil (MP) method for direction of arrival (DOA) estimation of plane wave signals using a combination of vertical uniform linear array (VULA) and uniform circular array (UCA). By applying phase mode excitation based beamforming to the UCA, we can apply the matrix pencil (MP) method to the beamspace data using only a single snapshot. The technique is based on the split array, which is composed of two perpendicular arrays. The vertical uniform linear array used to determine the elevation DOA components is located perpendicularly at the center of the uniform circular array in the horizontal plane used to calculate the azimuth angles. Unlike common planar and circular arrays, this antenna array with its particular geometry requires no pair‐matching between the azimuth and the elevation angle estimation and can also remove the drawbacks of estimation failure problems. Using this particular geometry for the 2D MP method leads to an efficient computational methodology for real‐time implementation on a digital signal processor. The obtained simulation results of the MP method applied to both uncorrelated and correlated narrow‐band sources in the presence of white noise show good performance estimation. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A novel analog maximum power point tracker for low‐cost and low‐power distributed PV systems

The main disadvantage of the voltage‐based maximum power point tracking (VMPPT) method is in the way the photovoltaic (PV) array is disconnected from the load when sampling open‐circuit voltage, which inevitably results in power loss. Another disadvantage is in case of rapid irradiance variation, where the duration between two successive samplings is too long, leading to considerable loss. To overcome these problems, this paper proposes a low‐cost analog VMPPT circuit that is designed on the basis of an ultralow‐power sample‐and‐hold circuit with the least hardware complexity, which has not been reported before. Furthermore, the method of determining the sampling frequency and time interval of the sampling mode is investigated. Experimental verification with a series of different PV power sources is likewise conducted. The experimental results confirm that the proposed MPPT circuit can operate over a wide range of PV power and can adapt quickly to the changing environment. The disconnection energy loss is reduced significantly, with a high system efficiency of up to 95.9%. © 2015 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Dependence of RF characteristics on ac bias current for large‐sized ferrites

A ferrite‐loaded radio‐frequency (RF) cavity with resonant frequency of several megahertz is commonly used for proton synchrotrons. The resonant frequency of the cavity is shifted upward during beam acceleration by increasing the bias current. Because the bias current is swept sinusoidally at a high repetition rate, the RF characteristics of ferrites deteriorate due to disappearance of the magnetic anisotropy induced by Co²⁺ and Co³⁺ ions. This paper presents test results of the RF characteristics for three ferrites with large diameters of over 500 mm. The tests were carried out on our ferrite test bench. The RF frequency and the ac bias current vary from 2 MHz to 3.3 MHz and from 0 A to 1000 A, respectively, at the maximum frequency of 75 Hz. As the frequency of the ac bias current became high, deterioration of the RF characteristics and an increase in the ac bias current were observed. Consequently, it was verified that an ac bias test with full RF power using the test bench was inevitable for designing an actual RF cavity. © 1999 Scripta Technica, Electr Eng Jpn 127(4): 1–8, 1999