Electrothermal simulation of multichip-modules with novel transient thermal model and time-dependent boundary conditions

The ability of monitoring the chip temperatures of power semiconductor modules at all times under various realistic working conditions is the basis for investigating the limits of the maximum permissible load. A novel transient thermal model for the fast calculation of temperature fields and hot spot temperature evolution presented recently is extended to include time-dependent boundary conditions for variations of ambient temperature and surface heat flows. For this a Green's function representation of the temperature field is used. Also, general initial temperature conditions are included. The method is exemplified by application to a dc/ac converter module for automotive hybrid drives. The thermal model, which can be represented by a thermal equivalent circuit, then is combined with an electrical PSpice-metal-oxide semiconductor field-effect transistor (MOSFET) model to allow for the fully self-consistent electrothermal circuit simulation of 42-V/14-V dc/dc-converter modules. 670 converter periods with altogether 8000MOSFET switching cycles in the six-chip module can be simulated within 1-h computing time on a Pentium PC. Various simulation results are presented, which demonstrate the feasibility of the simulation method and allow for the optimization of converter losses. Short circuit modes of converter operation are investigated with a high temperature increase also revealing the thermal interaction between different chips.     

Monte Carlo Static Timing Analysis with statistical sampling

With aggressive scaling of CMOS technologies, MOSFET devices are subject to increasing amounts of independent local statistical variability. The causes of these statistical variations and their effects on device performance have been extensively studied, but their impact on circuit performance is still difficult to predict. This paper proposes a method for modeling the impact of random intra-die statistical variations on digital circuit timing. The method allows the variation modeled by large-scale statistical transistor simulations to be propagated up the design flow to the circuit level, by making use of commercial STA and standard cell characterization tools. By using statistical sampling techniques, we achieve close to the accuracy of full SPICE simulation, but with a computational effort similar to that of Statistical Static Timing Analysis, while removing some of the inaccurate assumptions of Statistical Static Timing Analysis.     

A Practical Switching Loss Model for Buck Voltage Regulators

In this paper, a review of switching loss mechanisms for synchronous buck voltage regulators (VRs) is presented. Following the review, a new simple and accurate analytical switching loss model is proposed for synchronous buck VRs. The model includes the impact of common source inductance and switch parasitic inductances on switching loss. The proposed model uses simple equations to calculate the rise and fall times and piecewise linear approximations of the high-side MOSFET voltage and current waveforms to allow quick and accurate calculation of switching loss in a synchronous buck VR. A simulation program with integrated circuit emphasis (Spice) simulations are used to demonstrate the accuracy of the voltage source driver model operating in a 1-MHz synchronous buck VR at 12-V input, 1.3-V output. Switching loss was estimated with the proposed model and compared to Spice measurements. Experimental results are presented to demonstrate the accuracy of the proposed model.     

Modeling of the MOSFET inversion charge and drain current, inmoderate inversion

The widespread use of MOS technology in analog circuit design demands a precise and efficient circuit simulation model of the MOS transistor valid in all regions of inversion. Currently available circuit simulation models fail in the intermediate range of gate voltages, known as the moderate inversion region. Expressions characterizing the large-signal behavior of the long-channel MOS transistor in the moderate inversion region are derived. The correct dependencies on all the physical and process parameters are preserved by a careful approximation to the physical equations, based on the charge sheet assumption. Another goal is to develop expressions that treat the moderate inversion as a small, voltage-dependent correction to currently existing simplified models. This approach should allow a simple modification of the existing circuit simulation models to improve the accuracy in moderate inversion. The model was compared with a numerical charge sheet model and with experimental measurements of a long-channel, ion-implanted NMOS transistor. The expressions could serve as a basis for a comprehensive MOSFET circuit simulation model     

Model for the channel-implanted enhancement-mode IGFET

A simple dc four-terminal "channel-implanted model" is developed for the enhancement-mode IGFET. The model accurately predicts the dependence of transistor threshold voltage and current gain on substrate bias. Modeled and measured threshold voltages are shown to agree to within 25 mV across a 15-V range of VSB. Modeled and measured transistor currents agree to within 5 percent across a 10-V range of VSBfor medium- to long-channel length transistors (L_{drawn} ge 2.5µm). The channel impurity profile is approximated as a constant effective impurity concentration NAEextending from the semiconductor surface through the implanted region to an effective implant depth XDE("box" profile approximation). At depths greater than XDE, the bulk substrate impurity concentration is approximated as a constant, NA. The model is composed of two threshold voltage equations, three drain current equations, two saturation voltage equations, and two boundary equations. All first-order model equations and all of their first derivatives are continuous at all boundaries. The model's continuity and its accuracy make it useful for circuit simulation. Extrapolation of channel concentration profile parameters NAE, XDE, and NAfrom measured threshold voltages yields information on implant profile and on field-implant impurity encroachment into the transistor channel.     

A novel high-throughput method for table look-up based analog design automation

Analog circuit synthesis ofen requires repeated evaluations of circuit under design to reach the final design goals. Circuit simulations using SPICE can provide accurate assessment of circuit performance. Spice simulations are costly and incur significant overhead. A faster transistor-level evaluation is needed to provide higher throughput for synthesis applications. Further, miniaturization of FET’s has added physical effects into SPICE models, which complicated their equations with every generation. That complication has forced analog synthesis tool developers and circuit designers alike to perform circuit evaluations using SPICE.Analog circuit design tools largely failed in their declared goal, to take over circuit optimization tasks from human designers mainly due to over simplications using custom-developed equations for evaluating circuit performance. Since it is more and more difficult to accurately capture transistor behavior with each new generation of silicon technology, a more practical approach to analog design automation is to keep human engineers at the center of the design flow by providing them with as much needed decision-supporting data as quickly as possible. Mapping the trade-off landscape of a topology with respect to design specifications, for example, can save designers trial and error time. This approach to analog design automation requires less accuracy from the simulation sign-off tools, such as SPICE. However, it demands much faster response for circuit performance evaluations with sufficient accuracy.In this paper, a new solution to both calculation overheads and model complexity is proposed. The proposed fast evaluation method uses a novel look-up table (LUT) algorithm to extract circuit information from complex physics-based transistor models used by SPICE. The model makes use of contemporary memory space, by replacing equations with look-up tables in addition to advanced interpolation methods. The achieved improvement is over 100× throughput and complete decoupling from physical phenomena compared to SPICE run-time, in exchange for few gigabytes of data per device. Examples are shown for the effectiveness of replacing SPICE with our model in a transistor sizing flow, while keeping 99% of the samples inside the 5% error range on 180 nm and 40 nm CMOS processes. The proposed solution is not intended to replace sign-off quality tools, such as SPICE. Rather, it is intended to be used as a fast performance evaluator in analog design automation flows.     

Model requirements for simulation of low-voltage MOSFET in automotive applications

This paper focuses on the modeling of low-voltage automotive power electronic circuits to obtain accurate system simulation, including estimation of losses. The aim is to compare several metal-oxide semiconductor field-effect transistor (MOSFET) models to find out which can be used for low-voltage, high-current automotive converter simulations. As these models are intended for system simulation, only analytical models are addressed as they may be implemented into any circuit simulator. The different modes of operation of the switches are described (commutation, synchronous rectification, avalanche...), and several models of the power MOSFET transistor, allowing for simulation in these modes, are presented. Special care is given to the parameter extraction methods and to the interconnection model of the commutation cell. The four test circuits used to identify the low-voltage power MOSFET model parameters are presented. Comparison between simulations and measurements obtained with a calorimeter are then detailed. This measurement method is accurate and offers a simple way to prove the quality of simulation results. It is shown that the parameter identification is of major concern to achieve high accuracy, as classical Spice models can give good results, providing the model parameters are correctly set.     

Assessing model adequacy and selecting model complexity in integrated-circuit simulation

A method is described that selects, for each transistor in a circuit, the model of least complexity that will give acceptable accuracy. The capability to assess model adequacy derives from a self-consistency test in which the values of currents and voltages computed in a simulation of the circuit behavior are compared with onset parameters, to determine whether these computed values are consistent with the approximations underlying the device models used in the simulation. The onset parameters for a model are the terminal currents and voltages above or below which the model fails to give a satisfactory representation of device behavior. The authors set forth the onset parameters for the Ebers-Moll model and discuss their determination by terminal measurement and by calculation based on the transistor makeup. The paper limits consideration to the static behavior of transistors operating in the forward-active mode.     

A simple subcircuit extension of the BSIM3v3 model for CMOS RFdesign

An accurate and simple lumped-element extension of the BSIM3v3 MOSFET model for small-signal radio-frequency circuit simulation is proposed and investigated. Detailed comparisons of the small-signal y and s parameters with both two-dimensional device simulations and measurement data are presented. A procedure is developed to extract the values of two lumped resistors-the only added elements. The non-quasi-static and substrate effects can be modeled with these two resistors to significantly improve the model accuracy up to a frequency of 10 GHz, which is about 70% of the f_T of the 0.5 μm NMOS transistor     

Cluster-based delta-QMC technique for fast yield analysis

Monte Carlo (MC) analysis is often considered a golden reference for yield analysis because of its high accuracy. However, repeating the simulation hundreds of times is often too expensive for large circuit designs. The most widely used approach to reduce MC complexity is using efficient sampling methods to reduce the number of simulations. Aside from those sampling techniques, this paper proposes a novel approach to further improve MC simulation speed with almost the same accuracy. By using an improved delta circuit model, simulation speed can be improved automatically due to the dynamic step control in transient analysis. In order to further improve the efficiency while combining the delta circuit model and the sampling technique, a cluster-based delta-QMC technique is proposed in this paper to reduce the delta change in each sample. Experimental results indicate that the proposed approach can increase speed by two orders of magnitude with almost the same accuracy, which significantly improves the efficiency of yield analysis.     

Efficient analytical formulation and sensitivity analysis of neuro-space mapping for nonlinear microwave device modeling

A new computer-aided design (CAD) method for automated enhancement of nonlinear device models is presented, advancing the concept of Neuro-space mapping (Neuro-SM). It is a systematic computational method to address the situation where an existing device model cannot fit new device data well. By modifying the current and voltage relationships in the model, Neuro-SM produces a new model exceeding the accuracy limit of the existing model. In this paper, a novel analytical formulation of Neuro-SM is proposed to achieve the same accuracy as the basic formulation of Neuro-SM (known as circuit-based Neuro-SM) with much higher computational efficiency. Through our derivations, the mapping between the existing (coarse) model and the overall Neuro-SM model is analytically achieved for dc, small-signal, and large-signal simulation and sensitivity analysis. The proposed analytical formulation is a significant advance over the circuit-based Neuro-SM, due to the elimination of extra circuit equations needed in the circuit-based formulation. A two-phase training algorithm utilizing gradient optimization is also developed for fast training of the analytical Neuro-SM models. Application examples on modeling heterojunction bipolar transistor (HBT), metal-semiconductor-field-effect transistor (MESFET), and high-electron mobility transmistor (HEMT) devices and the use of Neuro-SM models in harmonic balance simulations demonstrate that the analytical Neuro-SM is an efficient approach for modeling various types of microwave devices. It is useful for systematic and automated update of nonlinear device model library for existing circuit simulators.     

A comparative study of graph-based, eikonal, and monodomain simulations for the estimation of cardiac activation times

The bidomain and monodomain equations are well established as the standard set of equations for the simulation of cardiac electrophysiological behavior. However, the computational cost of detailed bidomain/monodomain simulations limits their applicability in scenarios where a large number of simulations needs to be performed (e.g., parameter estimation). In this study, we present a graph-based method, which relies on point-to-point path finding to estimate activation times for single points in cardiac tissue with minimal computational costs. To validate our approach, activation times are compared to monodomain simulation results for an anatomically based rabbit ventricular model, incorporating realistic fiber orientation and conduction heterogeneities. Differences in activation times between the graph-based method and monodomain results are less than 10% of the total activation time, and computational performance is orders of magnitude faster with the proposed method when calculating activation times at single points. These results suggest that the graph-based method is well suited for estimating activation times when the need for fast performance justifies a limited loss of accuracy.     

Characterization of Standard Cells for Intra-Cell Mismatch Variations

With the adoption of statistical timing across industry, there is a need to characterize all gates/cells in a digital library for delay variation (referred to as statistical characterization). Statistical characterization needs to be performed efficiently with acceptable accuracy as a function of several process and environmental parameter variations. In this paper, we propose an approach to consider intra-cell process mismatch variations to characterize a cell's delay and output transition time (output slew) variations. A straightforward approach to address this problem is to model these mismatch variations by characterizing for each device fluctuation separately. However, the runtime complexity for such characterization becomes of the order of number of devices in the cell and the number of simulations required can easily become infeasible. We analyze the fluctuations in switching and nonswitching devices and their impact on delay variations. Using these properties of the devices, we propose a clustering approach to characterize for cell's delay variations due to intra-cell mismatch variations. The proposed approach results in as much as 12X runtime improvement with acceptable accuracy, compared with Monte Carlo simulation. We show that this approach ensures an upper bound on the results while keeping the number of simulations for each cell independent of the number of devices.      

Analytical modeling of single electron transistor for hybrid CMOS-SET analog IC design

A physically based compact analytical single electron transistor (SET) model is proposed for hybrid CMOS-SET analog circuit simulation. The modeling approach is based on the "orthodox theory" of single electron tunneling, and valid for single or multi gate, symmetric or asymmetric devices and can also explain the background charge effect. The model parameters are physical device parameters and an associated parameter extraction procedure is reported. The device characteristics produced by the proposed model are verified with Monte Carlo simulation for large range of drain to source voltages (|V/sub DS/|/spl les/3e/C/sub /spl Sigma//) and temperatures [T/spl les/e/sup 2//(10k/sub B/C/sub /spl Sigma//)] and good agreements are observed. The proposed model is implemented in a commercial circuit simulator in order to develop a computer-aided design framework for CMOS-SET hybrid IC designs. A series of SPICE simulations are successfully carried out for different CMOS-SET hybrid circuits in order to reproduce their experimental/Monte Carlo simulated characteristics.     

Analysis of ATPMOS configurations-based 4 × 1 multiplexer with estimation of power and delay

In this article, two consecutive augmenting transistor P-channel metal oxide semiconductor (ATPMOS) configurations are proposed. These two ATPMOS configurations (ST ATPMOS and DT ATPMOS) are implemented on a 4 × 1 (multiplexer) mux circuit. Leakage power dissipation, dynamic power dissipation and delay performance parameters are calculated for both (ST ATPMOS and DT ATPMOS) ATPMOS configurations-based 4 × 1 mux circuits at different values of transistor’s width. Due to simulation, it is realised that the leakage power dissipation and dynamic power dissipation are reduced and delay is improved (delay is reduced) in the DT ATPMOS configuration-based mux circuit compared to the ST ATPMOS configuration-based mux circuit. The whole simulation process was carried out in 45-nm technology. The circuits were operated at 1-V power supply.     

Convolution-based global simulation technique for millimeter-wave photodetector and photomixer circuits

A fast convolution-based time-domain approach to global photonic-circuit simulation is presented that incorporates a physical device model in the complete detector or mixer circuit. The device used in the demonstration of this technique is a GaAs metal-semiconductor-metal (MSM) photodetector that offers a high response speed for the detection and generation of millimeter waves. Global simulation greatly increases the accuracy in evaluating the complete circuit performance because it accounts for the effects of the millimeter-wave embedding circuit. Device and circuit performance are assessed by calculating optical responsivity and bandwidth. Device-only simulations using GaAs MSMs are compared with global simulations that illustrate the strong interdependence between device and external circuit.     

Harmonic and two-tone intermodulation distortion analyses of theinverted InGa/InAlAs/InP HBT

Harmonic and two-tone intermodulation distortion analyses of the InGaAs/InAlAs/InP collector-up heterojunction bipolar transistor (HBT) are performed by a simple Ebers-Moll model. The parasitic elements of the equivalent circuit are extracted at zero bias by numerical optimization. A semianalytical approach is used to extract the intrinsic parameters of the small-signal equivalent circuit at nonzero bias points. Appropriate equations given by device physics are fitted to the bias variation of intrinsic parameters so that the Ebers-Moll model parameters can be extracted. Agreement between simulation and measurement of harmonic and intermodulation distortion is achieved     

Modeling MOS VLSI circuits for transient analysis

Modeling plays a significant role in the efficient simulation of VLSI circuits. By simplifying the models used to analyze these circuits, it is possible to perform transient analyses with reasonable accuracy at speeds of one or two orders of magnitude faster than in conventional circuit simulation programs. The author discusses the models that are used in the second-generation MOTIS timing simulator. The methods used have been applied to a wide variety of MOS digital integrated circuits. All MOS transistors are modeled as voltage-controlled current sources using multidimensional tables. The actual currents are computed by approximation using variation-diminishing tensor splines. Nonlinear device capacitances in the circuit are approximated using linear models which are derived from experimental simulations using a circuit simulator. At the subcircuit level, special structures in the circuit are identified automatically by a preprocessor and are modeled using macro-models. Driver-load MOS transistor gates and bootstrapped circuits are examples of these structures. Their modeling is achieved by an experimental process before implementation in the preprocessor. The simplifications in the device and circuit models presented here have provided a significant improvement in the speed of transient analysis for large MOS digital circuits with relatively little loss in accuracy. This has resulted in a viable design verification environment using MOTIS.     

Automatic Scaling Procedures for Analog Design Reuse

In this paper, a methodology for analog design reuse is proposed. The basic idea is to keep the circuit topology unchanged while automatically modifying the MOSFETs aspect ratio in order to control the transistor transconductances g_m and output conductances g_DS. If g_m's and gDS's of each transistor are kept unchanged through the scaling procedure, we show that the overall frequency behavior of the scaled circuit remains very similar to the original one. The approach is very simple and it is suitable for the scaling of analog circuits. No input and output terminals have to be defined and it can be straightforwardly implemented in an automatic scaling tool. When this approach fails, more complex iterative numerical loops may be adopted. In order to validate and compare the scaling approaches, several linear and nonlinear circuits were scaled from a 0.25-mum, 2.5-V voltage supply to a 0.15-mum, 1.2-V voltage supply in standard CMOS technologies