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1.
The effect of rapid thermal annealing of the optical properties of a strained InAs/InP single quantum well structrure has investigated in this paper.The luminescence intensity of the quantum well at 8K was increased by a factor of 4 and 1.55meV blue shoft of the quantum well photoluminescence peak was observed af-ter annealing at the optimal condition of 700℃ for 5s.Furthermoer,we found that the luminescence efficiency of the deep radiative levels in the samples was also affected by rapid thermal annealing.Our experimental results have demonstrated that Rapid thermal annealing significantly improves the erystalline quality of strained quantum well struc-tures after growth and is an important way for enhancement of the performance of the laser device.  相似文献   

2.
Ohmic contacts with Ti/Al/Ti/Au source and drain electrodes on A1GaN/GaN high electron mobility transistors (HEMTs) were fabricated and subjected to rapid thermal annealing (RTA) in flowing N2. The wafer was divided into 5 parts and three of them were annealed for 30 s at 700, 750, and 800 ℃, respectively, the others were annealed at 750 ℃ for 25 and 40 s. Due to the RTA, a change from Schottky contact to Ohmic contact has been obtained between the electrode layer and the A1GaN/GaN heterojunction layer. We have achieved a low specific contact resistance of 7.41 × 10-6Ω cm2 and contact resistance of 0.54 Ω.mm measured by transmission line mode (TLM), and good surface morphology and edge acuity are also desirable by annealing at 750 ℃ for 30 s. The experiments also indicate that the performance of ohmic contact is first improved, then it reaches a peak, finally degrading with annealing temperature or annealing time rising.  相似文献   

3.
We have demonstrated the effect of annealing temperature on the diffusion density of phosphors in zinc oxide. The P-dopant P430 was sprayed on ZnO pellets and annealed at different temperatures from 500 to 1000℃ with a step of 100℃ for one hour using a programmable furnace. The concentration of P was controlled by varying the annealing temperature and the maximum solubility of P(3% At) was achieved at annealing 800℃ determined by energy dispersive X-ray diffraction(EDX) measurements. X-ray diffraction(XRD) confirmed the hexagonal structure of ZnO and showed that the growth direction was along the c-axis. We observed a maximum up shift in the(002) plane at an annealing temperature of 800℃, suggesting that P atoms replaced Zn atoms in the structure which results in the reduction of the lattice constant. Room temperature photoluminescence(PL) spectrum consists of a peak at 3.28 eV and related to band edge emission, but samples annealed at 800 and 900℃ have an additional donor acceptor pair peak at 3.2 eV. Hall effect measurements confirmed the p-type conductivity of the sample annealed at 800℃.  相似文献   

4.
Photoluminescence origin of nanocrystalline SiC films   总被引:1,自引:0,他引:1  
The nanocrystalline SiC films were prepared on Si then annealed at 800℃ and 1 000℃ for 30 minutes (111) substrates by rf magnetron sputtering and in a vacuum annealing system. The crystal structure and crystallization of as-annealed SiC films were determined by the Fourier transform infrared (FIR) absorption spectra and the X-ray diffraction (XRD) analysis. Measurement of photoluminescence (PL) of the nanocrystalline SiC (nc-SiC) films shows that the blue light with 473 nm and 477 nm wavelengths emitted at room temperature and that the PL peak shifts to shorter wavelength side and the PL intensity becomes stronger as the annealing temperature decreases. The time-resolved spectrum of the PL at 477 nm exhibits a bi-exponential decay process with lifetimes of 600 ps and 5 ns and a characteristic of the direct band gap. The strong blue light emission with short PL lifetimes suggests that the quantum confinement effect of the SiC nanocrystals resulted in the radiative recombination of the direct optical transitions.  相似文献   

5.
A new gate dielectric material HfTiON is deposited by reactive co-sputtering of Hf and Ti targets in N2/O2 ambient, followed by annealing in N2 at 600 ℃ and 800 ℃ respectively for 2 min. Capacitance-voltage and gate-leakage properties are characterized and compared for different anneal conditions. The results indicate that the sample annealed at 800 ℃ exhibits lower interface-state and oxide-charge densities, and better device reliability. This is attributed to the fact that the rapid thermal annealing at the higher temperature of 800 ℃ can effectively remove the damage-induced precipitation, forming a hardened dielectric/Si interface with high reliability.  相似文献   

6.
The Schottky barrier junction parameters and structural properties of Zr/p-GaN Schottky diode are explored at various annealing temperatures. Experimental analysis showed that the barrier height (BH) of the Zr/pGaN Schottky diode increases with annealing at 400℃ (0.92 eV (I-V)/1.09 eV (C-V)compared to the asdeposited one (0.83 eV (I-V)/0.93 eV (C-V). However, the BH decreases after annealing at 500℃. Also, at different annealing temperatures, the series resistance and BH are assessed by Cheung''s functions and their values compared. Further, the interface state density (NSS)of the diode decreases after annealing at 400℃ and then somewhat rises upon annealing at 500℃. Analysis reveals that the maximum BH is obtained at 400℃, and thus the optimum annealing temperature is 400℃ for the diode. The XPS and XRD analysis revealed that the increase in BH may be attributed to the creation of Zr-N phases with increasing annealing up to 400℃. The BH reduces for the diode annealed at 500℃, which may be due to the formation of Ga-Zr phases at the junction. The AFM measurements reveal that the overall surface roughness of the Zr film is quite smooth during rapid annealing process.  相似文献   

7.
The simultaneous control of residual stress and resistivity of polysilicon thin films by adjusting the deposition parameters and annealing conditions is studied. In situ boron doped polysilicon thin films deposited at 520 ℃ by low pressure chemical vapor deposition (LPCVD) are amorphous with relatively large compressive residual stress and high resistivity. Annealing the amorphous films in a temperature range of 600-800 ℃ gives polysilicon films nearly zero-stress and relatively low resistivity. The low residual stress and low resistivity make the polysilicon films attractive for potential applications in micro-electro-mechanical-systems (MEMS) devices, especially in high resonance frequency (high-f) and high quality factor (high-Q) MEMS resonators. In addition, polysilicon thin films deposited at 570 ℃ and those without the post annealing process have low resistivities of 2-5 mΩ·cm. These reported approaches avoid the high temperature annealing process (〉 1000 ℃), and the promising properties of these films make them suitable for high-Q and high-f MEMS devices.  相似文献   

8.
Amorphous silicon films prepared by PECVD on glass substrate have been crystallized by conventional furnace annealing and rapid thermal annealing(RTA), respectively. From the Raman spectra, X- ray diffraction and scanning electron microscope, it is found that the grain size is crystallized at 850 ℃ in both techniques. The thin film made by RTA is smooth and of perfect structure, the thin film annealed by FA has a highly structural disorder. An average grain size of about 30 nm is obtained by both techniques.  相似文献   

9.
The Ti/Al/Ni/Au metals were deposited on undoped AlN films by electron beam evaporation. The influence of annealing temperature on the properties of contacts was investigated. When the annealing temperatures were between 800 and 950℃, the AlN-Ti/Al/Ni/Au contacts became ohmic contacts and the resistance decreased with the increase of annealing temperature. A lowest specific contacts resistance of 0.379 Ω·cm2 was obtained for the sample annealed at 950℃. In this work, we confirmed that the formation mechanism of ohmic contacts on AlN was due to the formation of Al-Au, Au-Ti and Al-Ni alloys, and reduction of the specific contacts resistance could originate from the formation of Au2Ti and AlAu2 alloys. This result provided a possibility for the preparation of AlN-based high-frequency, high-power devices and deep ultraviolet devices.  相似文献   

10.
The effect of the different re-oxidation annealing (ROA) processes on the SiO2/SiC interface charac- teristics has been investigated. With different annealing processes, the flat band voltage, effective dielectric charge density and interface trap density are obtained from the capacitance-voltage curves. It is found that the lowest interface trap density is obtained by the wet-oxidation annealing process at 1050 ℃ for 30 min, while a large num- ber of effective dielectric charges are generated. The components at the SiO2/SiC interface are analyzed by X-ray photoelectron spectroscopy (XPS) testing. It is found that the effective dielectric charges are generated due to the existence of the C and H atoms in the wet-oxidation annealing process.  相似文献   

11.
用MOCVD技术生长GaN:Mg外延膜,在550~950℃温度范围内,对样品进行热退火,并进行室温Hall、光致发光谱(PL)测试.Hall测试结果表明,850℃退火后空穴浓度达到8×1017 cm-3以上,电阻率降到0.8Ω·cm以下.室温PL谱有两个缺陷相关发光峰,位于2.8eV的蓝光峰(BL)以及3.27eV附近的紫外峰(UVL).蓝光峰对紫外峰的相对强度(BL/UVL)在550℃退火后升高,之后随着退火温度的升高(650~850℃)而下降,继续提高退火温度至950℃,BL/UVL急剧上升.空穴浓度先随着Mg掺杂浓度的增加而升高;但继续增加Mg掺杂浓度,空穴浓度反而下降.这些结果表明要实现空穴浓度达1018 cm-3,不仅要考虑H的钝化作用,还要考虑Mg受主的自补偿效应.  相似文献   

12.
热处理和淬火的未掺杂半绝缘LEC GaAs的均匀性   总被引:2,自引:0,他引:2  
对未掺杂原生LECSIGaAs单晶在500~1170℃温度范围进行了单步、两步和三步热处理及淬火,研究了这种热处理对EL2分布的影响,并检测了位错和As沉淀的变化。结果表明,650℃以上温度的热处理可以改善EL2分布均匀性,且在650~950℃温度范围的热处理中,EL2均匀性的改善与热处理后的降温速率无明显联系。此外,两步或三步热处理的样品中EL2分布甚至比单步热处理样品中更优。950℃以下的热处理和淬火对位错和As沉淀无明显影响。但是1170℃热处理井淬火后位错密度增加大约30%,As沉淀消失。对经1170℃淬火的样品再进行80O℃或950℃的热处理,As沉淀重新出现。EL2分布的变化可能与点缺陷、位错和As沉淀的相互作用有关。文中提出了这种相互作用的模型,利用该模型可解释不同条件热处理后EL2分布的变化。  相似文献   

13.
Si0.8Ge0.2strained epilayer were grown on Si substrates by rapid thermal process/very low pressure-chemical vapor deposition(RTP/VLP-CVD)and implanted with boron at 40keV,a dosage of 2.5×10^4cm^-2.Rapid thermal annealing(RTA)and steady-state furnace annealing with different temperature and time period were performed for comparison.Results indicate that RTA is better than furnace annealing.After RTA at750℃-850℃ for 10 s or at 700℃for 40s,the implantation induced damage can be removed,the carrier mobility was about 300cm^2/V·s and the activity was nearly 100%.  相似文献   

14.
喷射CVD法制备金刚石厚膜及其内应力分析   总被引:1,自引:1,他引:0  
采用直流电弧等离子体喷射CVD法制备出金刚石薄膜,利用扫描电子显微镜(SEM)、Raman光谱及X射线衍射(XRD)等研究基底温度对金刚石厚膜生长特性及内应力的影响。结果表明:950℃基底温度生长的金刚石厚膜结晶性能较好,纯度较高;而850℃和1050℃生长的金刚石厚膜表面呈现大量的孪晶缺陷,结晶度较低,同时出现较多的非金刚石碳,纯度较低。随着基底温度的增加,(111)晶面和(311)晶面的衍射峰强度逐渐增强,(220)晶面的衍射峰强度逐渐降低。850℃和950℃基底温度生长的金刚石厚膜的宏观应力和微观应力都呈现出拉应力,1050℃基底温度生长的金刚石厚膜的宏观应力和微观应力都呈现出压应力。  相似文献   

15.
研究了适用于GaAs离子注入材料的石墨红外快速热退火方法,对Si~+注入GaAs材料进行950℃,6秒快速退火。从测得的电学特性,DLTS和GaAs MESFET的研究结果表明,红外快速热退火工艺可获得高质量的有源层以及抑制电子陷阱EL2的外扩散。  相似文献   

16.
Ultrashallow gated diodes have been fabricated using 500-eV boron-ion implantation into both Ge-preamorphized and crystalline silicon substrates. Junction depths following rapid thermal annealing (RTA) for 10 s at either 950°C or 1050°C were determined to be 60 and 80 nm, respectively. These are reportedly the shallowest junctions formed via ion implantation. Consideration of several parameters, e.g. reduced B+ channeling, increased activation, and reduced junction leakage current, lead to the selection of 15 keV as the optimal Ge preamorphization energy. Transmission electron microscope results indicated that an 850°C/10-s RTA was sufficient to remove the majority of bulk defects resulting from the Ge implant. Resulting reverse leakage currents were as low as 1 nA/cm2 for the 60-nm junctions and diode ideality factors for crystalline and preamorphized substrates ranged from 1.02 to 1.12. Even at RTA temperatures as low as 850°C, the leakage current was only 11 nA/cm 2. The final junction depths were found to be approximately the same for both preamorphized and nonpreamorphized samples after annealing at 950°C and 1050°C. However, the preamorphized sample exhibited significantly improved dopant activation  相似文献   

17.
本文用直流磁控溅射方法在离子注入n型GaAs衬底上制备了WSi_xN_y难熔金属膜,研究了它的热稳定性、界面和势垒特性.同时对WSi_(0.6),W,WN等难熔栅金属膜也进行了研究.AES和SIMS分析表明,WSiN/GaAs的界面通过1000℃,10秒钟快速退火(RTA)或850℃,20分钟常规炉退火处理仍保持稳定,势垒高度达到0.8V,理想因子n=1.1.制作了WSiN栅自对准(SAG)增强和耗尽型MESFET.其跨导分别为154mS/mm和250mS/mm.用这一工艺制作的运放差分输入电路从直流到1千兆赫增益达29.5dB.  相似文献   

18.
用电泳法在硅衬底上沉积了ZnO/SiO2复合薄膜,然后在650℃和950℃退火热处理30 min。测试结果表明,样品经650℃退火后,复合薄膜ZnO和SiO2微晶颗粒集结成块状,结晶程度较高,颗粒尺寸较大,不连续的散落在硅衬底上。经950℃退火后,其中ZnO和SiO2发生反应生成少量的ZnSiO4微晶颗粒,使复合薄膜在室温下的绿色发光强度有所增加。  相似文献   

19.
采用磁控溅射的方法在p型GaAs衬底上沉积了Ti/Pt/Au金属薄膜,研究了退火工艺参数(温度和时间)对p-GaAs/Ti/Pt/Au欧姆接触性能的影响。结果表明:p-GaAs上制作的Ti/Pt/Au金属系统能在很短的退火时间(60 s)内形成很好的欧姆接触。过分延长退火时间,并不能改善系统的欧姆接触性能。退火温度在400~450℃时均可得到较好的欧姆接触。当退火温度为420℃,退火时间为120 s时,比接触电阻率达到最低,为1.41×10–6.cm2。  相似文献   

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