共查询到19条相似文献,搜索用时 390 毫秒
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Huffman解码是感知音频解码过程的重要部分。软件实现Huffman解码运算,计算速度慢、功耗高,采用硬件实现的方法,设计并实现了一个兼容MP3与AAC标准的Huffman解码硬件加速器。采用十六叉树搜索算法.在存储空间增加不大的情况下,有效减少了Huffman码字的搜索深度,简化寻址操作,加快了搜索速度。通过直接外设访问的接口设计,该硬件加速器还可快速进行音频码流的数据读取。在XilinixFPGA上的功能和性能验证表明。该Huffman硬件加速器可成功应用于MP3和AAC解码器。 相似文献
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廖腾 《微电子学与计算机》2009,26(6)
改变以往PNG图像中Huffman解码器的软件实现方式,将PNG图像中Huffman解码器用硬件实现,加速PNG图像解码.研究了Huffman解码器在专用集成电路中的实现问题,以PNG图像中的Huffman解码为研究对象,在研究码表的特点和压缩数据的基础上设计出高速的Huffman解码电路.实现的Huffman硬件解码器经EDA工具测试和MATLAB验证,可以完全无失真地解码PNG图像. 相似文献
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Huffman算法的实现是MPEG-4 AAC解码的一个关键部分,它在整个解码算法中占有很大的运算比重和内存开销。讨论了不同的Huffman解码算法及其改进,结合AAC解码器不同码表的特点,针对XScale处理器选择了其合适的Huffman解码算法,并对每种选择的算法从提高解码效率、减少内存开销的角度进行了优化.达到了理想的效果。 相似文献
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针对双核SOC设计开发中使用商用微处理器IP核成本较高的问题,提出了一种基于LEON开源微处理器核的双核SoC平台的构建方案。介绍了LEON开源微处理器软核,通过复用开源的硬件IP软核完成了硬件平台的设计,并基于此双核平台完成了软件设计,实现了JPEG的DSP解码。 相似文献
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本文研究了Huffman解码器在集成电路上的实现问题,在研究解码码表的特点以及简化解码算法的基础上设计出高速Huffman解码电路。这种Huffman解码技术在数字通信领域将会有很大的使用价值。 相似文献
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《IEEE transactions on information theory / Professional Technical Group on Information Theory》1987,33(1):154-156
The data structure of Huffman codes and its application to efficient encoding and decoding of Huffman codes are studied in detail. The tree structure is presented by a two-dimensional array which can be applied for the decoding of Huffman codes as a state transition table of the finite-state decoding automaton. Inversion produces a one-dimensional state transition table of the semiautonomous finite-state sequential machine which can be used as a Huffman encoder with a push-down stack. The encoding and decoding procedures are simple and efficient. It is not only possible to implement by simple hardware but is also applicable to software implementation. 相似文献
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卷积码在多种通信领域中广泛应用,Viterbi译码是对卷积码的一种最大似然译码算法。随着卷积码约束度的增加,并行维特比译码所需的硬件资源呈指数增长,限制其硬件实现。介绍了一种串行译码结构的FPGA实现方案,在保证性能译码的前提下有效地节省资源。同时提出了充分利用FPGA的RAM存储单元的免回溯Viterbi解码实现算法,减少了译码时延,这种算法在串行和并行译码中都可以应用。 相似文献
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The Block Decoder (BD) which is an indispensable component of the JPEG 2000 image compression standard has the highest computational complexity and determines the speed of the overall decoder system. This paper proposes a high throughput pass parallel BD architecture, which can decode more than one bit per clock cycle. In BD, the dependency between context generation and arithmetic decoding unit incorporates stalling and reduces the throughput of the decoding process. The proposed selective byte input and synchronous sample skipping techniques are used to prevent stalling in the decoding process. The proposed architecture achieves 86% more throughput with 50% increment in the hardware cost than that of the best available serial BD architecture. In comparison with the best available pass parallel architecture, throughput improves almost 8.2 times with 61% increment in the hardware cost. Incorporation of the speed up techniques in the design is the main reason for more hardware consumption. The Figure of Merit of the proposed design, which is the ratio of throughput and hardware cost, is more than that of the available BD architectures for typical code block (CB) size of 32 × 32. The ASIC implementation of the proposed design consumes 66 mW power at maximum operating frequency. 相似文献
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在信息快速传输和存储过程中,数据压缩有着重要的作用.从赫夫曼树定义及算法出发,介绍了一个赫夫曼编译码系统的设计与实现过程.这对于深入理解数据结构、程序设计有益. 相似文献
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《Journal of Visual Communication and Image Representation》2014,25(4):689-697
We present a framework for the analysis of the decoding delay in multiview video coding (MVC). We show that in real-time applications, an accurate estimation of the decoding delay is essential to achieve a minimum communication latency. As opposed to single-view codecs, the complexity of the multiview prediction structure and the parallel decoding of several views requires a systematic analysis of this decoding delay, which we solve using graph theory and a model of the decoder hardware architecture. Our framework assumes a decoder implementation in general purpose multi-core processors with multi-threading capabilities. For this hardware model, we show that frame processing times depend on the computational load of the decoder and we provide an iterative algorithm to compute jointly frame processing times and decoding delay. Finally, we show that decoding delay analysis can be applied to design decoders with the objective of minimizing the communication latency of the MVC system. 相似文献
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《IEEE transactions on circuits and systems. I, Regular papers》2009,56(1):144-155
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Low-density parity-check (LDPC) codes, proposed by Gallager, emerged as a class of codes which can yield very good performance on the additive white Gaussian noise channel as well as on the binary symmetric channel. LDPC codes have gained lots of importance due to their capacity achieving property and excellent performance in the noisy channel. Belief propagation (BP) algorithm and its approximations, most notably min-sum, are popular iterative decoding algorithms used for LDPC and turbo codes. The trade-off between the hardware complexity and the decoding throughput is a critical factor in the implementation of the practical decoder. This article presents introduction to LDPC codes and its various decoding algorithms followed by realisation of LDPC decoder by using simplified message passing algorithm and partially parallel decoder architecture. Simplified message passing algorithm has been proposed for trade-off between low decoding complexity and decoder performance. It greatly reduces the routing and check node complexity of the decoder. Partially parallel decoder architecture possesses high speed and reduced complexity. The improved design of the decoder possesses a maximum symbol throughput of 92.95 Mbps and a maximum of 18 decoding iterations. The article presents implementation of 9216 bits, rate-1/2, (3, 6) LDPC decoder on Xilinx XC3D3400A device from Spartan-3A DSP family. 相似文献
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David Gnaedig Emmanuel Boutillon Michel JÉZéquel Vincent C. Gaudet P. Glenn Gulak 《电信纪事》2005,60(1-2):79-102
The main problem with the hardware implementation of turbo codes is the lack of parallelism in the MAP-based decoding algorithm. This paper proposes to overcome this problem by using a new family of turbo codes called Multiple Slice Turbo Codes. This family is based on two ideas: the encoding of each dimension with P independent tail-biting codes and a constrained interleaver structure that allows the parallel decoding of the P independent codewords in each dimension. The optimization of the interleaver is described. A high degree of parallelism is obtained with equivalent or better performance than thedvb-rcs turbo code. For very high throughput applications, the parallel architecture decreases both decoding latency and hardware complexity compared to the classical serial architecture, which requires memory duplication. 相似文献