基于通讯的NoC设计

近年来，一种全新的集成电路体系结构——Network on Chip（NoC）已经成为徽电子学科研究的热点佃题之一，其核心思想是将计算机网络技术移植到芯片设计中来，从体系结构上彻底解决片上通讯的瓶颈问题。文章提出了一种基于通讯的NoC设计方法，通过监控和协调NoC的网络通讯来获得更好的性能．并总结了实现该设计方法所必须研究的关键技术。     

片上网络拓扑结构的研究

随着SoC体系结构设计复杂度的提高,传统的总线结构已成为IP核之间通信的瓶颈。为了满足大规模集成电路发展对扩展性、能耗、面积、时钟异步、重用性、QoS等方面的需求,新的设计方法—片上网络(NoC)应运而生,它是对原有设计模式的一次革新。本文分析了NoC的技术特点以及在该领域中的关键技术,详细地对NoC中常见的拓扑结构进行了分类研究,并指出了每种拓扑结构中的优点与不足;然后通过分析每种拓扑结构的性能参数,从而对其性能进行综合的比较。     

北京联合大学微电子应用技术研究所

北京联合大学微电子应用技术研究所依托“信息与通信系统”和“电子科学与技术”两个一级学科，集学科建设、人才培养和研究工作于一体。重点研究领域为通信与信息系统专用集成电路、NoC与SoC技术。2005年以来投资500余万元建立了技术比较完整的集成电路设计实验室，同时还与Mentor公司成立了集成电路联合设计实验室。     

从SOC到NOC的集成电路设计技术发展

遵循摩尔定律的预言,半导体集成电路工艺技术持续高速向深亚微米工艺发展,大规模集成电路设计技术是发展过程中需要解决的关键问题.基于片上总线的SOC设计技术解决了大规模集成电路的设计难点,但是片上总线的应用带来了可扩展性差、平均通信效率低等问题.近几年研究提出全新的集成电路体系结构NOC,是将计算机网络技术移植到芯片设计中,从体系结构上彻底解决了SOC设计技术存在的问题.因此,NOC将成为集成电路下一代主流设计技术.     

IC设计技术中的IP核互连

随着IC设计复杂度的不断提高,在SoC中集成的IP核越来越多,基于片上总线的SOC设计技术解决了大规模集成电路的设计难点,但是片上总线的应用带来了可扩展性差、平均通信效率低等问题。近几年来,将英特网络中分层互连的思想引入到SOC设计中IP核的互连上来,提出了全新的集成电路体系结构——片上网络（NOC）,NOC从多处理体系结构、消除时钟树以节省资源、实现并行通信等几个方面,展示了优于总线结构的本质和特性,成功地解决了SOC设计中存在的问题。     

接口标记容错路由算法

随着片上系统(SoC)集成度的不断提高,IP核之间的通信故障成为亟待解决的问题,片上网络(NoC)是解决SoC通信问题的有效途径。容错路由算法是NoC设计中的关键技术,对NoC的通信效率有重要影响。在Valiant随机路由算法和源路由算法的基础上,提出了一种接口标记容错路由算法。该算法吸取了Valiant随机路由算法能平衡网络负载、降低拥塞概率的优良性能与源路由算法中路径不需要计算与查找的特点,减小了传输时延,提高了路由器的利用率。     

NoC系统设计的研究

片上网络研究涉及从物理设计到体系结构、系统应用、设计方法和工具等诸多方面.文中从系统结构的角度总结了片上网络设计的一些主要研究内容和NoC技术研究发展方向.     

低功耗优先的片上网络映射优化方法

在分析片上网络通讯功耗与通讯流量的关系模型的基础上,针对片上网络设计中的映射问题,提出了一种新的降低通讯功耗的映射方法,该方法首先对映射过程做预处理,划分成若干候选图,将通讯量大的IP核映射到与其他资源节点距离较短的位置上,利用预处理的结果产生初始解,结合流量估算技术对映射空间动态搜索,从而实现将通讯任务图中的IP核映射到NoC结构图的资源节点上.实验结果表明该方法能有效地降低NoC的通讯流量,从而更加适合求解片上网络的低功耗映射问题.     

优化NoC性能的存储和通信压缩

文中针对NoC体系结构,提出了两种数据压缩技术,被称为高速缓存压缩和网络接口控制(NIC)内的压缩.性能实测结果指示压缩能够使NoC设计在较低的网络延迟、较低的功耗和改进应用性能等方面获得优势.     

SoC技术现状及其挑战

当前,在微电子及其应用领域正在发生一场前所未有的变革,这场变革是由片上系统（SoC）技术研究应用和发展引起的。从技术层面看,SoC技术是超大规模集成电路发展的必然趋势和主流,它以超深亚微米VDSM（Very Deep Submicron）工艺和知识产权IP核复用技术为支撑。     

Mapping and Scheduling for Circuit‐Switched Network‐on‐Chip Architecture

Network‐on‐chip (NoC) architecture provides a high‐performance communication infrastructure for system‐on‐chip designs. Circuit‐switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real‐time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication circuits, and allocates a proper bandwidth for each circuit. Simulation results show that the average waiting times of packets in a switch in 6×6, 8×8, and 10×10 mesh NoC networks are 0.59, 0.62, and 0.61, respectively. The latency of circuits is significantly decreased. Furthermore, the buffer of a switch in NoC only needs to accommodate the data of one time slot. The cost of the switch in the circuit‐switched network can be reduced using our scheme. Our design provides an effective solution for a critical step in NoC design.     

3DNoC关键通信部件容错方法研究综述

三维片上网络通过硅通孔（Through Silicon Via,TSV）将多层芯片进行堆叠,具有集成密度大,通信效率高等特点,是片上多核系统的主流通信架构。然而,工艺偏差及物理缺陷所引发的错误和TSV良率较低等因素,使得三维片上网络面临严重的故障问题。为保证通信效率,对三维片上网络关键通信部件进行容错设计必不可少。本文针对三维片上网络关键通信部件———路由器和TSV的故障和容错相关问题,从容错必要性、国内外研究现状、未来的研究方向和关键问题、以及拟提出的相关解决方案四个方面,展开深入探讨。为提高片上网络可靠性、保证系统高效通信提供一体化的解决方案。     

On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems

Homogeneous manycore systems are emerging for tera-scale computation and typically utilize Network-on-Chip (NoC) as the communication scheme between embedded cores. Effective defect tolerance techniques are essential to improve the yield of such complex integrated circuits. We propose to achieve fault tolerance by employing redundancy at the core-level instead of at the microarchitecture level. When faulty cores exist on-chip in this architecture, however, the physical topologies of various manufactured chips can be significantly different. How to reconfigure the system with the most effective NoC topology is a relevant research problem. In this paper, we first show that this problem is an instance of a well known NP-complete problem. We then present novel solutions for the above problem, which not only maximize the performance of the on-chip communication scheme, but also provide a unified topology to Operating System and application software running on the processor. Experimental results show the effectiveness of the proposed techniques.      

连接圭从IP核的片上网络路由器结构

随着单个芯片上集成的元器件数目不断增加,功耗问题也变得越来越突出。片上网络虽然能够从理论上解决传统总线结构带来的种种问题,但其功耗问题在某些具体应用中却变成了关键的制约因素。路由器作为片上网络的核心部件,其结构直接影响片上网络的性能。路由器的功耗问题已经成为片上网络领域一个热点问题。本文运用最优化理论对连接主从IP核的片上网络路由器结构进行优化设计,并运用路由器的功耗模型对功耗问题进行了分析。最后运用OPNET仿真软件对路由器的交换机制和路由算法进行分析对比,得出最终结论。     

Partial Virtual Channel Sharing: A Generic Methodology to Enhance Resource Management and Fault Tolerance in Networks-on-Chip

We present a novel Partial Virtual channel Sharing (PVS) NoC architecture which reduces the impact of faults on performance and also tolerates faults within the routing logic. Without PVS, failure of a component impairs the fault-free connected components, which leads to considerable performance degradation. Improving resource utilization is key in enhancing or sustaining performance with minimal overhead when faults or overload occurs. In the proposed architecture, autonomic virtual-channel buffer sharing is implemented with a novel algorithm that determines the sharing of buffers among a set of ports. The runtime allocation of the buffers depends on incoming load and fault occurrence. In addition, we propose an efficient technique for maintaining the accessibility of a processing element (PE) to the network even if its router is faulty. Our techniques can be used in any NoC topology and for both, 2D and 3D NoCs. The synthesis results for an integrated video conference application demonstrate 22 % reduction in average packet latency compared to state-of-the-art virtual channel (VC) based NoC architecture. Extensive quantitative simulation has been carried out with synthetic benchmarks. Simulation results reveal that the PVS architecture improves the performance significantly in presence of faults, compared to other VC-based NoC architectures.     

片上网络调度算法相关研究

随着半导体集成工艺的发展,单个芯片上集成的IP核数目急剧增加,片上网络(NoC)成为未来取代总线设计的新模式。调度算法作为NoC研究的关键问题之一,对整个网络的传输性能起着重要的作用。本文对片上网络虚信道路由器调度算法的相关研究进展进行了总结,首先从路由器结构特点出发,介绍了几种典型的NoC仲裁器和调度器实例,总结相应的算法设计思想。再对NoC常用路由器调度算法进行了分类介绍,详细分析了各种调度算法的相关特性。最后,探讨了NoC路由器调度算法的研究方向。     

Test Scheduling of NoC‐Based SoCs Using Multiple Test Clocks

Network‐on‐chip (NoC) is an emerging design paradigm intended to cope with future systems‐on‐chips (SoCs) containing numerous built‐in cores. Since NoCs have some outstanding features regarding design complexity, timing, scalability, power dissipation and so on, widespread interest in this novel paradigm is likely to grow. The test strategy is a significant factor in the practicality and feasibility of NoC‐based SoCs. Among the existing test issues for NoC‐based SoCs, test access mechanism architecture and test scheduling particularly dominate the overall test performance. In this paper, we propose an efficient NoC‐based SoC test scheduling algorithm based on a rectangle packing approach used for current SoC tests. In order to adopt the rectangle packing solution, we designed specific methods and configurations for testing NoC‐based SoCs, such as test packet routing, test pattern generation, and absorption. Furthermore, we extended and improved the proposed algorithm using multiple test clocks. Experimental results using some ITC’02 benchmark circuits show that the proposed algorithm can reduce the overall test time by up to 55%, and 20% on average compared with previous works. In addition, the computation time of the algorithm is less than one second in most cases. Consequently, we expect the proposed scheduling algorithm to be a promising and competitive method for testing NoC‐based SoCs.     

A hardened network-on-chip design using runtime hardware Trojan mitigation methods

Due to the globalized semiconductor business model, malicious hardware modifications, known as hardware Trojans (HTs), have risen up as a big concern for chip security. HT detection and mitigation methods for general integrated circuits have been investigated in the past decade. However, the majority of the existing efforts are not customized for HTs in Networks-on-Chip (NoCs). To complement the firmware and software level methods for rogue NoCs detection, we propose countermeasures to harden the NoC hardware design against tampering. More specifically, we propose a collaborative dynamic permutation and flit integrity check method to mitigate the potential inside-router HTs inserted by the disloyal member in the NoC design house or the 3^rd-party system integration company. Our method improves the number of received packets by up to 70.1% over the other methods if the HT controls the NoC packet destination address. The average link availability of our method is 43.7% higher than that of the exiting methods. Our method increases the effective average latency by up to 63.4%, 68.2%, and 98.9% for the single HT in the destination, header, and tail fields, respectively, over the existing methods.     

基于网络监控器的专用片上网络动态容错路由

针对专用片上网络（Network on Chip,NoC）全局通信事务管理和可靠性设计问题,提出片上网络监控器的概念,用于获取全局网络实时状态信息及执行路径分配算法,基于此提出一种动态路由机制DyRS-NM.该机制能检测和定位NoC中的拥塞和故障链路,并能区分瞬时和永久性链路故障,采用重传方式避免瞬时故障,通过重新路由计算绕开拥塞和永久性故障.设计实现了RTL级网络监控器和与之通信的容错路由器模块,并将MPEG4解码器应用映射至基于网络监控器的4×4Mesh结构NoC体系结构中,验证了系统性能以及面积功耗开销.相比静态XY路由和容错动态路由FADR,DyRS-NM机制在可接受的开销代价下获得了更优的性能.