A clarification on bus-cut diakoptics

The brevity required in the paper by Sasson and Brown (A. M. Sasson and H. E. Brown, "Deductions and clarifications on the diakoptics approach," in 1971 7th PICA Conf. Proc., pp. 433-439) obscures a computational aspect important to the tutorial and application value of their "bus-cut" method. A numerical example is presented here to help clarify this computation.     

Post electrochemical Cu deposition anneal impact on stress-voiding in individual vias

Stress-voiding is a critical reliability issue in Cu dual-damascene interconnects which could induce via openings. In our case, voids are typically observed at the edges at the bottom of vias. This location is correlated to a local delamination at Cu/Ta interface [E.T. Ogawa, J.W. McPherson, J.A. Rosal, M.J. Dickerson, T.-C. Chiu, L.Y. Tsung, M.K. Jain, T.D. Bonifield, J.C. Ondrusek, W.R. McKee, IEEE Int. Rel. Phys. Symp. Proc. (2002) 312-321; Y.K. Lim et al., Stress-induced voiding in multi-level copper/low-k interconnects, IEEE Int. Rel. Phys. Symp. Proc. (2004) 240-245]. Then, Cu/Ta interface properties at the bottom of via seem to be in the critical path for stress-voiding. In this paper, stress-voiding on 300 mm wafers in individual vias for different post electrochemical Cu deposition (ECD) anneals is studied. Electrical results show the clear benefit of hot plate and short furnace annealings. Microstructural characterizations indicate that impurities accumulation at Cu/Ta interface during long annealings could drive preferred void nucleation.     

Epitaxial layer induced series resistance and microwave properties of NNP Si X band impatt diodes

Following Gummel-Blue approach [1] [H.K. Gummel, J. L. Blue, IEEE Trans. Electron. Devices 14(1967) pp. 569-572.], the effect of undepleted epitaxial layers on the series resistance (R_s) as well as on its microwave properties of single drift region (n⁺np⁺) Si IMPATT diodes [2] [M. Mitra, M. Das, S. Kar, S.K. Roy, IEEE Trans. Electron. Devices 40(1993) pp. 1890-1893.] with flat doping profile with capacity 0.2PF at X band under experimental bias current of 25 mA and temperature 373 K have been studied. The computation for series resistance fits well with the device data for flat doping profile [2] [M. Mitra, M. Das, S. Kar, S.K. Roy, IEEE Trans. Electron. Devices 40(1993) pp. 1890-1893.]. The same study has also been simulated on its low-high-low (lhl) doping profile counterpart. The value of R_s increases approximately linearly with the increase of undepleted epi-layer thickness determined by the doping density for both flat and lhl structure. The value of R_s decreases remarkably as the doping profile changes from flat to lhl type.     

A precision noise measurement and analysis method used to estimate reliability of semiconductor devices

In this paper, some problems with previous ultra-low noise measurement methods have been discussed, then a double-channel preamplifier cross-spectrum measurement method has been adopted, different from the previous cross-correlation method [A. van der Ziel, Noise: Sources, Characterization, Measurement, p. 54. Prentice-Hall, Englewood Cliffs, NJ (1970), L. Stor, Experimental techniques in noise measurement with special emphasis on precision measurement, Proc. 10th Int. Conf. on Noise in Physical Systems, pp. 551–560. Budapest, Hungary (1989)] in that an average periodogram using a windowing procedure has been performed. The theoretical analysis shows that the expected value of the cross-spectrum is incoherent with background noise and zero-drift from the preamplifier and power supply system, the average periodogram can decrease the variance of the periodogram and the additional bias of the cross-spectrum periodogram.Experimental results demonstrate that if the equivalent input noise of measuremental set-up is two orders of magnitude lower than the noise of each preamplifier, then an ultra-low noise spectrum can be measured accurately, the low limit is about 0.1 nV/√Hz at 1 kHz, which is 20 dB lower than the noise of each preamplifier. The thermal noise of a small resistance and the shot noise of a diode under forward conditions have been measured, the experimental results are in good agreement with the theoretical value, this means that this method is feasible and accurate for an ultra-low noise spectrum measurement.Finally, the noise spectrum analysis procedure based on the curve fitting method has been presented, which ensures that we obtain an accuracy value of three noise components in the semiconductor, i.e. noise, white noise and g-r noise. This noise spectrum analysis method is a useful tool for investigation of noise mechanism, the diagnosis of defects in semiconductors and reliability estimation.     

One and Two-Weight Z2R2 Additive Codes

This paper is devoted to the construction of one and two-weight Z2R2 additive codes, where R2 =F2[v]/. It is a generalization towards another direction of Z2Z4 codes (S.T. Dougherty, H.W. Liu and L. Yu,"One weight Z2Z4 additive codes", Applicable Algebra in Engineering, Communication and Computing, Vol.27, No.2, pp.123–138, 2016). A MacWilliams identity which connects the weight enumerator of an additive code over Z2 R2 and its dual is established. Several construction methods of one-weight and two-weight additive codes over Z2 R2 are presented. Several examples are presented to illustrate our main results and some open problems are also proposed.     

Implementation of a Multi-band Pulsed-OFDM Transceiver

A multi-band orthogonal frequency division multiplexing (OFDM) ultra wideband (UWB) system is being considered for the IEEE 802.15.3a wireless personal area networks. An enhancement to this system, named pulsed-OFDM, has been proposed to reduce the complexity and power consumption of the transceiver without sacrificing performance. In this paper, we describe a detailed implementation of a pulsed-OFDM transceiver. The main focus of the paper is designing each section with maximum power saving and minimum complexity. Specially we design each section such that each part of the pulsed-OFDM transceiver has less or equal complexity and power consumption than the corresponding part in the original multi-band OFDM transceiver. Different options to implement encoder and decoder as well as modulator and demodulator (Inverse Fast Fourier Transform and Fast Fourier Transform) are examined. We also present the simulation results to choose appropriate resolution for analog-to-digital and digital-to-analog converters (ADC and DAC). Finally we investigate the effect of fixed point arithmetic in calculating FFTs and required resolution using simulation results. Ebrahim Saberinia received his BS and MS degrees both in Electrical Engineering from Sharif University of Technology, Tehran, Iran in 1996 and 1998 respectively, and PhD degree in Electrical and Computer Engineering from the University of Minnesota, Minneapolis in 2004. Currently he is an assistant professor at the Department of Electrical and Computer Engineering, University of Nevada, Las Vegas. His research interests includes: wireless communications, signal processing and wireless networks. His current research activities include ultra wideband communications and wireless personal area networks. Kai-Chuan Chang received his BS degrees in Electrical Engineering and Mathematics with Summa Cum Laude in 2000 from University of Minnesota, Minneapolis. He is the recipient of the University of Minnesota graduate school fellowship in 2000. He obtained his MS in Electrical Engineering in 2002 from University of Minnesota. He is currently working on his PhD degree in the area of VLSI implementation of UWB OFDM systems at University of Minnesota, Minneapolis. Gerald E. Sobelman received a B.S. in physics, summa cum laude, from the University of California, Los Angeles in 1974. He was awarded M.A. and Ph.D. degrees in physics from Harvard University in 1976 and 1979, respectively. He has held positions at The Rockefeller University, Sperry Corporation and Control Data Corporations. Since 1986, he has been a faculty member at the University of Minnesota. His current research interests are in the areas of VLSI and SoC design for applications in communications, signal processing, coding and cryptography. He has published more than 60 research papers, is a co-author of one book and holds 10 U.S. patents. He has been a member of the program committees for IEEE ISCAS and SOCC and has served as an Associate Editor for IEEE Signal Processing Letters. Ahmed H. Tewfik (Fellow IEEE) received his B.Sc. degree from Cairo University, Cairo Egypt, in 1982 and his M.Sc., E.E. and Sc.D. degrees from the Massachusetts Institute of Technology, Cambridge, MA, in 1984, 1985 and 1987 respectively. Dr. Tewfik has worked at Alphatech, Inc., Burlington, MA in 1987. He is the E. F. Johnson professor of Electronic Communications with the department of Electrical Engineering at the University of Minnesota. He served as a consultant to MTS Systems, Inc., Eden Prairie, MN, Emerson-Rosemount, Inc., Eden Prairie, MN, CyberNova, Milipitas, CA, Macrovision, Santa Clara, CA, Visionaire Technology, Fremont, CA and Ipsos, New York. He worked with Texas Instruments and Computing Devices International. From August 1997 to August 2001, he was the President and CEO of Cognicity, Inc., an entertainment marketing software tools publisher that he co-founded, on partial leave of absence from the University of Minnesota. His current research interests are in programmable wireless networks, genomics and proteomics, healthcare safety and datanomic and pervasive computing and storage. Prof. Tewfik is a Fellow of the IEEE. He was a Distinguished Lecturer of the IEEE Signal Processing Society in 1997–1999. He received the IEEE third Millennium award in 2000. He was invited to be a principal lecturer at the 1995 IEEE EMBS summer school. He was awarded the E. F. Johnson professorship of Electronic Communications in 1993, a Taylor faculty development award from the Taylor foundation in 1992 and an NSF research initiation award in 1990. He delivered plenary lectures at several IEEE and non-IEEE meetings, including the 1994 IEEE Int. Conf. on Acoust. Speech and Signal Proc. (ICASSP’94), the 1999 IEEE-EURASIP Workshop on Nonlinear Signal and Image Processing, the 1999 IEEE Turkish Signal Processing Conference (SIU 99), the 1^st IEEE International Symposium on Signal Processing and Information Theory (2001), SSGRR2002w International Conference on Advances in Infrastructure for Electronic Business, Science, and Education on the Internet, the 2003 European Union COST meeting and the 10^th IEEE International Conference on Electronics, Circuits and Systems. He gave invited tutorials on ultrawideband communications at the 2003 Fall IEEE Vehicular Technology Conference, watermarking at the 1998 IEEE International Conference on Image Processing and wavelets at the 1994 IEEE workshop on Time-Frequency and Time-Scale Analysis. He was selected to be the first Editor-in-Chief of the IEEE Signal Processing Letters from 1993 to 1999. He is a past associate editor of the IEEE Trans. on Signal Proc., was a guest editor of three special issue of that journal on wavelets and their applications and watermarking and a guest editor of a special issue of the IEEE Trans. on Multimedia on multimedia databases. He also served as the president of the Minnesota chapters of the IEEE signal processing and communications societies for the past 3 years.     

Characterisation of electroplated Sn/Ag solder bumps

Environmental concerns as well as legal constraints have been pushing research on flip chip technology towards the development of lead-free solders and also to new deposition techniques [Z.S. Karim, R. Schetty, Lead-free bump interconnections for flip-chip applications, in: IEEE/CPMT 1nternational Electronics Manufacturing Technology Symposium, 2000, pp. 274-278, P. Wölflick, K. Feldmann, Lead-free low-cost flip chip process chain: layout, process, reliability, in: IEEE International Electronics Manufacturing Technology (IEMT) Symposium, 2002, pp. 27-34, M. McCormack, S. Jin, The design and properties of new, pb-free solder alloys, in: IEEE/CPMT International Electronics Manufacturing Technology Symposium, 1994, pp. 7-14, T. Laine-Ylijoki, H. Steen, A. Forsten, Development and validation of a lead-free alloy for solder paste applications. IEEE Transactions on Components, Packaging, and Manufacturing technology, 20(3) (1997) 194-198, D. Frear, J. Jang, J. Lin, C. Zhang, Pb-free solders for flip-chip interconnects, JOM, 53(6) (2001) 28-32].Binary and ternary tin alloys are promising candidates to substitute lead-content components. In this paper, we describe an electroplating technique for high density FlipChip packaging [M. Bigas, E. Cabruja, Electrodeposited Sn/Ag for flip chip connection, CDE (2003)]. An analysis using Auger Electron Spectroscopy (AES) together with additional Energy Dispersive Xray analysis (EDS) tests and Scanning Electron Microscope (SEM) analysis have been performed to optimize the reflow process of the electrodeposited bumps.     

Authenticated Adversarial Routing

The aim of this paper is to demonstrate the feasibility of authenticated throughput-efficient routing in an unreliable and dynamically changing synchronous network in which the majority of malicious insiders try to destroy and alter messages or disrupt communication in any way. More specifically, in this paper we seek to answer the following question: Given a network in which the majority of nodes are controlled by a node-controlling adversary and whose topology is changing every round, is it possible to develop a protocol with polynomially bounded memory per processor (with respect to network size) that guarantees throughput-efficient and correct end-to-end communication? We answer the question affirmatively for extremely general corruption patterns: we only request that the topology of the network and the corruption pattern of the adversary leaves at least one path each round connecting the sender and receiver through honest nodes (though this path may change at every round). Out construction works in the public-key setting and enjoys optimal transfer rate and bounded memory per processor (that is polynomial in the network size and does not depend on the amount of traffic). We stress that our protocol assumes no knowledge of which nodes are corrupted nor which path is reliable at any round, and is also fully distributed with nodes making decisions locally, so that they need not know the topology of the network at any time. The optimality that we prove for our protocol is very strong. Given any routing protocol, we evaluate its efficiency (rate of message delivery) in the “worst case,” that is with respect to the worst possible graph and against the worst possible (polynomially bounded) adversarial strategy (subject to the above mentioned connectivity constraints). Using this metric, we show that there does not exist any protocol that can be asymptotically superior (in terms of throughput) to ours in this setting. We remark that the aim of our paper is to demonstrate via explicit example the feasibility of throughput-efficient authenticated adversarial routing. However, we stress that out protocol is not intended to provide a practical solution, as due to its complexity, no attempt thus far has been made to reduce constants and memory requirements. Our result is related to recent work of Barak et al. (Proc. of Advances in Cryptology—27th EUROCRYPT 2008, LNCS, vol. 4965, pp. 341–360, 2008) who studied fault localization in networks assuming a private-key trusted-setup setting. Our work, in contrast, assumes a public-key PKI setup and aims at not only fault localization, but also transmission optimality. Among other things, our work answers one of the open questions posed in the Barak et al. paper regarding fault localization on multiple paths. The use of a public-key setting to achieve strong error-correction results in networks was inspired by the work of Micali et al. (Proc. of 2nd Theory of Cryptography Conf., LNCS, vol. 3378, pp. 1–16, 2005) who showed that classical error correction against a polynomially bounded adversary can be achieved with surprisingly high precision. Our work is also related to an interactive coding theorem of Rajagopalan and Schulman (Proc. 26th ACM Symp. on Theory of Computing, pp. 790–799, 1994) who showed that in noisy-edge static-topology networks a constant overhead in communication can also be achieved (provided none of the processors are malicious), thus establishing an optimal-rate routing theorem for static-topology networks. Finally, our work is closely related and builds upon to the problem of End-To-End Communication in distributed networks, studied by Afek and Gafni (Proc. of the 7th ACM Symp. on Principles of Distributed Computing, pp. 131–148, 1988); Awebuch et al. (Proc. of the 30th IEEE Symp. on Foundations of Computer Science, FOCS, 1989); Afek et al. (Proc. of the 11th ACM Symp. on Principles of Distributed Computing, pp. 35–46, 1992); and Afek et al. (J. Algorithms 22:158–186, 1997), though none of these papers consider or ensure correctness in the setting of a node-controlling adversary that may corrupt the majority of the network.     

Test of switched-capacitor ladder filters using OBT

In this paper, a way to test switched-capacitors ladder filters by means of Oscillation-Based Test (OBT) methodology is proposed. Third-order low-pass Butterworth and Elliptic filters are considered in order to prove the feasibility of the proposed approach. A topology with a non-linear element in an additional feedback loop is employed for converting the Circuit Under Test (CUT) into an oscillator. The idea is inspired in some author's previous works (G. Huertas, D. Vázquez, A. Rueda, J.L. Huertas, Oscillation-based Test Experiments in Filters: a DTMF example, in: Proceedings of the International Mixed-Signal Testing Workshop (IMSTW'99), British Columbia, Canada, 1999, pp. 249–254; G. Huertas, D. Vazquez, E. Peralías, A. Rueda, J.L. Huertas, Oscillation-based test in oversampling A/D converters, Microelectronic Journal 33(10) (2002) 799–806; G. Huertas, D. Vázquez, E. Peralías, A. Rueda. J.L. Huertas, Oscillation-based test in bandpass oversampled A/D converters, in: Proceedings of the International Mixed-Signal Test Workshop, June 2002, Montreaux (Switzerland), pp. 39–48; G. Huertas, D. Vázquez, A. Rueda, J.L. Huertas, Practical oscillation-based test of integrated filters, IEEE Design and Test of Computers 19(6) (2002) 64–72; G. Huertas, D. Vázquez, E. Peralías, A. Rueda, J.L. Huertas, Testing mixed-signal cores: practical oscillation-based test in an analog macrocell, IEEE Design and Test of Computers 19(6) (2002) 73–82). Two methods are used, the describing function approach for the treatment of the non linearity and the root-locus method for analysing the circuit and predicting the oscillation frequency and the oscillation amplitude. In order to establish the accuracy of these predictions, the oscillators have been implemented in SWITCAP (K. Suyama, S.C. Fang, Users' Manual for SWITCAP2 Version 1.1, Columbia University, New York, 1992). Results of a catastrophic fault injection in switches and capacitors of the filter structure are reported. A specification-driven fault list for capacitors is also defined based on the sensitivity analysis. The ability of OBT for detecting this kind of faults is presented.     

Handling routability in floorplan design with twin binary trees

As technology moves into the deep-submicron era, the complexities of VLSI circuits grow rapidly. Interconnect optimization has become an important concern. Most routability-driven floorplanners [H.M. Chen, H. Zhou, F.Y. Young, D.F. Wong, H.H. Yang, N. Sherwani, Integrated floorplanning and interconnect planning, in: Proceedings of IEEE International Conference on Computer-Aided Design, 1999, pp. 354–357; S. Krishnamoorthy, J. Lou, H.S. Sheng, Estimating routing congestion using probabilistic analysis, in: Proceedings of International Symposium on Physical Design, 2001, pp. 112–117; M. Wang, M. Sarrafzadeh, Modeling and minimization of routing congestion, in: IEEE Asia and South Pacific Design Automation Conference, 2000, pp. 185–190] use grid-based approach that divides a floorplan into grids as in global routing to estimate congestion by the expected number of nets passing through each grid. This approach is direct and accurate, but not efficient enough when dealing with complex circuits containing many nets. In this paper, an efficient and innovative interconnect-driven floorplanner using twin binary trees (TBT) representation [B. Yao, H. Chen, C.K. Cheng, R. Graham, Revisiting floorplan representations, in: Proceedings of International Symposium on Physical Design, 2001, pp. 138–143; E.F.Y. Young, C.C.N. Chu, Z.C. Shen, Twin binary sequences: a non-redundant representation for general non-slicing floorplan, in: Proceedings of International Symposium on Physical Design, 2002, pp. 196–201] is proposed. The estimations are based on the wire densities (number of wires passing through per unit length) on the half-perimeter boundaries of different regions in a floorplan. These regions are defined naturally by the TBT representation. Buffer planning is also considered by deciding if buffers can be inserted successfully for each net. In order to increase the efficiency of our floorplanner, a fast algorithm for the least common ancestor (LCA) problem in Bender and Farach-Colton [The LCA problem revisited, in: Latin American Theoretical INformatics, 2000, pp. 88–94] is used to compute wire density, and a table look-up approach is used to obtain the buffer insertion information. Experimental results show that our floorplanner can reduce the number of unroutable wires. The performance is comparable with other interconnect-driven floorplanners that perform global routing-like operations directly to estimate routability, but our estimation method is much faster and is scalable for large complex circuits.     

Markov model assessment of subjects' clinical skill using the E-Pelvis physical simulator

Inherent difficulties evaluating clinical competence of physicians has led to the widespread use of subjective skill assessment techniques. Inspired by an analogy between spoken language and surgical procedure, a generalized methodology using Markov models (MMs), independent of the modality under study, was developed. The methodology applied to an endoscopic experiment in "Generalized approach for modeling minimally invasive surgery as a stochastic process using a discrete Markov model" by J. Rosen et al. (IEEE Trans. Biomed. Eng., Vol. 53, No. 3, pp. 399-413, Mar. 2006) is modified and applied to data collected with the E-Pelvis physical simulator. The simulator incorporates five contact pressure sensors located in key anatomical landmarks. Two 32-state fully connected MMs are used, one for each skill level. Each state corresponds to a unique five-dimensional signature of contact pressures. Statistical distances measured between models representing subjects with different skill levels are sensitive enough to provide an objective measure of medical skill level. The method was tested with 41 expert subjects and 41 novice subjects in addition to the 30 subjects used for training the MM. Of the 82 subjects, 76 (92%) were classified correctly. Unique state transitions as well as pressure magnitudes for corresponding states were found to be skill dependent. The "white box" nature of the model provides insight into the examination process performed.     

Hard-Fault Detection and Diagnosis During the Application of Model-Based Data Converter Testing

The concept of model-based test was developed in order to reduce the production test effort for data converters (Cherubal and Chatterjee (IEEE Trans Circuits Syst part I 50(3):317–327, 2003); Stenbakken and Souders (1985) Modelling and test point selection for data converter testing. In: ITC, Int Test Conf, pp 813–817; Wegener and Kennedy (IEEE Trans Circuits Syst I 51(1):213–217, 2004); Wrixon and Kennedy (IEEE Trans Instrum Meas IM-48(5):978–985, 1999)). In applying this concept, a vector of model parameters is determined for each device under test (DUT). Typically, this model parameter vector is merely used to calculate the DUT performance characteristic which is then subject to specification-oriented testing. However, each element of the model parameter vector represents an independent error source which contributes to performance degradations; thus, the model parameter vector can be viewed as a signature of the error sources. In this work, analyzing the error source signature is used to devise a model-based methodology for hard-fault detection and diagnosis. We investigate conditions under which hard-faults are detectable/diagnosable in spite of masking effects due to manufacturing process variations. In particular, we show that taking the model parameter vector as the fault signature is optimal as it minimizes the masking effects and thus maximizes detectability/diagnosibility.

The convex-concave characteristics of Gaussian channel capacity functions

In this correspondence, we give several inherent properties of the capacity function of a Gaussian channel with and without feedback by using some operator inequalities and matrix analysis. We give a new proof method which is different from the method appearing in: K. Yanagi and H. W. Chen, "Operator inequality and its application to information theory," Taiwanese J. Math., vol. 4, no. 3, pp. 407-416, Sep. 2000. We obtain the following results: C/sub n,Z/(P) and C/sub n,FB,Z/(P) are both concave functions of P, C/sub n,Z/(P) is a convex function of the noise covariance matrix and C/sub n,FB,Z/(P) is a convex-like function of the noise covariance matrix. This new proof method is very elementary and the results shall help study the capacity of Gaussian channel. Finally, we state a conjecture concerning the convexity of C/sub n,FB,/spl middot//(P).     

Exploring the potential of Siamese network for RGBT object tracking

Siamese tracking is one of the most promising object tracking methods today due to its balance of performance and speed. However, it still performs poorly when faced with some challenges such as low light or extreme weather. This is caused by the inherent limitations of visible images, and a common way to cope with it is to introduce infrared data as an aid to improve the robustness of tracking. However, most of the existing RGBT trackers are variants of MDNet (Hyeonseob Nam and Bohyung Han, Learning multi-domain convolutional neural networks for visual tracking, in: Proceedings of the IEEE conference on computer vision and pattern recognition, 2016, pp. 4293–4302.), which have significant limitations in terms of operational efficiency. On the contrary, the potential of Siamese tracking in the field of RGBT tracking has not been effectively exploited due to the reliance on large-scale training data. To solve this dilemma, in this paper, we propose an end-to-end Siamese RGBT tracking framework that is based on cross-modal feature enhancement and self-attention (SiamFEA). We draw on the idea of migration learning and employ local fine-tuning to reduce the dependence on large-scale RGBT data and verify the feasibility of this approach, and then we propose a reliable fusion approach to efficiently fuse the features of different modalities. Specifically, we first propose a cross-modal feature enhancement module to exploit the complementary properties of dual-modality, followed by capturing non-local attention in channel and spatial dimensions for adaptive weighted fusion, respectively. Our network was trained end-to-end on the LasHeR (Chenglong Li, Wanlin Xue, Yaqing Jia, Zhichen Qu, Bin Luo, Jin Tang, LasHeR: A Large-scale High-diversity Benchmark for RGBT Tracking, CoRR abs/2104.13202, 2021) training set and reached new SOTAs on GTOT (C. Li, H. Cheng, S. Hu, X. Liu, J. Tang, L. Lin, Learning collaborative sparse representation for grayscale-thermal tracking, IEEE Trans. Image Process, 25 (12) (2016) 5743–5756.), RGBT234 (C. Li, X. Liang, Y. Lu, N. Zhao, and J. Tang, “Rgb-t object tracking: Benchmark and baseline,” Pattern Recognition, vol. 96, p. 106977, 2019.), and LasHeR (Chenglong Li, Wanlin Xue, Yaqing Jia, Zhichen Qu, Bin Luo, Jin Tang, LasHeR: A Large-scale High-diversity Benchmark for RGBT Tracking, CoRR abs/2104.13202, 2021) while running in real-time.     

A Bit-Error Rate Measurement and Error Analysis of Wireline Data Transmission using Current Source Model for Single Event Effect under Irradiation Environment

A high-speed wireline interfaces, e.g. LVDS (Low Voltage Differential Signaling), are widely used in the aerospace field for powerful computing in artificial satellites and aircraft [19]. This paper describes Bit Error Rate (BER) prediction methodology for wireline data transmission under irradiation environment at the design stage of data transmitter, which is useful in proactively determining if the design circuit meets the BER criteria of the target system. Using a custom-designed LVDS transmitter (TX) to enhance latch-up immunity [42], the relationship between transistor size and BER has been analyzed with focusing on Single Event Effect (SEE) as a cause of the bit error. The measurement was executed under ⁸⁴Kr¹⁷⁺ exposure of 322.0 MeV at various flux condition from 1?×?10³ to 5?×?10⁵ count/cm²/sec using cyclotron facility. For the analysis of the bit error, circuit simulation by SPICE was utilized with expressing the irradiation environment by a current source model. The current source model represents a single event strike into the circuit at drain and substrate junctions in bulk MOSFETs. For the construction of the current source model, a charge collection was simulated at the single particle strike with the creation of 3D Technology CAD (TCAD) models for the MOS devices of bulk transistor process technology. The simulation result of the charge correction was converted to a simple time-domain equation, and the single-event current source model was produced using the equation. The single-event current source was applied to SPICE simulation at bias current related circuits in the LVDS transmitter, then simulation results are carefully verified whether the output data is disturbed enough to cause bit errors on wireline data transmission. By the simulation, sensitive MOSFETs have been specified and a sum of the gate area for these MOSFETs has 29% better correlation than the normal evaluation index (sum of the drain area) by comparison to the actual BER measurement. Through the precise revelation of the sensitive area by SPICE simulation using the current model, it became possible to estimate BER under irradiation environment at the pre-fabrication design stage.

     

Digital sinusoidal PWMs for a micro-controller based single-phase inverter,Part 1: Principles of digital sinusoidal PWM generation

Nowadays, Digital Sinusoidal Pulse Width Modulation (DSPWM) is playing a major role in the generation of pure sinusoidal waveforms using micro-controller based inverters (Kawabata, Miyashita and Yamamoto 1991 Kawabata, T., Miyashita, T. and Yamamoto, Y. 1991. “Digital Control of Three-Phase PWM Inverter With LC Filter,”. IEEE Transactions on Power Electronics, 6: 62–72.  [Google Scholar]; Herrmann, Langer and Broeck 1993 Herrmann, U., Langer, H. G. and Broeck, H. V.D. 1993. “Low Cost DC to AC Converter for Photovoltaic Power Conversion in Residential Applications,”. 24th Annual IEEE Power Electronics Specialists Conference. 1993, Seattle, WA, USA.  [Google Scholar]; Ying-Yu 1995 Ying-Yu, T. “DSP-Based Fully Digital Control of a PWM DC-AC Converter for AC Voltage Regulation,”. 26th Annual IEEE Power Electronics Specialists Conference. Atlanta, GA.  [Google Scholar]; PICREF-1 1997 PICREF-1. 1997. Uninterruptible Power Supply Reference Design Vol. 2004. Microchip Technology [Google Scholar]; Shih-Liang, Meng-Yueh, Jin-Yi, Li-Chia and Ying-Y 1999 Shih-Liang, J., Meng-Yueh, C., Jin-Yi, J., Li-Chia, Y. and Ying-Yu, T. 1999. “Design and Implementation of an FPGA-Based Control IC for AC-Voltage Regulation,”. IEEE Transactions on Power Electronics, 14: 522–532.  [Google Scholar]; The Electrical Engineering Handbook 2000 The Electrical Engineering Handbook. 2000. , 2nd ed., New York: CRC Press LLC.  [Google Scholar]; Koutroulis, Chatzakis, Kalaitzakis and Voulgaris 2001 Koutroulis, E., Chatzakis, J., Kalaitzakis, K. and Voulgaris, N. C. 2001. “A Bidirectional, Sinusoidal, High-Frequency Inverter Design,”. IEE Proceedings-Electric Power Applications, 148: 315–321.  [Google Scholar]; Skvarenina 2002 Skvarenina, T. L. 2002. “The Power Electronics Handbook,”. In Industrial Electronics Series, Edited by: Irwin, J. D. New York: CRC.  [Google Scholar]; Pop, Chindris and Dulf 2004 Pop, O., Chindris, G. and Dulf, A. 2004. “Using DSP Technology for True Sine PWM Generators for Power Inverters,”. 27th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 1: 141–146.  [Google Scholar]; Zhongyi, Mingzhu and Yan 2005 Zhongyi, H., Mingzhu, L. and Yan, X. “Core Techniques of Digital Control for UPS,”. IEEE International Conference on Industrial Technology.  [Google Scholar]). The types of DSPWM that can be generated depend on the micro-controller hardware resources and are therefore limited, but provide performance benefits not possible with an analogue controller. For instance, digital controllers offer a programmable solution and therefore more flexibility, as advanced algorithms and additional features can be added to the system in software instead of hardware (Monti, Santi, Dougal, and Riva 2003 Monti, A., Santi, E., Dougal, R. A. and Riva, M. M. 2003. “Rapid Prototyping of Digital Controls for Power Electronics,”. IEEE Transactions on Power Electronics, 18: 915–923.  [Google Scholar]; Brush 2005 Brush, L. “Trends in Digital Power Management: Power Converter and System Demand Characteristics,”. Twentieth Annual IEEE Applied Power Electronics Conference and Exposition. Austin, TX [Google Scholar]). Digital controllers are also less sensitive to environmental conditions and show precise behaviour compared with their analogue counterparts (Skvarenina 2002 Skvarenina, T. L. 2002. “The Power Electronics Handbook,”. In Industrial Electronics Series, Edited by: Irwin, J. D. New York: CRC.  [Google Scholar]). This two-part article looks at the benefits and limitations of three major DSPWMs for a single-phase full-bridge inverter and investigates their performance. In Part 1, the theory of the three major DSPWMs are presented, including mathematical models and simulation results. It looks at the PWM patterns required to generate these DSPWMs and the benefits and limitations of each. To evaluate the proposed mathematical models and simulation results, a 2kVA single-phase full-bridge inverter was developed and the DSPWMs implemented. In Part 2, experimental results from the implementation of the DSPWMs on the prototype 2kVA inverter are presented, which confirms the validity of the proposed analysis in Part 1. Moreover, the performance, including efficiency and losses (switching, conduction, and transformer) of the different DSPWMs implemented on the 2kVA inverter under different loads were examined and recommendations presented.     

A High Dynamic Range Programmable CMOS Front-End Filter with a Tuning Range from 1850 to 2400 MHz

This paper presents a highly programmable front-end filter and amplifier intended to replace SAW filters and low noise amplifiers (LNA) in multi-mode direct conversion radio receivers. The filter has a 42 MHz bandwidth, is tunable from 1850 to 2400 MHz, achieves a 5.8 dB NF, –25 dBm in-band 1-dB input compression point (ICP) and 0 dBm out-of-band ICP while drawing 26 mA from a 2.5 V supply.Kâre T. Christensen received the M.Sc. and Ph.D. degrees in electrical engineering from the Technical University of Denmark in 1997 and 2002, respectively.In 1995-96 he was a visiting scholar working on switched current memory cells at the Spanish National Microelectronics Centre in Seville. In 1997 he worked on an asynchronous embedded MIPS16/MIPS32 microprocessor core for LSI Logic. In 1999-2000 he was a visiting researcher at Stanford University. During his stay he worked on fully integrated RF front-end filters in CMOS.From 1998 to 2002 he worked for Nokia Mobile Phones conducting research in the design of RF ICs for multi-band GSM terminals. He currently works for the Danish hearing aid manufacturer Oticon A/S designing micro-power RF circuits and systems in CMOS.He has lectured on several occasions at the Technical University of Denmark and other universities. He has authored or co-authored nine papers and holds three U.S. patents.Thomas H. Lee received the S.B., S.M. and Sc.D. degrees in electrical engineering, all from the Massachusetts Institute of Technology in 1983, 1985, and 1990, respectively.He joined Analog Devices in 1990 where he was primarily engaged in the design of high-speed clock recovery devices. In 1992, he joined Rambus Inc. in Mountain View, CA where he developed high-speed analog circuitry for 500 megabyte/s CMOS DRAMs.He has also contributed to the development of PLLs in the StrongARM, Alpha and AMD K6/K7/K8 microprocessors. Since 1994, he has been a Professor of Electrical Engineering at Stanford University where his research focus has been on gigahertz-speed wireline and wireless integrated circuits built in conventional silicon technologies, particularly CMOS.He has twice received the Best Paper award at the International Solid-State Circuits Conference, co-authored a Best Student Paper at ISSCC, was awarded the Best Paper prize at CICC, and is a Packard Foundation Fellowship recipient.He is an IEEE Distinguished Lecturer of both the Solid-State Circuits and Microwave Societies. He holds 35 U.S. patents and authored The Design of CMOS Radio-Frequency Integrated Circuits (now in its second edition), and Planar Microwave Engineering, both with Cambridge University Press. He is a co-author of four additional books on RF circuit design, and also cofounded Matrix Semiconductor.Erik Bruun received the M.Sc. and Ph.D. degrees in electrical engineering in 1974 and 1980, respectively, from the Technical University of Denmark. In 1980 he received the B.Com. degree from the Copenhagen Business School. In 2000 he also received the dr. techn. degree from the Technical University of Denmark.From January 1974 to September 1974 he was with Christian Rovsing A/S, working on the development of space electronics and test equipment for space electronics. From 1974 to 1980 he was with the Laboratory for Semiconductor Technology at the Technical University of Denmark, working in the fields of MNOS memory devices, IL devices, bipolar analog circuits, and custom integrated circuits. From 1980 to 1984 he was with Christian Rovsing A/S. From 1984 to 1989 he was the managing director of Danmos Microsystems ApS. Since 1989 he has been a Professor of analog electronics at the Technical University of Denmark where he has served as head of the Sector of Information Technology, Electronics, and Mathematics from 1995 to 2001. Since 2001 he has been head of ÿrstedïDTU.His current research interests are in the areas of RF integrated circuit design and integrated circuits for mobile phones.     

The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer

Computer architects have been studying the dynamically reconfigurable computer (Schaumont, Verbauwhede, Keutzer, and Sarrafzadeh, “A Quick Safari through the Reconfiguration Jungle,” in Proc. of the 38th Design Automation Conference, Las Vegas, pp. 127–177, 2001) for a number of years. New capabilities such as on-demand computing power, self-adaptiveness and self-optimization capabilities by restructuring the hardware on the fly at run-time is seen as a driving technology factor for current research initiatives such as autonomic (Kephart and Chess, Computer, 36:41–52, 2003; IBM Autonomic Computing Initiative, (http://www.research.ibm.com/autonomic/)) and organic computing (Müller-Schloer, von der Malsburg, and Würtz, Inform.-Spektrum, 27:332–336, 2004; The Organic Computing Page, (http://www.organic-computing.org)). Much research work is currently devoted to models for partial hardware module relocation (SPP1148 Reconfigurable Computing Priority Program, (http://www12.informatik.uni-erlangen.de/spprr/)) and dynamically reconfigurable hardware reconfiguration on e.g., FPGA-based platforms. However, there are many physical restrictions and technical problems limiting the scope or applicability of these approaches. This led us to the development of a new FPGA-based reconfigurable computer called the Erlangen Slot Machine. The architecture overcomes many architectural constraints of existing platforms and allows a user to partially reconfigure hardware modules arranged in so-called slots. The uniqueness of this computer stems from (a) a new slot-oriented hardware architecture, (b) a set of novel inter-module communication paradigms, and (c) concepts for dynamic and partial reconfiguration management.