内存映射文件及其在广义舒适度仿真中的应用

本文分析了win32系统下的虚拟内存系统模式及内存映射文件的工作机理,介绍了如何用windows API将文件映射至内存,利用原型页表入口技术实现了多个进程之间的数据共享。通过实验数据得出,采用内存映射文件读取高速服役列车的广义舒适度仿真中的超大数据文件,其效率远远高于传统的基于文件I/O方式的数据存取。     

基于内存映射文件的进程间数据传输

介绍了Windows操作系统的内存管理方式及Windows操作系统中进程间通信的几种方式,论述了内存映射文件的定义,以及使用内存映射文件在进程间共享内存的原理、操作和使用内存映射文件的方法和步骤。根据内存映射文件在进程间共享数据的原理,实现了多进程间数据传输共享的消息队列,并应用于工程实践中,取得了较好的效果。     

Win32中多进程间的内存共享数据通信方法

支持多任务操作是 Windows 操作系统的主要优点之一。本文针对32位 Windows 的技术特点,提出了基于共享内存的多进程间数据传输方法,并详细讨论了通过内存映射文件的内存共享实现技术。给出编程实例之后,本文对共享内存技术做了总结。     

基于内存映射文件的仿真系统进程间数据

针对某综合仿真系统进程间进行大数据量快速实时传输的需求,在分析进程间数据传输方法的基础上,采用内存映射文件技术,实现了进程间大数据量的实时传输。结果表明,基于内存映射文件技术的进程间大数据量的快速实时传输,在某综合仿真系统中工作可靠、稳定。     

Win32中多进程间的内存共享数据通信方法

支持多任务操作是Windows操作系统的主要优点之一。本文针对32位Windows的技术特点,提出了基于共享内存的多进程间数据传输方法,并详细讨论了通过内存映射文件的内存共享实现技术。给出编程实例之后,本文对共享内存技术做了总结。     

内存映射技术在大数据存储应用中的研究

针对无线网络技术研究中对大数据实时存储和国产化需求,在Qt平台下利用内存映射技术,设计实现了一种针对大数据的实时存储方案,可实现对无线网络中频采样数据和解调解码数据的实时存储。并通过设计有效的索引机制,极大的提高了后续离线数据分析时的数据搜索效率。最后通过测试代码对该内存映射文件存储技术进行了实验验证。     

使用Win32优化内存和文件I/O管理

分析了传统I/O管理中存在的一些问题和Win32部件对象的特性,详细介绍了使用内存映射文件的全过程。为了使用的方便,设计了一个C++来包装使用内存映射文件的API函数,并用于实际的编程。具有一定的实用价值。     

使用Wind32优化内存和文件I／O管理

分析了传统I/O管理中存在的一些问题和Win32部件对象的特性，详细介绍了使用内存映射文件的全过程。为了使用的方便。设计了一个C^ 来包装使用内存映射文件的API函数。并用于实际的编程。具有一定的实用价值。     

WIN32下利用内存映射文件实现进程间通信

本文介绍了VC＋＋编译环境下利用内存映射文件实现WIN32进程间的通信，并通过实例介绍实现过程。     

基于WINDOWS平台下银行卡系统流水文件的自动识别与分析

在银行卡交易的清分及结算环节,流水文件作为卡组织与其成员金融机构结算、对账的重要媒介,为应对卡组织对账文件种类多、存储信息量大、字段结构复杂以及文件字节过大用户无法人工阅读的特点,通过参数化灵活设置、内存映射及动态定位等技术方式,实现可基于WINDOWS平台的文件处理能力.     

Anticipatory I/O Management for Clustered Flash Translation Layer in NAND Flash Memory

Recently, NAND flash memory has emerged as a next generation storage device because it has several advantages, such as low power consumption, shock resistance, and so on. However, it is necessary to use a flash translation layer (FTL) to intermediate between NAND flash memory and conventional file systems because of the unique hardware characteristics of flash memory. This paper proposes a new clustered FTL (CFTL) that uses clustered hash tables and a two‐level software cache technique. The CFTL can anticipate consecutive addresses from the host because the clustered hash table uses the locality of reference in a large address space. It also adaptively switches logical addresses to physical addresses in the flash memory by using block mapping, page mapping, and a two‐level software cache technique. Furthermore, anticipatory I/O management using continuity counters and a prefetch scheme enables fast address translation. Experimental results show that the proposed address translation mechanism for CFTL provides better performance in address translation and memory space usage than the well‐known NAND FTL (NFTL) and adaptive FTL (AFTL).     

Random access protocols for high-speed interprocessor communicationbased on an optical passive star topology

A multiple-instruction multiple-data (MIMD) distributed memory parallel computer system environment is considered. Media access control protocols that maintain good performance with high capacity optical channels are investigated. Three examples of star-coupled structures are introduced, one of which exhibits optical self-routing. Self-routing single-step optically interconnected communication structures can be designed through the incorporation of agile laser diode sources and wavelength tunable optical filters in a wavelength-division multiple-access environment. Intermediary latencies typical of MIMD distributed memory systems are eliminated. The degree and diameter of the resulting structures are dramatically reduced, and the complexity of the communication subsystem is reduced since intermediate buffering and routing of packets are eliminated     

5G自身智能化及赋能智能产业之路

2019年是5G商用的元年,5G深入各个垂直行业的应用同人工智能(AI)的典型应用高度重叠。5G网络自身的智能化是5G+AI赋能各行各业应用的基础,同时也是提升网络效率,降低运营运维成本的关键。5G+AI赋能产业的场景和规模正在加速发展,这些不断拓展的新业务需求也对5G网络和AI技术提出了新的挑战。本文阐述了5G网络自身智能化及5G+AI赋能产业所取得的进展,以及面临的核心技术问题,呼吁产学研突破现有的研发共享合作模式,加速解决核心技术挑战。     

基于AT89S52和K9F6408UOA的语音数字系统设计

在研究传统语音录放电路的基础上,提出了一种基于AT89S52的音频信号采集、存储与处理系统。该系统以单片机AT89S52为控制器,采用键盘和LCD作为人机界面,ADC0809采集音频信号,扩展8MB闪速存储器K9F6408UOA作为数字化音频信号的存储器,通过软件滤波滤除噪音;采用PWM产生声音的原理,使存储在Flash中的音频数据控制PWM每个波形的占空比,通过低通滤波器将声音从PWM的脉冲中分离,并驱动扬声器。实验表明：8kHz采样频率和8位采样位数可获得清晰的语音以及较好的音乐声,语音存储时间达15min。     

RT级综合中存储器工艺映射算法的研究

提出了一种寄存器传输级存储器工艺映射（RTLM）算法,该方法用目标存储模块来综合一个源存储器,它支持使用高层次综合和设计再利用的现代VLSI设计方法学。存储器的映射被定义为三个子问题,即端口映射、字长映射和字数映射。最后,把这三个子问题综合起来形成完整的算法。实验结果表明,RTLM在高层次综合中对存储器设计的再利用是一种有效的方法。     

Synthesis of hardware models in C with pointers and complex datastructures

One of the greatest challenges in a C/C++-based design methodology is efficiently mapping C/C++ models into hardware. Many networking and multimedia applications implemented in hardware or mixed hardware/software systems now use complex data structures stored in multiple memories, so many C/C++ features that were originally designed for software applications are now making their way into hardware. Such features include dynamic memory allocation and pointers for managing data. We present a solution for efficiently mapping arbitrary C code with pointers and malloc/free into hardware. Our solution, which fits current memory management methodologies, instantiates an application-specific hardware memory allocator coupled with a memory architecture. Our work also supports the resolution of pointers without restriction on the data structures. We present an implementation based on the SUIF framework along with case studies such as the realization of a video filter and an ATM segmentation engine     

小型化模测终端的关键技术及测试验证

本文提出的小型化模测终端可以实现降低模测成本、提升模测效率两大目标。文中首先介绍了小型化模测终端的研发背景,然后,论证了其中涉及的两大关键技术;接着,说明了小型化模测终端的应用场景;最后,AICL项目组还基于定制样机开展了实验室及外场测试验证,通过实测证明了小型化模测终端的可行性。     

基于Mini700记录器的1553B数据处理软件设计

随着新型机载飞行数据记录器Mini700在飞行试验中的广泛应用,总线数据的记录格式发生变化,数据处理通用软件对1553B数据处理不仅流程复杂而且效率低下。为解决这一问题,针对Mini700记录器的数据格式进行了分析,重点研究了其数据绝对时间的计算及数据格式的解析算法,设计开发了基于Mini700记录格式的1553B总线数据处理软件。测试结果表明,新软件不仅改进简化了当前的数据处理流程,而且大幅提高了数据处理效率。     

基于内存映射的进程问通信实现跨平台软件互联互通

在某型号改研制过程中,软件运行于WindowsXP操作系统中,需要将VC平台下编写的软件无缝嵌入delphi平台下编写的软件中,实现两个单独运行进程的互联互通。以内存文件映射技术为基础,提出了将共享内存区分为读数据区和写数据区,并利用特定字节设定允许读写标志。在读写数据时,分剐在两个进程中采用间隔相等的轮询定时器,实现了在两个进程中数据的双向通信。后续试验表明,该方法可靠实用,软件改动量小,极大地促进了工厂的型号研制。     

A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck

Memory latency has always been a major issue in embedded systems that execute memory-intensive applications. This is even more true as the gap between processor and memory speed continues to grow. Hardware and software prefetching have been shown to be effective in tolerating the large memory latencies inherit in large off-chip memories; however, both types of prefetching have their shortcomings. Hardware schemes are more complex and require extra circuitry to compute data access strides, while software schemes generate prefetch instructions, which if not computed carefully may hamper performance. On the other hand, some applications domains (such as multimedia) have a uniform and known a priori memory access pattern, that if exploited, could yield significant application performance improvement. With this characteristic in mind, we present our findings on hiding memory latency using the direct memory access (DMA) mode, which is present in all modern systems, combined with a software prefetch mechanism, and a customized on-chip memory hierarchy mapping. Compared to previous approaches, we are able to estimate the performance and power metrics, without actually implementing the embedded system. Experimental results on nine well known multimedia and imaging applications prove the efficiency of our technique. Finally, we verify the performance estimations by implementing and simulating the algorithms on the TI C6201 processor.