改善不同环境温度下SiGe HBT热稳定性的技术

提出了发射极非均匀指间距技术以增强多发射极指SiGe HBT在不同环境温度下的热稳定性。通过建立热电反馈模型对采用发射极非均匀指间距技术的SiGe HBT进行热稳定性分析,得到多发射极指上的温度分布。结果表明,与传统的均匀发射极指间距SiGe HBT相比,在相同的环境温度及耗散功率下,采用发射极非均匀指间距技术的SiGe HBT,其最高结温明显降低,热阻显著减小,温度分布更加均匀,有效地提高了多发射极指功率SiGe HBT在不同环境温度下的热稳定性。     

Temperature dependence of hot-carrier-induced degradation in 0.1μm SOI nMOSFETs with thin oxide

This letter investigates hot-carrier-induced degradation on 0.1 μm partially depleted silicon-on-insulator (SOI) nMOSFETs at various ambient temperatures. The thermal impact on device degradation was investigated with respect to body-contact nMOSFETs (BC-SOI) and floating-body SOI nMOSFETs (FB-SOI). Experimental results show that hot-carrier-induced degradation on drive capacity of FB-SOI devices exhibits inverse temperature dependence compared to that of BC-SOI devices. This is attributed to the floating-body effect (FBE) and parasitic bipolar transistor (PBT) effect     

Simulation of Life Testing Procedures for Estimating Long-Term Degradation and Lifetime of AlGaN/GaN HEMTs

Finite element 3-D thermal simulations of long-term degradation in AlGaN/GaN HEMTs for high-power applications are reported on, in which temperature evolves over time as the local degradation rate varies within the modeled device based on the local temperature of the degrading region (i.e., the channel). Specifically, hotter regions within a device are modeled as degrading faster due to a thermal component to the degradation rate equation. This allows self-consistent simulation of life testing, commonly used to estimate long-term reliability by extrapolating failure times seen at elevated channel temperatures to a lower "use" temperature. We find that it is necessary to consider the entire distribution of temperatures within the device instead of at one characteristic location to get the most accurate estimates for long-term device life. The effect of device geometry, assumed degradation mode, incorrect thermal resistance data, and dissipated power level on this lifetime estimation error is investigated. It is found that the error in the extrapolated failure time is greatly increased when both the thermal resistance is in error and the dissipated power of the life test does not match the expected power during operation, compared to when only one of these is off.     

Temperature dependence of hot-electron degradation in bipolartransistors

Degradation of the base current and current gain observed in bipolar transistors that were electrically stressed at-75, 175, and 240°C for 1000 h with a constant reverse-bias voltage applied to the emitter-base junctions is discussed. The rate of degradation was found to be temperature-dependent with a larger degradation occurring at the lower temperature. This temperature dependency is studied using an electron energy simulation technique and experimental data on degradation and postdegradation annealing. From the electron energy simulations, the number of hot electrons above a damage threshold energy was seen to increase with increasing ambient temperature at a constant reverse-bias voltage. This increase with temperature occurred because higher stress currents dominated over a reduction in the electron mean free path between collisions at higher temperatures. However, an actual degradation rate reduction at higher temperatures occurs because of simultaneous annealing of the states produced by hot electrons. A model that describes the temperature dependence of degradation and postdegradation annealing is described     

Insight into the charge transport and degradation mechanisms in organic transistors operating at elevated temperatures in air

Operational stability of organic devices at above-room-temperatures in ambient environment is of imminent practical importance. In this report, we have investigated the charge transport and degradation mechanisms in pentacene based organic field effect transistors (OFETs) operating in the temperatures ranging from 25 °C to 150 °C under ambient conditions. The thin film characterizations techniques (X-ray photoelectron spectroscopy, X-ray diffraction and atomic force microscopy) were used to establish the structural and chemical stability of pentacene thin films at temperatures up to 150 °C in ambient conditions. The electrical behavior of OFETs varies differently in different temperature bracket. Mobility, at temperatures below 110 °C, is found to be thermally activated in presence of traps and temperature independent in absence of traps. At temperatures above 110 °C mobility degrades due to polymorphism in pentacene or interfacial properties. The degradation of mobility is compensated with the decrease in threshold voltage at high temperatures and OFETs are operational at temperatures as high as 190 °C. 70 °C has been identified as the optimum temperature of operation for our OFETs where both device behavior and material properties are stable enough to ensure sustainable performance.     

Effects of annealing on the hydrogen concentration and the performance of InGaP/InGaAsN/GaAs heterojunction bipolar transistors

The effects of rapid thermal annealing (RTA) on InGaP/InGaAsN heterojunction bipolar transistors (HBTs) with a carbon-doped base have been studied. The hydrogen and nitrogen concentrations in the base, as well as the direct current (DC) and radio frequency (RF) device performance, were studied as a function of the annealing temperature. A 30-sec anneal at 650°C and 700°C under N₂ ambient effectively eliminates hydrogen from the base. As the annealing temperature is increased, the base sheet resistance decreases, and the corresponding maximum frequency of oscillation increases. For all annealing temperatures studied, we found degradation in the DC gain, presumably caused by the increase of nitrogen concentration in the base region.     

Investigation of smart power DMOS devices under repetitive stress conditions using transient thermal mapping and numerical simulation

Temperature distribution in diced and packaged DMOS devices subjected to repetitive stress is analyzed using transient interferometric mapping (TIM) technique combined with measurements on diode built-in temperature sensors. The effect of DMOS device position on dice, duty cycle and chip ambient temperature on thermal distribution is studied. The TIM experiments and transient temperature measurements are in good agreement with numerical 3D thermal simulations. Failure analysis data after long term pulse stress testing indicate electromigration degradation of the top metal.     

Investigation of the thermal performance of micro-whisker structured silicon heat spreaders for power devices

The driving forces of developments in power electronics are the continuing miniaturization and enhancement of power densities. New packaging concepts are required allowing the dissipation of a power loss density of up to several hundred W/cm² at operation temperatures as low as possible. A promising attempt to decrease the thermal resistance to the ambient is the development of silicon substrates structured with microwhiskers perpendicular to its surface. An industrial application of this new heat spreader technology in power electronic modules makes necessary the specification of the substrate properties. In this work, a new method for determination of thermal qualities based on laser heating of the heat spreader, surface temperature measurement by thermovision, and dynamic reverse modeling is described. For numerical determination of the thermal characteristics, the measured data are evaluated with the help of a thermal model of the heat spreaders under various boundary conditions. The respective temperature distributions are calculated with a new simulation tool using an alternating-direction implicit algorithm (ADI-method). Results obtained from heat spreaders with microwhisker treatment are compared with those from reference samples with a polished surface. Based on these results a view on future applications for power electronics assemblies are derived.     

Investigation of the thermal properties of thin solid materials at different temperature levels using a set of microresistors

The measurement of thermal properties of solid materials at different temperatures above ambient is investigated using a set of microresistors. Samples consisted of suspended films with sets of long, parallel resistive wires deposited on their surfaces. One resistive wire was heated by an alternating current. Surface temperature changes in DC and AC regimes were then detected by measuring the change in electrical resistance of the other wires deposited on the surface. The length of wires was chosen so that they may be assumed isothermal and such that heat diffusion acts perpendicularly to their axes. By measuring the dependence of the surface alternating temperature oscillation on the modulation frequency f and on the separation between the heating wire and the probing wires, the thermal diffusivity of the sample was determined. Through adjustment of the alternating current amplitude in the source wire, the temperature at which the thermal diffusivity of the sample was evaluated was finely controlled. For the validation of the method, pure silicon samples were first studied. An experimental bench was set up and resistive source and probes were experimentally characterized. Results obtained from ambient temperature to 500 K for pure silicon are in accordance with reference data found in the scientific literature.     

Reliability of high radiance InGaAsP/InP LED́s operating in the 1.2-1.3 µm wavelength

The reliability of high radiance InGaAsP/InP DH LED's operating in the1.2-1.3 mum wavelength and the defect structures observed in this quaternary alloy have been presented. Threading dislocations and misfit dislocations do not act as strong nonradiative recombination centers, in contrast with the case in GaAs or GaAlAs optical devices. Dark-spot defects (DSD's) were sometimes generated in the emitting area during aging at elevated temperatures. These defects were analyzed microscopically using a transmission electron microscope and were identified as precipitates. To investigate the homogeneous degradation, accelerated aging at the ambient temperatures of 20, 60, 120, 170, 200, and 230°C has been carried out for over 15 000 h at the current density of 8 kA/cm²using LED's without dark structures. The degradation rates were statistically calculated by assuming the normal distribution. The mean values of degradation rates and the values of standard deviation were determined at the temperatures above 170°C. The activation energy of homogeneous degradation was determined to be 1.0 eV and the extrapolated half-life in excess of 10⁹h was estimated at the ambient temperature of 60°C.     

Optimization and validation of thermal management for a RF front-end SiP based on rigid-flex substrate

This paper mainly presents a new 3D stacking RF System-in-Package (SiP) structure based on rigid-flex substrate for a micro base station, with 33 active chips integrated in a small package of 5cm × 5.5cm × 0.8cm. Total power consumption adds up to 20.1 Watt. To address thermal management and testability difficulties of this RF SiP, a thermal test package is designed with the same package structure and assembly flow, only replacing active chips with thermal test dies (TTDs). Optimization and validation of thermal management for the thermal test package is conducted. Effects of the structure, chip power distribution, and ambient temperature aspects on the thermal performance are studied. Thermal vias designed in the organic substrate provide a direct heat dissipation path from TTDs to the top heatsink, which minimizes junction temperature gap of the top substrate from 31.2 °C to 5.3 °C, and enables junction temperatures of all the chips on the face to face structure to be well below 82 °C. Chip power distribution optimization indicates placing high power RF parts on the top rigid substrate is a reasonable choice. The ambient temperature optimizes with forced air convection and cold-plate cooling method, both of which are effective methods to improve thermal performances especially for this micro base station application where environment temperature may reach more than 75 °C. The thermal management validation is performed with a thermal test vehicle. Junction temperatures are compared between finite-volume-method (FVM) simulation and thermal measurement under the natural convection condition. The accordance of simulation and measurement validates this thermal test method. Junction temperatures of typical RF chips are all below 80 °C, which shows the effectiveness of thermal management of this RF SiP.     

星敏感器组件的热设计

根据高分辨率卫星上星敏感器的特点和任务需求,通过仿真分析与试验相结合的方法对星敏感器组件进行热设计.首先,根据热变形分析确定星敏感器支架的热控指标为183 ℃.其次,根据轨道参数及结构布局获得3只星敏感器及其安装支架的外热流,同时考虑内热源分布及多层隔热材料表面参数的退化等因素,选用被动热控和主动热控相结合的热控模式.然后,通过仿真分析,得到星敏感器支架在低温工况和高温工况下的温度范围为17.0~19.1 ℃.最后,通过热平衡试验及在轨温度测试验证热设计,星敏支架在各试验工况下的温度范围为17.3~18.7 ℃,与分析结果相符;在轨测试星敏支架的温度范围为16.0~19.0 ℃,满足热控指标要求183 ℃.热设计合理有效,满足任务需求.     

Degradation behavior of 600 V–200 A IGBT modules under power cycling and high temperature environment conditions

One challenge for automotive hybrid traction application is the use of high power IGBT modules that can withstand high ambient temperatures, from 90 °C to 120 °C, for reliability purpose. The paper presents ageing tests of 600 V–200 A IGBT modules subjected to power cycling with 60 °C junction temperature swings at 90 °C ambient temperature. Failure modes are described and obtained results on the module characteristics are detailed. Especially, physical degradations are described not only at the package level, like solder attach delaminations, but also at the chip level, with a shift on electrical characteristics such as threshold voltage. Finally, numerical investigations are performed in order to assess the thermal and thermo-mechanical constraints on silicon dies during power cycling and also to estimate the effect of ambient temperature on the mechanical stresses.     

Thermal stress effects on Dye-Sensitized Solar Cells (DSSCs)

Since the DSSCs gain heat during exposure to sunlight increasing its own temperature, we have studied the role of temperature on the degradation of DSSCs. We have performed pure thermal stresses keeping the devices at a constant temperature inside a climatic chamber and monitoring the electrical parameters during stress. We found that temperature alone strongly impacts on the DSSC performances, enhancing the degradation of the sensitizer and then reducing the photo-generated current.     

Analysis of Phase Characteristics as a Function of Ambient Temperature of IMPATT Amplifiers

Experimental data on phase characteristics as a function of ambient temperatures for GaAs IMPATT amplifiers are presented. An evaluation is given to show the impact of ambient temperature on an amplifier design used in phased-array RADARs.     

Direct Low‐Temperature Integration of Nanocrystalline Diamond with GaN Substrates for Improved Thermal Management of High‐Power Electronics

A novel approach for the direct synthetic diamond–GaN integration via deposition of the high‐quality nanocrystalline diamond films directly on GaN substrates at temperatures as low as 450–500 °C is reported. The low deposition temperature allows one to avoid degradation of the GaN quality, which is essential for electronic applications The specially tuned growth conditions resulted in the large crystalline diamond grain size of 100–200 nm without coarsening. Using the transient “hot disk” measurements it is demonstrated that the effective thermal conductivity of the resulting diamond/GaN composite wafers is higher than that of the original GaN substrates at elevated temperatures. The thermal crossover point is reached at ≈95–125 °C depending on the thickness of the deposited films. The developed deposition technique and obtained thermal characterization data can lead to a new method of thermal management of the high power GaN electronic and optoelectronic devices.     

Thermal performance modeling of loop heat pipes with flat evaporator for electronics cooling

This work deals with modeling of the thermal performance of a copper-water loop heat pipe (LHP) with a flat evaporator operating in steady state operation. The model is based on steady-state energy and momentum balance equations for each LHP component. Modeling the heat transfer in the evaporator was particularly considered, and the evaporation heat transfer coefficient is determined from a dimensionless correlation which is developed on the basis of experimental data from literature. The validation of this model consists in comparing the experimental results and those obtained by the model for different cooling temperatures. Finally, a parametric study is presented to show the effects of different key parameters such as the radii and the lengths of the liquid and vapor lines, the length of the condenser, the heat sink temperature and heat transfer coefficient as well as the ambient temperature and the heat losses to the ambient.     

Reliability aspects of thermal micro-structures implemented on industrial 0.8 μm CMOS chips

This paper discusses the reliability characterization of thermal micro-structures implemented on industrial 0.8 μm CMOS chips. Various degradation and failure mechanisms are identified and evaluated under high temperature operation. At high temperatures the mechanisms are many and varied, and co-incidental thermally-induced mechanical defects are found in both the poly-Si heater and the poly-Si temperature sensor, along with temperature- and current-enhanced interlayer diffusion degradation of the heater contacts. Local reduction in the device thermal capacity by using silicon micro-machining can be expected to hold the promise of a number of significant advantages, especially for limiting current stressing of the contact regions. The results can be used to optimize the design of thermally based micro-sensors on CMOS chips, such as CMOS compatible chemoresistive gas sensors.     

Influence of TiSi2 formation temperature on film thermal stability

This work is addressed to investigate thermal stability of a thin TiSi₂ film, that is its ability to resist degradation due to heat treatments at high temperatures. The study was carried out as a function of the formation RT treatment (675–750°C) at the end of a common process flow. Sheet resistance measurements were employed in order to evaluate this degradation. Electrical measures were performed on large and narrow poly-Si lines, on Van Der Pauw structures and on doped mono-Si substrates. An increase in sheet resistance value of an order of magnitude for silicide formed at temperatures below 700°C with respect to the one formed at temperatures above 700°C was found, particularly on poly-Si lines. The effect is detectable independently of the structure: it was observed also on 0.75-μm wide poly-Si lines, increasing when line width decreases. Different morphological analyses were carried out for investigating the influence of the formation temperature. We explain the increase of the final sheet resistance decreasing the formation temperature as a lower thermal stability of the TiSi₂ film, leading to a thermal grooving of the silicide grains.