Analog behavioral modeling by multi-companding and wavelet collocation method

In this paper, we develop a wavelet collocation method with multi-companding for behavioral modeling of analog circuits. In the multi-companding procedure, the nonlinear companding algorithm is developed to control the error distribution continuously, while the adaptive scheme is employed to reduce the number of used wavelets. Consequently, the proposed multi-companding algorithm can not only modify the modeling error distribution continuously but also decrease the number of basis functions efficiently. Moreover, the companding function generation is automatic and can be applied for the behavioral modeling of any analog circuits. Jun Tao received the B.S degree in electrical engineering from Fudan University, China, in 2002. Now she is currently working toward the Ph.D. degree in micro-electronic engineering at the Fudan University. Her research interest includes analog behavioral modeling, analog circuit simulation and DFM. Xuan Zeng (M97) received the B.Sc. and Ph.D. degrees in electrical engineering from Fudan University, Shanghai, China, in 1991 and 1997, respectively. She joined the Electrical Engineering Department, Fudan University in 1997 and became a full professor in Microelectronics Department in 2001. Now she serves as the Vice Director of ASIC & System State key Lab. and the Associate Head of Microelectronics Department Fudan University. She was a visiting professor in the Electrical Engineering Department, Texas A&M University, USA and Microelectronics Department of TU Delft, Netherland in 2002 and 2003 respectively. Her research interests include DFM, analog and mixed signal design automation (behavioral modeling, circuit simulation and analog layout generation), high speed interconnect analysis and design and ASIC design. Dr. Zeng received the Cross-Century Outstanding Scholar Award from the Ministry of Education of China in 2002. She was selected into “IT Top 10” in Shanghai China in 2003. She served in the technical program committee of IEEE/ACM ASP-DAC in 2000 and 2005. Dian Zhou received the B.S degree in physics and M.S degree in electrical engineering from Fudan University, China, in 1982 and 1985, respectively, and the Ph.D. degree in electrical and computer engineering from the University of Illinois in 1990. He joined the University of North Carolina at Charlotte as an assistant professor in 1990, where he became an associate professor in 1995. He joined the University of Texas at Dallas as a full professor in 1999, and joined Fudan university as a Changjiang Professor in 2003 (on-leave from the University of Texas at Dallas). Currently, he serves as the dean of Microelectronics School, director of National Key Lab. on ASICs and Systems, and director of Miro-nano-electronics Innovation Platform at Fudan University. His research interests include: High-speed VLSI systems, CAD tools, mixed-signal ICs, and algorithms. Charles Chiang received his Bachelor degrees from the Department of Political Science, Tunghai University at Taichung, Taiwan in 1980, and Department of Computer Science, New Mexico State University, Las Cruces, New Mexico in 1986. Then he had his Masters and Ph.D. degree from the Department of Electrical Engineering and Computer Science, Northwestern University, Illinois in 1988 and 1991, respectively. After working at IBM and EDA companies for 10 years, he joined the Advanced Technology Group at Synopsys, Inc. in 2001. His research interests include routing, placement, floorplan, and signal integrity. His main research focus is now on design for manufacturability (DFM). Dr. Chiang has been a Senior Member of IEEE since 1998. He received the Superior Design Recognition award and the ADAL award from IBM Rochester in 1993 and 1994, respectively. He is one of the top 15 winners with new patent filing in 2005 and 2006 in Synopsys. He has served on the technical committee of ICCAD from 2004 to 2006, on that of Field Programming Logic (FPL) from 2002 to 2003, as well as on the committee of ASP-DAC in 2007. He has published more than 40 technical papers and filed 10 US patents.     

New layout strategies with improved matching performance

In this paper, the systematic mismatch error in integrated circuits due to gradient effects is modeled and analyzed. Three layout strategies with improved matching performance are reviewed and summarized. The hexagonal tessellation pattern can cancel quadratic gradient errors with only 3 units for each device and has high area-efficiency when extended. Both the Nth-order circular symmetry patterns and Nth-order central symmetry patterns can cancel up to Nth-order gradient effects between two devices using 2^N unit cells for each one. Among these three techniques, the central symmetry patterns have the best-reported matching performance for Manhattan structures; the circular-symmetry patterns have the best theoretical matching performance; and the hexagonal tessellation pattern has high density and high structural stability. The Nth-order central symmetry technique is compatible to all IC fabrication processes requiring no special design rules. Simulation results of these proposed techniques show better matching characteristics than other existing layout techniques under nonlinear gradient effects. Specifically, two pairs of P-poly resistors using 2nd and 3rd-order central symmetry patterns were fabricated and tested. Less than 0.04% mismatch and less than 0.002% mismatch were achieved for the 2nd and the 3rd-order structures, respectively. Chengming He was born in YiWu, China in 1976. He received his B.S. in 1999 in Electronic Engineering department and his M.S. degree in the institute of Microelectronics in 2001 at Tsinghua University, Beijing. He started to work toward his PhD in Iowa State University since August 2001. Since June 2004 he started to work as a design engineer in Silicon Laboratories, Inc., Austin, TX. He studied and designed LNA, band-pass filter and on-chip power management blocks as well as matching-enhanced layout patterns. He is interested in designing high gain low voltage amplifier, high speed power-efficient ADC and high speed high linear DAC as well as other mixed-signal circuits. He is also interested in the application of nonlinear system dynamical theory in mixed-signal design and yield-enhancement by improving layout matching. He has published more than 10 technical papers. He was a student member of IEEE from 01--04 and now is a member. He is a member of Tau Beta Pi. Xin Dai was born in Shanghai, China on March 11, 1981. She received the B.Eng. in 2003 from Shanghai Jiao Tong University, Shanghai, China. She is currently a graduate student in Department of Electrical and Computer Engineering at Iowa State University, Ames, IA. Her research has been connected to data converter design and calibrations, layout techniques and build-in-self-test. Xin Dai is now taking a summer-intern in Broadcom Corp., CA. Hanqing Xing was born in Dalian, China, in 1978. He received the B.S. and M.S. degrees with honors in Electronic Engineering from Tsinghua University, Beijing, China, in 2000 and 2003, respectively. He is currently a PhD student at Iowa State University working in analog and mixed signal design group. His research interests include analog, mixed-signal, and data-conversion integrated circuits design and test. Degang Chen received his B.S. degree in 1984 in Instrumentation and Automation from Tsinghua University, Beijing, China and his M.S. and Ph.D. degrees in 1988 and 1992, respectively, both in Electrical and Computer Engineering, from the University of California, Santa Barbara. From 1984 to 1986, he was with the Beijing Institute of Control Engineering, a space industry R/D institute. From March 1992 to August 1992, he was the John R. Pierce Instructor of Electrical Engineering at California Institute of Technology. After that, he joined Iowa State University where he is currently an Associate Professor. He was with the Boeing Company in summer of 1999 and was with Dallas Semiconductor-Maxim in summer of 2001. His research experience include particulate contamination in microelectronic processing systems, vacuum robotics in microelectronics, adaptive and nonlinear control of electromechanical systems, and dynamics and control of atomic force microscopes. His current teaching and research interests are in the area of analog and mixed-signal VLSI integrated circuit design and testing. In particular, he is interested in low-cost high-accuracy testing and built-in-self-test of analog and mixed-signal and RF circuits, and in self-calibration and adaptive reconfiguration/repair strategies for performance and yield enhancement. Dr. Chen is the recipient of the Best Paper Award at the 1990 IEEE Conference on Decision and Control and the Best Transaction Paper Award from the ASME Journal of Dynamic Systems, Measurement, and Control in 1995. He was selected an A.D. Welliver Faculty Fellow with the Boeing Company in 1999.     

Characteristic Investigation of New Pathological Elements

A characteristic investigation of the new pathological elements (i.e voltage mirror and current mirror) has been presented. Many nullor-mirror equivalences are explored. The circuit cascadability is discussed with nullor and mirror concepts. Also, the conventional inverse network transformation has been extended for applying to the circuits with current mirror output. To demonstrate the use of presented properties, practical examples have been given. The derived circuits have been verified with HSPICE simulation and the simulation results confirm with our theoretical prediction.Hung-Yu Wang was born in Kaohsiung, Taiwan, Republic of China, on January 4, 1969. He received the Ph.D. degree in optical sciences from National Central University, Chung-Li, Taiwan in 2002.Since 1993 he has worked on promoting the prototyping IC implementation of academic researches, and propelling the collaboration of the academia and industries in Chip Implementation Center (CIC), National Science Council of the Republic of China. In 2003 he became a researcher and the deputy director in Division of Chip Implementation Service of CIC. He is currently working on South Region Office of National Chip Implementation Center, National Applied Research Laboratories as a researcher and the department manager. His research interests are in current-mode circuits design, analog IC design and analog IP design.Ching-Ting Lee was born in Taoyuan, Taiwan, R.O.C., on November 1, 1949. He received his B.S. and M.S. in Electrical Engineering Department of the National Cheng-Kung University, Taiwan, in 1972 and 1974, respectively. He received Ph.D. degree in Electrical Engineering Department from the Carnegie-Mellon University, Pittsburgh, PA, in 1982.He worked on Chung Shan Institute of Science and Technology, before he joined the Institute of Optical Sciences, National Central University, Chung-Li, Taiwan, as a Professor in 1990. He works on National Cheng-Kung University as the dean of Electrical Engineering and Computer Science and the professor or the Institute of Microelectronics, Department of Electrical Engineering in 2003. His current research interests include theory, design, and application of guided-wave structures and devices for integrated optics and waveguide lasers. His research activities have also involved in the research concerning semiconductor lasers, photodetectors and high-speed electronic devices, and their associated integration for electrooptical integrated circuits. He received the outstanding Research Professor Fellowship from the National Science Council (NSC), R.O.C. in 2000 and 2002. He also received the Optical Engineering Medal from Optical Engineering Society and Distinguish Electrical Engineering professor award from Chinese Institute of Electrical Engineering Society in 2003.Chun-Yueh Huang was born in Taichung, Taiwan, Republic of China, on March 24, 1967. He received the B.S. degree in industrial education from National Chang Hwa Normal University, Chang Hwa, Taiwan in 1991, M.S. and Ph.D. degrees both in electrical engineering from the National Cheng Kung University, Tainan, Taiwan in 1993 and 1997, respectively. Since 1999 he has been with the Kan Shan University of Technology, where he is currently Associate Professor and Chairman of Department of Electronic Engineering. His biography is included in the 7th Edition (2003–2004) of Who’s Who in Science and Engineering.His current researches include current-mode circuits design, VLSI design, analog IC design and analog IP design.     

A Software-Hardware Co-Implementation of MPEG-4 Advanced Video Coding (AVC) Decoder with Block Level Pipelining

We present a baseline MPEG-4 Advanced Video Coding (AVC) decoder based on the methodology of joint optimization of software and hardware. The software is first optimized with algorithm improvements for frame buffer management, boundary padding, content-aware inverse transform and context-based entropy decoding. The overall decoding throughput is further enhanced by pipelining the software and the dedicated hardware at macroblock level. The decoder is partitioned into the software and hardware modules according to the target frame rate and complexity profiles. The hardware acceleration modules include motion compensation, inverse transform and loop filtering. By comparing the optimized decoder with the committee reference decoder of Joint Video Team (JVT), the experimental results show improvement on the decoding throughput by 7 to 8 times. On an ARM966 board, the optimized software without hardware acceleration can achieve a decoding rate up to 5.9 frames per second (fps) for QCIF video source. The overall throughput is improved by another 27% to 7.4 fps on the average and up to 11.5 fps for slow motion video sequences. Finally, we provide a theoretical analysis of the ideal performance of the proposed decoder.Shih-Hao Wang was born in Tainan, Taiwan, R.O.C. in 1977. He received the M.S. degree in Electrical and Control Engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2001, where he is currently working toward the Ph.D. degree in the Institute of Electronics.His research interests are video compression and VLSI implementation.Wen-Hsiao Peng was born in Hsin-Chu, Taiwan, Republic of China, in 1975. He received the B.S. and the M.S. degrees in Electrics Engineering from National Chiao-Tung University, Hsin-Chu, Taiwan, in 1997 and 1999respectively. During 2000–2001, he was an intern in Intel Microprocessor Research Lab, U.S.A. In 2002, he joined the Institute of Electronics of National Chiao-Tung University, where he is currently a Ph.D candidate. His major research interests include scalable video coding, video codec optimization and platform based architecture design for video compression applications. Since 2000, he has been working with video coding development and implementation. He has actively contributed to the development of MPEG-4 Fine Granularity Scalability (FGS) and MPEG-21 Scalable Video Coding (Now, MPEG-4 Part 10 AVC Amd.1).Yu-Wen Hereceived his Ph.D. degree in computer application from Tsinghua University in 2002. He was a lecture of the Department of Computer Science and Technology from 2002 to 2003 in Tsinghua University. In 2004, he joined Internet Media group of Microsoft Research Asia.His research interests include video coding, transmission and embedded multimedia application systems.Guan-yi Lin was born in Kaohsiung, Taiwan in 1981. He received the B.S. degree in Electronics Engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2003, where he is currently working toward the M.S. degree in the Institute of Electronics.His research interests are video compression and communication systems design.Cheng-Yi Lin was born in Tainan, Taiwan in 1981. He received the B.S. degree in Electronics Engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2003, where he is currently working toward the M.S. degree in the Institute of Electronics.His research interests are on-chip communication and testing.Shih-Chien Chang was born in Taichung, Taiwan in 1981. He received the B.S. degree in Electronics Engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2003, where he is currently working toward the M.S. degree in the Institute of Electronics.His research interests are video compression and VLSI implementation.Chung-Neng Wang was born in PingTung, Taiwan, in 1972. He received the B.S. degree and Ph.D degree in computer science and information engineering from National Chiao-Tung University (NCTU), HsinChu, Taiwan in 1994 and 2003, respectively. He joined the faculty at National Chiao-Tung University in Taiwan, R.O.C in January 2003.Since 2001 he has actively participated in ISO’s Moving Picture Experts Group (MPEG) digital video coding standardization process. He has made more than 18 contributions to the MPEG committee over the past 4 years. He published over 23 technical journal and conference papers in the field of video and signal processing. His current research interests are video/image compression, motion estimation, video transcoding, and streaming.Tihao Chiangwas born in Cha-Yi, Taiwan, Republic of China, 1965. He received the B.S. degree in electrical engineering from the National Taiwan University, Taipei, Taiwan, in 1987, and the M.S. degree in electrical engineering from Columbia University in 1991. He received his Ph.D. degree in electrical engineering from Columbia University in 1995. In 1995, he joined David Sarnoff Research Center as a Member of Technical Staff. Later, he was promoted as a technology leader and a program manager at Sarnoff. While at Sarnoff, he led a team of researchers and developed an optimized MPEG-2 software encoder. For his work in the encoder and MPEG-4 areas, he received two Sarnoff achievement awards and three Sarnoff team awards.Since 1992 he has actively participated in ISO’s Moving Picture Experts Group (MPEG) digital video coding standardization process with particular focus on the scalability/compatibility issue. He is currently the co-editor of the part 7 on the MPEG-4 committee. He has made more than 90 contributions to the MPEG committee over the past 10 years. His main research interests are compatible/scalable video compression, stereoscopic video coding, and motion estimation. In September 1999, he joined the faculty at National Chiao-Tung University in Taiwan, R.O.C. Dr. Chiang is currently a senior member of IEEE and holder of 13 US patents and 30 European and worldwide patents. He was a co-recipient of the 2001 best paper award from the IEEE Transactions on Circuits and Systems for Video Technology. He published over 50 technical journal and conference papers in the field of video and signal processing.     

An Analog/Digital Baseband Processor Design of a UWB Channelized Receiver for Transmitted Reference Signals

The frequency channelized receiver enables the use of practical analog-to-digital converters (ADC) to digitize ultra-wideband (UWB) signals. The design issues of the analog and digital baseband processor for the channelized receiver in a UWB transmitted reference (TR) system are investigated. In the analog part, the receiver performance is shown to be weakly dependent on the analog filter bandwidth, the filter order, and the ADC oversampling ratio assuming white input noise. In the digital part, the coarse acquisition performance is shown to be significantly better in a channelized receiver than in a fullband receiver. The implementation issues for fine synchronization and correlation window length are also studied. Lei Feng received the B.S. and M.S. degree in electrical engineering from Peking University, Beijing, in 1997 and 2000, respectively. He is currently working toward the Ph.D degree in electrical engineering at University of Southern California, Los Angeles, CA. His doctoral research focuses on the design of wideband communication transceivers for wireless and wireline applications. Won Namgoong received the BS degree in Electrical Engineering and Computer Science from the University of California at Berkeley in 1993, and the MS and Ph.D. degrees in Electrical Engineerig from Stanford University in 1995 and 1999, respectively. In 1999, he joined the faculty of the Electrical Engineering Department at the University of Southern California, where he is an Assistant Professor. His current research areas include wireless/wireline communication systems, signal processing systems, RF circuits, and low-power/high-speed circuits. In 2002, he received the National Science Foundation (NSF) CAREER Award.     

A time-to-first spike CMOS image sensor with coarse temporal sampling

Conventional voltage-based CMOS image sensors inherently have a dynamic range of about 60 dB. To extend the dynamic range, a two-degree of freedom time-based CMOS image sensor is proposed. Instead of reading analog voltages off chip, a time representation is used to record when the photodetector voltage passes a timing-varying threshold. The time measurements are combined with the reference voltage waveform to reconstruct the image. Experimental results on a prototype 32 × 32 pixel array CMOS image sensor verify that the two-degree of freedom sampling technique is feasible for ultra-wide dynamic range imaging. A measured 115 dB dynamic range at 30 fps is obtained. Qiang Luo received the B.S. (with honor) and M.S. degrees in electrical engineering from Fudan University, Shanghai, China, in 1995 and 1998, respectively, and the Ph.D. degree in electrical engineering from University of Florida, Gainesville, FL, in 2002. In 2001, he was with Texas Instruments Inc., Dallas, TX, where he was an intern engineer working on ultra-wide dynamic range CMOS image sensors. From 2002 to 2004, he was with National Semiconductor Corporation, Santa Clara, CA, where he was a staff circuit design engineer and worked on the design of high performance CMOS image sensors. He is currently with the Marvell Semiconductor Inc, Sunnyvale, CA, where he is working on the development of advanced DVD servo IC. His research interests include high-speed mixed-signal IC design, CMOS image sensors, DVD servo IC and device physics. Dr. John G. Harris received his BS and MS degrees in Electrical Engineering from MIT in 1983 and 1986. He earned his PhD from Caltech in the interdisciplinary Computation and Neural Systems program in 1991. After a two-year postdoc at the MIT AI lab, Dr Harris joined the Electrical and Computer Engineering Department at the University of Florida (UF). He is currently an associate professor and leads the Hybrid Signal Processing Group in researching biologically-inspired circuits, architectures and algorithms for signal processing. Dr. Harris has published over 100 research papers and patents in this area. He co-directs the Computational NeuroEngineering Lab and has a joint appointment in the Biomedical Engineering Department at UF. Zhiliang J. Chen received Ph.D. degree in electrical engineering from University of Florida in 1994. From 1994 to 2004, he was with Texas Instruments where he worked as Senior Member of Technical Staff and Design Branch Manager. In 2002 he was expatriated to COMMIT, a Texas Instruments JV company in China, as director of RF & Analog Base Band department. In 2004, he left Texas Instrument and found On-Bright (Shanghai) Corporation where he serves as president of the company. Dr. Chen currently held 22 US patents and has published morn than 10 journal papers. He was a recipient of the Best Paper Award from the 1997 ESD/EOS symposium.     

A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices

This paper extends the timing test model in [5] to be more realistic by including the effects of the test fixtures between a device under test and a tester. The paper enables analyzing the trade-offs that arise between the predicted yield and the required overall test environment timing accuracy (OTETA) which involves the tester overall timing accuracy (OTA) and the test fixtures' impacts. We specifically focus on the application of the extended model to predict the test yield of standard high-speed interconnects, such as PCI Express, Parallel/Serial RapidIO, and HyperTransport. The extended model reveals that achieving an actual yield of 80% with a test escape of 300 DPM (Defects Per Million) requires an equivalent OTETA that is about half the acceptable absolute limit of the tested parameter. Baosheng Wang received his B.S. degree from Beijing University of Aeronautics and Astronautics (BUAA), Beijing, P.R. China, in 1997 and M.S. degree from Precision Instrument & Mechanical Engineering from the Tsinghua University, Beijing, P. R. China in 2000. In 2005, he received his Ph.D. degree in Electrical Engineering from the University of British Columbia (UBC), Vancouver, BC, Canada. During his Master study, he was doing MEMS, Micro Sensors and Digital Signal processing. From 2000 to 2001, he worked in Beijing Gaohong Telecommunications Company as a hardware engineer in ATM technology. Currently, he is a Design-for-Test (DFT) engineer at ATI Technologies Inc., Markham, Ontario, Canada. He publishes widely at international conferences and journals. His primary research interests are time-driven or timing-oriented testing methodologies for System on-a-Chip (SoC). These fields include test time reduction for SRAMs, accelerated reliability test for non-volatile memories, yield analysis for SoC timing tests, SoC path delay timing characterization and embedded timing measurements. Andy Kuo is currently a Ph.D student of System on a Chip (SoC) Research Lab at the Department of Electrical and Computer Engineering, University of British Columbia. He received his M.A.Sc. and B.A.Sc in electrical and computer engineering from University of British Columbia and University of Toronto in 2004 and 2002 respectively. His research interests include high-speed signal integrity issues, jitter measurement, serial communications. Touraj Farahmand received the B.Sc. degree in Electrical Engineering from Esfahan University of Technology, Esfahan, Iran in 1989 and the M.Sc. in Control Engineering from Sharif university of Technology, Tehran, Iran in 1992. After graduation, he joined the Electrical and Computer Research center of Esfahan University of Technology where he was involved in the DSP algorithm development and design and implementation of the control and automation systems. Since October 2001, he has been working in the area of high-speed signal timing measurement at SoC (System-on-a-Chip) lab of UBC (University of British Columbia) as a research engineer. His research interests are signal processing, jitter measurement, serial communication and control. André Ivanov is Professor in the Department of Electrical and Computer Engineering, at the University of British Columbia. Prior to joining UBC in 1989, he received his B.Eng. (Hon.), M. Eng., and Ph.D. degrees in Electrical Engineering from McGill University. In 1995–96, he spent a sabbatical leave at PMC-Sierra, Vancouver, BC. He has held invited Professor positions at the University of Montpellier II, the University of Bordeaux I, and Edith Cowan University, in Perth, Australia. His primary research interests lie in the area of integrated circuit testing, design for testability and built-in self-test, for digital, analog and mixed-signal circuits, and systems on a chip (SoCs). He has published widely in these areas and holds several patents in IC design and test. Besides testing, Ivanov has interests in the design and design methodologies of large and complex integrated circuits and SoCs. Dr. Ivanov has served and continues to serve on numerous national and international steering, program, and/or organization committees in various capacities. Recently, he was the Program Chair of the 2002 VLSI Test Symposium (VTS'02) and the General Chair for VTS'03 and VTS'04. In 2001, Ivanov co-founded Vector 12, a semiconductor IP company. He has published over 100 papers in conference and journals and holds 4 US patents. Ivanov serves on the Editorial Board of the IEEE Design and Test Magazine, and Kluwer's Journal of Electronic Testing: Theory and Applications. Ivanov is currently the Chair of the IEEE Computer Society's Test Technology Technical Council (TTTC). He is a Golden Core Member of the IEEE Computer Society, a Senior Member of the IEEE, a Fellow of the British Columbia Advanced Systems Institute and a Professional Engineer of British Columbia. Yong Cho received the B.S. degree from Kyung Pook National Unviersity, Korea, in 1981 and the M.S. degree from in electrical and computer engineering from the University of South Carolina, Columbia, S.C., in 1988 and the Ph.D. degree in electrical engineering and applied physics from Case Western Reserve University, Cleveland, OH, in 1992. He is currently a Professor with the Department of Electronics Engineering, Konkuk University, Seoul, Korea. His recent research interests include SoC Design and Verification, H/W and S/W co-design, and embedded programming on SoC. Sassan Tabatabaei received his PHD in Electrical Engineering from the University of British Columbia, Vancouver, Canada in 2000. Since then, he has held several senior technical positions at Vector12 Corp, Guide Technology, and Virage Logic. His professional and research interests include mixed-signal design and test, and signal integrity and jitter test methodologies for high-speed circuits and multi-Gbps serial interfaces. He has published several papers and holds a US patent in the area of timing and jitter measurement. Currently, he holds the position of the director for embedded test at Virage Logic Corporation.     

A Prototype Bandpass Sigma-Delta Modulator Employing Crystal Resonator

This paper describes an initial work on a second-order bandpass Sigma-delta modulator employing crystal resonator. The aim of this work is to explore the possibilities of realizing bandpass sigma-delta modulator using non-electronic resonators, such as micro-mechanical resonators. The initial study is based on crystal resonators as they have similar characteristics as the other types of resonator and are readily available. In order to obtain the desired loop transfer function, a compensation circuit is proposed to cancel the anti-resonance in the crystal resonator. The modulator chip is fabricated in a 0.6-μ m CMOS process. The bandpass noise shaping is demonstrated in the experiment with a 1- and 8-MHz crystal resonator, respectively. Yong Ping Xu graduated from Nanjing University, P.R. China in 1977. He received his Ph.D. from University of New South Wales (UNSW) Australia, in 1994. From 1978 to 1987, he was with Qingdao Semiconductor Research Institute, P.R.China, initially as an IC design engineer, and later the deputy R&D manager and the Director. From 1993 to 1995, he worked on an industry collaboration project with GEC Marconi, Sydney, Australia, at the same university, involved in design of sigma-delta ADCs. He was a lecturer at University of South Australia, Adelaide, Australia from 1996 to 1998. He has been with the Department of Electrical and Computer Engineering, National University of Singapore since June 1998 and is now an Associate Professor. His general research interests are in the areas of mixed-signal and RF integrated circuits, and integrated MEMS and sensing systems. He is a Senior Member of IEEE. Xiaofeng Wang was born in Shangqiu, China, in 1980. He received B.Eng. degree from Northwestern Polytechnical University, Xi'an, China, in 2000 and M. Eng. degree from National University of Singapore, Singapore, in 2003, both in electrical engineering. He is currently working toward the Ph.D. degree at Tufts University, Medford, USA. His research is on high speed ADC design. Wai Hoong Sun was born in Taiping, Malaysia in 1976. He received the B. App. Sc. (Honours) degree in electrical engineering from the University of Toronto, Canada in 1999. After graduating, he joined Sharp Electronics Singapore as an R&D Engineer where he was involved in FPGA and digital IC design of display related circuits. In 2001 and 2002, he did full time research in the National University of Singapore on bandpass sigma-delta modulators. During that period, he was also a Graduate Tutor in electronics for second year electrical and computer engineering students. He then joined Philips Electronics Singapore in 2002 as a Lead Engineer. He did board-level designs for LCD and plasma televisions. He was also development project leader for a project that was successful in bringing to the market a range of LCD and plasma televisions. Currently, he is a Hardware Architect where he is responsible for the system-level electrical design of the television board.     

Simplified Modeling of a Multipole Amplifier Using All-Pass Network Functions

This paper presents a system model for the representation of amplifiers that cannot be accurately characterized by a classical two pole transfer function. The effects of higher order poles are modeled by an all-pass function added to the conventional two pole model. The accuracy of the model is demonstrated by comparing the results for a typical CMOS amplifier to those obtained from device level simulations using SPICE. This model can be easily implemented in a standard simulator and is shown to achieve fast simulation time. This model is expected to have application in system level modelling of mixed-signal circuits using conventional SPICE simulators.Yihong Dai received his B.S. and M.Eng. degrees in Electrical Engineering from Shanghai JiaoTong University, Shanghai, China in 1993 and 1996, respectively. From 1996 to 1998, he enjoyed his industrial experiences in Shanghai with semiconductor companies like Shanghai Nortel Semiconductor and Motorola Electronics (China) Shanghai Branch. Since 1998, he has been a research assistant at the Analog and Mixed-signal Laboratory of the Electrical Engineering Department of Brigham Young University working toward his Ph.D. During the summer of 1999, he was with AMI semiconductor Utah Research and Design Center where he developed a threshold voltage based CMOS voltage reference architecture. In the summer of 2001, he was with Ultra Design where he designed a reference amplifier for high speed digital-to-analog converters. His research interest includes voltage reference, reference amplifier and high speed data converters in both CMOS and GaAs processes.Donald T. Comer received the B.S, M.S., and Ph.D. degrees from San Jose State University, the University of California (Berkeley), and the University of Santa Clara, respectively, all in electrical engineering. He began teaching at San Jose State University in 1961 and mixed his teaching and industrial work until he left San Jose State University in 1979. He has worked for California Technical Industries, IBM Corp., Mobility Systems, Precision Monolithics, Storage Technology Corp., and Analog Devices during his career. He founded the AMI Utah Research and Design Center in 1998 that specializes in MOS design. In 2002, Dr. Comer founded Ultra Design, a design center that specializes in high-frequency heterojunction circuit designs. He holds fifteen patents and has published over 50 articles dealing with solid-state and integrated circuits. He has published five textbooks in the field of large-signal and integrated circuits. He formerly held the Quentin Berg Chair at Penn State Harrisburg from 1990 to 1995. He is now a professor of electrical and computer engineering at Brigham Young University where he held the Endowed Chair of Engineering from 1995 to 1998.David J. Comer received the B.S., M.S., and Ph.D. degrees from San Jose State University, the University of California (Berkeley), and Washington State University, respectively, all in electrical engineering. He has worked for IBM Corp., Pacific Electromagnetics, Lawrence Livermore Laboratories, and Intel Corporation. He began his teaching career at the University of Idaho and has taught at the University of Calgary and California State University, Chico. He is presently a professor of electrical and computer engineering at Brigham Young University. He served as Chairman of the Division (Dean) of Engineering at CSU, Chico and as Department Chair at BYU.While at CSU, Chico, Dr. Comer served on the statewide Engineering Liaison Committee and served as Chair of the Council of California State University Deans of Engineering.Dr. Comer has published twelve textbooks and over 60 articles in the field of circuit design. He has contributed sections to the Encyclopedia of Physical Science and Technology and holds seven patents. He was given the Professional Achievement Award at CSU, Chico and was named the Outstanding Teacher of Engineering at BYU. He has also held the College of Engineering Research Chair at Brigham Young University.Darren Korth received the B.S. and M.S. degrees in electrical engineering at Brigham Young University, Provo, Utah in 1999. He is currently pursuing a Ph.D. in electrical engineering. He served as an instructor for the Department of Electrical and Computer Engineering at Brigham Young University from 2000 to 2002. From 2001 to 2003, he also worked as a senior design engineer at UltraDesign, LLC, Provo, Utah where he researched high-speed data converter circuits. He is currently with AMI Semiconductor in their RF CMOS group.     

A 3-A CMOS low-dropout regulator with adaptive Miller compensation

A 3-A CMOS low-dropout regulator (LDO) is presented by utilizing adaptive Miller compensation (AMC) technique, which provides high stability, as well as fast line and load transient responses. The proposed LDO has been fabricated in a standard 0.5 μm CMOS technology, and the die area is small as 1330 μm × 1330 μm with the area-efficient waffle layout for power transistors. Both load and line regulation are less than ±0.1%. And the output voltage can recover within 80 μs for full load changes. The power–supply rejection ratio (PSRR) at 20 KHz is −30 dB. Moreover, it is stable enough with a ceramic capacitor small to 2.2 μF, and the added series resistance is not needed. Xinquan Lai received his BSc degree in Technical Physics in 1987, and MSc degree in Electronic Engineering in 1993, both from the Xidian University, Xi’an, China. And he received a PhD degree in Computer Science & Engineering from the Northwestern Polytechnical University (NPU) in 1998. He is currently a professor in Xidian University. His present research interests include mixed signal VLSI/ASIC and SOC design, CMOS Sensor, and power management IC design, validation, test and other relative theories. Jianping Guo was born in Jiangxi, P.R. China in 1981. He received the BSc and MSc degrees in electronic engineering from Xidian University, Xi’an, China, in 2003 and 2006, respectively. He is currently severed as power management IC engineer in Xi’an Deheng Microelectronic Inc. His research interest involves power management IC design such as LDO linear regulator, DC-DC switching regulator etc. Zuozhi Sun was born in Zhejiang, P. R. China in 1978. He received the BSc and MSc degrees in electronic engineering from Xidian University, Xi’an, China, in 2000 and 2003, respectively. He joined Xi’an Deheng Microelectronic Inc. in 2003, where he works on development of power management IC. His research interest involves power management IC, audio amplifier etc. Jianzhang Xie received his BSc and MSc degrees in electronic engineering from Xidian University, Xi’an, China, in 1998 and 2005, respectively. He joined AIWA (Shenzhen) Ltd. as an electronic circuit designer in 1998, and now he is severed as an analog and mixed IC engineer in RENEX Technology (Shanghai) Ltd. His research interest involves power management IC, PLLs and high speed communication circuits.