针孔缺陷对集成电路功能成品率影响分析与仿真

对集成电路针孔缺陷引起功能成品率下降的模型进行了研究,给出了分析和仿真针孔功能成品率的两种计算方法——Monte-Carlo方法和关键面积提取方法,这对集成电路成品率设计和分析是非常重要的.     

集成电路功能成品率模拟与设计方法

本文基于在缺陷空间分布和粒径分布的模型，研究并讨论了计算集成电路（ＩＣ）功能成品率的理论和模拟ＩＣ功能成品率的方法．为了验证所研究方法和模型的正确性，对测试图样和实际ＩＣ的功能成品率进行模拟，并分析了影响功能成品率的几个因素，得到了有益的结果．     

集成电路局部缺陷模型及其相关的功能成品率分析

大规模集成电路（VLSI）使亚微米特征尺寸的大面积集成电路制造以及集成数百万个器件在一芯片上成为可能。然而,缺陷的存在致使电路版图的拓扑结构发生变化,产生IC电路连接错误,导致电路丧失功能,从而影响IC的成品率,特别是功能成品率。文章主要对缺陷的轮廓模型、空间分布模型和粒径分布模型作了介绍;对集成电路成品率的损失机理作了详细论述。最后,详细介绍了功能成品率的分析模型。     

提高砷化镓功率MMIC中电容成品率的研究

金属－绝缘体－金属（ＭＩＭ）电容量影响ＧａＡｓ微波单元集成电路（ＭＭＩＣ）成品率的主要原因之一，ＰＥＣＶＤ氮化硅膜又是影响ＭＩＭ电容质量和成品率的主要因素。本文通过实验和分析，提出了提高氮化硅膜质量和减少薄膜针孔的方法，结果大大提高了ＭＩＭ电容ＧａＡｓＭＭＩＣ的成品率，降低了ＧａＡｓ ＭＭＩＣ的成本。     

集成电路成品率研究

集成电路的成品率是集成电路制造中的一个重要问题。只有高水平的集成电路成品率，才能降低集成电路成本，带来集成电路的高质量及高可靠性。文章首先介绍了成品率的要领然后研究了成品率的理论计算方法有经验，半经验公式，最后简单地概述了提高集成电路成品率的实践途径。     

一种基于非参数统计的微波集成电路成品率优化算法

给出了一种新的微波集成电路成品率优化算法——基于非参数统计的成品率快速优化算法。利用该方法，仅需要较少的仿真次数或直接利用非参数统计成品率分析算法的结果，便可直接得出一组或几组参数的成品率优化值，有效地缩短了优化时间。算例表明，该方法对微波集成电路进行快速成品率优化设计及提高电路设计的稳定性具有较好的应用价值。     

功能成品率估算的缺陷特征参数提取方法

基于微电子测试双桥结构,本文给出了缺陷特征参数提取方法.这些特征参数包含了缺陷在硅片上的空间分布和粒径(直径)分布,它们对集成电路功能成品率仿真是重要的.     

一种基于数值积分的集成电路成品率估计方法

本文提出了一种基于数值积分的集成电路成品率估计方法。该方法通过直接在可接受域上对性能的联合概率密度函数进行积分获得成品率的估计。为达到此目的,性能的仿真数据须先经由Box-Cox变换 (BCT) 转化为服从多变量正态分布的数据。同时,文中采用了基于正交表的改进拉丁超立方体抽样法 (OA-MLHS) 对电路的工艺扰动参数实施抽样,如此可以大幅减小联合概率密度函数中分布参数的估计方差。文中对结合使用OA-MLHS与BCT从而减少了分布参数的估计方差的数学原理进行了分析。以一个四阶OTA-C低通滤波器和一个三维二次函数的成品率估计为例,在不同的样本量及成品率水平的组合下,对包含拉丁超立方体抽样和重要抽样等的六种不同的成品率估计法做了性能比较。大量的仿真证明本文所述的方法无论在精度还是效率上都要优于其他几种方法。因此,该方法更加适用于集成电路的成品率优化。     

渗透刻蚀技术

一 前言 随着半导体工业的发展,大规模、超大规模,集成电路中为了提高成品率,提高集成度,对细微线条加工技术的要求愈来愈高,因此相继出现了电子束曝光,x射线曝光等,而干法光刻工艺也是这个方面的一个新工艺,它具有高分辨率,工艺简单,操作方便,针孔少等特点,省去了大量贵重而且对人体有害的化学药品——丁酮,因此各个单位对于干法渗透刻蚀都很重视。     

反应溅射氧化铁光刻掩模试制小结

一、概述 在以往的集成电路的生产中,尤其是在中、大规模集成电路的试制中,深深感到高质量光刻掩模的需要。举例说:在多层布线工艺试验工作中,目前最难于解决的问题莫过于光刻中所产生的针孔,而针孔的产生,掩模的质量是问题的主要方面之一。在中、大规模集成电路的试制中,由于芯片的集成度提高,芯片尺寸增加,掩模图形质量对电路成品率产生巨大影响,不解决掩模质量问题,中、大规模电路的批量生产看来是困难的。由于生产和科研工作开展的实际需要,促使我们开展了选择性透光掩模(即彩色版)的试制。 选择性透光掩模之所以受人注意,主要是它们具有以下几方面优点: a.具有选择性透光,便于光刻时图形套准,而且不必在掩模上作对准标记。 b.光反射率低,改善了边缘锐度,提高了分辨率,有利于细线条光刻。光反射率低,使光刻操作者眼睛不致疲劳。 c.透光掩模本身具有优良的薄膜特性,如针孔密度小,粘附性好,耐划伤等。 目前,一般认为具有代表性的有发展前途的透光掩模大致有三种:即硅、氧化铬和氧化铁。硅掩模是一种相当出色的掩模。据称硅掩模针孔密度最小,可认为无针孔     

等离子增强化学气相沉积法低温生长SiO_x薄膜的针孔缺陷修复

针对等离子增强化学气相沉积(PECVD)方法低温(60℃)生长氧化硅(SiOx)薄膜中存在的针孔缺陷,在SiOx薄膜上采取原子层沉积(ALD)方法生长氧化铝(AlOy),利用ALD方法材料保形生长的特点,进行SiOx薄膜的针孔缺陷修复工艺技术研究。实验结果表明:在SiOx薄膜上利用ALD方法保形生长氧化铝,可以明显降低AlOy/SiOx复合薄膜的水汽渗透率,提高薄膜封装性能。通过实验数据分析认为:复合薄膜的水汽阻隔能力是由于ALD方法及PECVD方法两种薄膜生长方法的综合作用,这种综合作用很有可能来自PECVD方法薄膜中针孔缺陷的修复,而ALD方法正是完成修复过程的技术手段。另外,ALD方法的工艺参数与针孔缺陷的修复效果相关,ALD生长周期时间延长,有利于提高针孔缺陷的修复效果,从而降低了复合薄膜的水汽渗透率。     

基于制造成品率模型的集成电路早期可靠性估计

缺陷是影响集成电路成品率与可靠性的主要因素.本文在区分缺陷与故障两个概念的基础上,将缺陷区分为成品率缺陷(硬故障)、可靠性缺陷(软故障)和良性缺陷.利用关键区域的面积,给出了一个缺陷成为"硬故障"或"软故障"的概率,给出了精度较高的IC成品率预测模型.利用成品率缺陷与可靠性缺陷之间的关系,给出了工艺线生产的产品的失效率与该工艺线制造成品率之间的定量关系.在工艺线稳定的条件下,通过该工艺线的制造成品率可以利用该关系式可以有效的估计出产品的失效率,可以有效地缩短了新产品的研发周期.     

CMOS工艺氧化膜完整性的评估

提出了用阵列电容来监测氧化层的完整性。分析表明,从多个子列的氧化层电容漏电合格率的曲线可以求出氧化层完整性的表征因子Ｅ值（每个缺陷包含的单元数）。     

考虑缺陷形状分布的IC成品率模型

实现了基于圆缺陷模型的蒙特卡洛关键面积及成品率估计,模拟了圆缺陷模型估计的成品率误差与缺陷的矩形度之间的关系,提出了更具有一般性的两种集成电路成品率模型,它们分别对应于矩形度相同和不同的缺陷．仿真结果表明该模型为成品率的精确表征提供了新途径．     

An ROBDD-Based Combinatorial Method for the Evaluation of Yield of Defect-Tolerant Systems-on-Chip

In this paper, we develop a combinatorial method for the evaluation of the functional yield of defect-tolerant systems-on-chip (SoC). The method assumes that random manufacturing defects are produced according to a model in which defects cause the failure of given components of the system following a distribution common to all defects. The distribution of the number of defects is arbitrary. The yield is obtained by conditioning on the number of defects that result in the failure of some component and performing recursive computations over a reduced ordered binary decision diagram (ROBDD) representation of the fault-tree function of the system. The method has excellent error control. Numerical experiments seem to indicate that the method is efficient and, with some exceptions, allows the analysis with affordable computational resources of systems with very large numbers of components.      

Growth and microstructure of InxGa1−xN films grown on SiC substrates via low pressure metalorganic vapor phase epitaxy

The growth and microstructures of In_xGa_1−xN films (x≤0.23) grown on α(6H)–SiC(0001) wafer/AIN buffer layer/GaN heterostructures by low pressure metalorganic vapor phase epitaxy have been investigated. The system deposition pressure limited the InN content in these films. The maximum InN contents achievable at the deposition pressures of 45 and 90 torr were ∼13 and ∼23%, respectively. Kinetic phenomena based on the rates of adsorption and desorption of the In growth species off the growth surface are presented to explain the film composition dependence on the system pressure. The surface morphologies and microstructures of the In_xGa_1−xN films were analyzed using several techniques, and the formation of pinhole defects in the films was investigated. Most of the pinhole defects were associated with threading dislocations with a c-component Burgers vector. Edge-type dislocations were never observed to terminate in pinholes in the samples observed here. Indium segregation to areas around the defect areas was observed, as was an In compositional gradient in the growth direction. Based on experimental observations, the strain field around dislocations with a c-component Burgers vector could result in the increase of In atoms at the dislocation sites in the film, which result in a change to the local growth mode of the film and causes the pinhole defects to form.     

Origin of Surface Defects in PCB Final Finishes by the Electroless Nickel Immersion Gold Process

We suggest a unique mechanism for surface defect generation causing solder joint or bonding failures in printed circuit boards (PCBs). Surface defects can be defined as corroded holes or spikes of the Ni-P layers on the soldering or wire bonding pads of PCBs. The typical defects are the black pad or pinhole pad defects generated after final finishing by the electroless nickel immersion gold (ENIG) process. Once corroded voids or spikes are plentifully created in nickel/gold interfaces, the bonding strength of solder or wire bonding joints is reduced. Therefore, it is important to characterize the details of these surface defects. In this paper, the defect microstructures and the P content variation with the ENIG processes are investigated. The surface defect selectivity with pad size and pad connectivity is suggested based on the key findings of P content variation. An overall mechanism is proposed based on a mixed mode of concentration cell corrosion and galvanic cell corrosion. Based on these results, more reasonable root causes are suggested.     

In-process functional testing of pixel circuit in AM-OLEDs

This paper presents a functional testing scheme using a two-thin-film-transistor (TFT) pixel circuit of an active-matrix organic light-emitting display (AM-OLED). This pixel circuit and the co-operative electrical testing scheme can not only evaluate the characteristics of each TFT, but also determine the location of line and point defects in the TFT array. Information on defects can be used in a unique repair system that cutting and repairing these defects. Furthermore, the functional testing scheme can be applied as a part of yield management of the AM-OLED array process.     

Suppression of pinhole defects in fullerene molecular electron beam resists

Molecular resists, such as fullerenes, are of significant interest for next generation lithographies. They utilize small carbon rich molecules, giving the potential for higher resolution and etch durability, together with lower line width roughness than conventional polymeric resists. The main problem with such materials has historically been low sensitivity, but with the successful implementation of chemical amplification schemes for several of the molecular resist families this is becoming less of a concern. Aside from sensitivity the other main obstacle has been the difficulty of preparing good quality thin films of non-polymeric materials. Here we present a study of pinhole defect density in fullerene films as a function of substrate cleanliness, post-application bake, and incorporation of chemical amplification components. Ultrathin (sub 30 nm) films of the previously studied fullerene resist MF03-01, and the polymeric resist PMMA were prepared on hydrogen terminated silicon by spin coating and the density of pinhole defects in the films was studied using atomic force microscopy. It was seen that pinhole density was strongly affected by the quality of the substrates, with the lowest densities found on films spun on freshly cleaned substrates. Aging of the film subsequent to spin coating was seen to have less effect than similar aging of the substrate prior to spin coating. Additionally, the use of a post-application bake significantly degraded the quality of the films. The addition of an epoxy crosslinker for chemical amplification was found to reduce defect density to very low levels.