基于改进CORDIC算法的数字预失真实现

针对传统CRODIC算法存在的角度扩展、迭代复杂度等问题,在旋转模式下提出一种改进型CORDIC算法。对于旋转角度范围的扩展,采取将向量限制在第一和第四象限,旋转最后再根据输入向量符号判断旋转角度值;对于迭代复杂度,采用跳跃旋转方式来减少迭代次数。最后在Quartus软件上实现了该改进算法,并且将改进后的CORDIC算法应用于数字预失真技术,在FPGA上设计实现。仿真与实验结果表明:与传统的CORDIC算法相比,改进算法减少了硬件的开销,运算速度和精度都有很大改进,能够快速提取预失真参数,显著提高功率放大器的线性度。     

基于改进Scaling-Free CORDIC算法的DDS

直接数字频率合成器(Direct Digital Synthesizer,DDS)在现代数字通信系统中有非常重要的应用。基于CORDIC算法的DDS在高速、高精度信号源领域已得到广泛应用,但传统的CORDIC算法存在迭代次数多、硬件消耗资源大、缩放因子补偿误差等问题。文章提出固定角度的传统迭代预旋转和分段双步SF(Scaling-Free)CORDIC算法旋转方式,有效减少了算法的迭代次数,并且采用区间映射将收敛区间扩展到[0,2π]。结果表明,该算法在保持高计算精度的同时减少了迭代次数和面积消耗。基于此算法的DDS产生的正交信号具有精度高、噪声低、线性度好等优点。     

基于FPGA的CORDIC算法实现

针对传统CORDIC算法延时大,消耗资源多的缺点,在平行CORDIC算法的基础上提出了一种优化的平行算法,利用二进制转两极算法和微旋转角度编码对低部和高部的旋转方向进行预测,并在高部旋转中利用正反旋转抵消的策略来进一步减少旋转次数,提高运算速度。采用FPGA对提出的算法进行了硬件设计和验证,结果表明,计算迭代次数少,资源消耗少,精度较传统算法来说都有了明显改善。     

数字下变频中基于CORDIC算法的NCO设计

在数字下变频中传统数字控制振荡器(Numerically Controlled Oscillator,NCO)模块都是基于查找表结构的,该结构在FPGA内部实现需要占用大量ROM资源,针对这一问题,提出采用坐标旋转数字计算(Coordinate Rotation Digital Computer,CORDIC)算法进行NCO设计,相比传统的NCO设计,该方法具有输出信号频谱纯度高、能够直接混频而不需要乘法器等优点。设计中采用变象限映射方法解决CORDIC算法无法全周期覆盖的问题,采用流水线技术解决串行迭代带来难以实时输出的问题。经过Modelsim仿真分析,实际输出值与理论值之间的相对误差在10-4~10-5数量级范围内,满足数字下变频中NCO的性能需要。     

免缩放因子双步旋转CORDIC算法

集成电路设计中经常使用CORDIC算法实现高效的向量旋转操作.当前对该算法的研究热点集中在减少该算法的迭代次数、扩展其收敛范围以及降低缩放因子补偿操作的代价等问题上.本文提出免缩放因子的双步旋转CORDIC算法使用双步旋转策略,减少了免缩放因子CORDIC算法的迭代次数,将收敛区间扩展到了整个圆周区间.实验结果表明,该算法保持高计算精度的同时减少了迭代次数和面积消耗.     

CORDIC算法的FPGA与DSP实现的优劣分析

介绍了坐标旋转数字计算机（CORDIC）的算法原理,分析了算法中旋转迭代次数、操作数位宽与精度的关系,在现场可编程门阵列（FPGA）芯片和数字信号处理器（DSP）芯片上用全流水、高并行结构分别实现了旋转模式下的CORDIC算法,并将两者的精度、时间效率、空间效率的优劣进行比较。结果表明,DSP数值精度比FPGA高且设计更灵活,可移植性更强;而FPGA速度远远快于DSP,消耗硬件资源更少。     

多模式CORDIC算法结构改进与实现

本文对计算反正余弦函数的CORDIC算法的迭代结构进行了改进,并在此基础上完成多模式CORDIC算法的实现.通过重新设定初始旋转向量避免了前两级迭代,通过修改向量旋转方向的判决条件对原算法的误差进行了校正,在增加了很少资源的情况下将正余弦运算和反正余弦运算统一到同样的迭代结构中并予以实现.实现结果表明改进后的算法反正余弦运算结果有更高的运算精度,在两种运算函数都需要的应用中能够有效减少的硬件资源占用.     

基于CORDIC旋转器的基-3 FFT算法高效设计

设计出一种可以用于FPGA高效实现的基-3 FFT算法,采用改进的三端前馈延迟转换器结构,优化了延迟和运算过程。针对蝶形运算中复数乘法器占据大量内存的问题,引入了CORDIC旋转器实现输入与旋转因子相乘的运算,可以降低乘法运算的复杂度,该CORDIC旋转器采用改进的高基CORDIC算法,解决了传统的CORDIC算法迭代次数多、延迟大的问题,从而达到高吞吐率要求。该基-3 FFT算法以寻址变序、流水处理的方式,可以满足最高运行频率为404 MHz的FFT处理要求。与基于传统复数乘法器的基-3 FFT算法相比,基于CORDIC旋转器的基-3 FFT算法使功耗平均减少了22%,使总延迟平均减少了29%。     

利用CORDIC算法提取脉内特征在FPGA上的实现

介绍了坐标旋转数字计算(CORDIC)算法的原理,给出了利用CORDIC算法提取信号脉内特征的迭代公式,在此基础上实现了用该算法的流水型迭代结构提取瞬时幅度、相位和频率的FPGA电路,解决了电路中的时钟与寄存器配置、数据的补码格式和相位累加等问题。通过在硬件芯片上的下载验证,表明电路结构合理、测试有效,满足设计要求。     

采用CORDIC算法的数控振荡器设计

基于CORDIC（坐标旋转数字计算）算法的NCO（数控振荡器）设计方法克服了传统数字下变频器查询表大的缺点,摆脱了用查表法产生离散正弦信号需要占用大量ROM资源的弊端,提高了资源的利用率,减小了硬件设计的代价。该算法使数控本振和数字混频两个功能合在一起完成,省去了2个乘法器,利用CORDIC算法CORDIC旋转的移位一相加流水结构,实现了数字下变频器的设计,其有效性通过仿真得到验证。     

一种多进制连续相位调制信号的符号定时跟踪方法

针对多进制连续相位调制信号(MCPFSK)的传输系统,提出一种在相位上提取定时误差的符号定时跟踪方法,并分析定时跟踪环路的特性。根据MCPFSK信号特性,接收端将信号差分、鉴相后,利用多进制信号特性提取定时误差。Matlab仿真结果表明,在加性高斯白噪声信道上,该方法能准确地估算出定时偏差,适用于MCPFSK信号的非相干差分解调系统。     

大容量多通道数字水印算法

现有许多数字水印算法基本上都是针对灰度图像的，彩色图像数字水印算法尚未得到充分研究，且所能嵌入水印的容量也不够大。本文提出的大容量多通道数字水印算法对这一问题进行了研究。该算法以彩色图像作为原始载体，通过数字水印压缩编码，载体图像颜色空间转换，彩色分量分块离散余弦变换，结合人眼视觉系统确定水印嵌入位置等措施，将二维水印图像嵌入到原始彩色载体图像中，且能嵌入较大容量的水印图像。实验结果表明，该算法不仅提高了水印容量，且对剪切、模糊、锐化等有损攻击具有良好的健壮性。     

一种基才DWT-DCT变换强鲁棒性的数字水印算法

提出一种基于DWT-DCT的新的数字图像水印算法。该算法充分利用离散小波变换多分辨率特性和离散余弦变换能量压缩特性．综合两种变换的优点。在嵌入时,先对宿主图像进行DWT变换,得到4个子带。选择HL子带进行DCT变换．然后将加密后的水印嵌入DCT变换后得到子带中频系数。为获得较强的安全性,在嵌入前先对水印进行混沌加密。试验结果表明基于DWT-DCT联合的水印算法具有较强的不可见性,对常见的攻击具有较强的鲁棒性。     

A direct digital frequency synthesizer based on ROM free algorithm

An ROM free quadrature direct digital frequency synthesizer (DDFS) was proposed in this paper. The proposed DDFS mainly consists of two adders and two multipliers to generate quadrature outputs. The proposed DDFS was implemented in both cell-base library and ALTERA Stratix EP1S40F780C5 FPGA board for verification.     

An optimal spectrum‐balancing algorithm for digital subscriber lines based on particle swarm optimization

This paper presents a new algorithm for optimal spectrum balancing in modern digital subscriber line (DSL) systems using particle swarm optimization (PSO). In DSL, crosstalk is one of the major performance bottlenecks, therefore various dynamic spectrum management algorithms have been proposed to reduce excess crosstalks among users by dynamically optimizing transmission power spectra. In fact, the objective function in the spectrum optimization problem is always nonconcave. PSO is a new evolution algorithm based on the movement and intelligence of swarms looking for the most fertile feeding location, which can solve discontinuous, nonconvex and nonlinear problems efficiently. The proposed algorithm optimizes the weighted rate sum. These weights allow the system operator to place differing qualities of service or importance levels on each user, which makes it possible for the system to avoid the selfish‐optimum. We can show that the proposed algorithm converges to the global optimal solutions. Simulation results demonstrate that our algorithm can guarantee fast convergence within a few iterations and solve the nonconvex optimization problems efficiently. Copyright © 2008 John Wiley & Sons, Ltd.     

An hybrid evolutionary multiobjective algorithm for multiuser margin maximization in DSL

This work describes and proposes the application of evolutionary algorithms on the multiuser spectrum and SNR margin optimization problem for multicarrier systems, such as digital subscriber line. The proposed method is designed such that it takes advantage of special characteristics of the well‐known power adaptation techniques and uses them to solve the broader and more challenging problem of multiuser margin adaptation. Simulations show that the proposed method provides Pareto‐optimal and diverse solutions when compared to a previous method to solve the same problem. Copyright © 2014 John Wiley & Sons, Ltd.     

基于非下采样剪切波变换和QR分解的鲁棒零水印算法

针对数字图像的版权保护问题,提出了一种基于非下采样剪切波变换(NSST,non-subsam-pled shearlet transform)和QR分解的零水印算法。首先,采用NSST对宿主图像进行分解;然后利用Logistic混沌系统从分解后的低频逼近分量中随机抽取出一幅子图,并将其分割成互不重叠的子块;最后对每一个子块进行QR分解,通过判断各个子块R矩阵中第1行元素向量的l1范数和所有子块R矩阵第1行元素向量l1范数的均值之间的大小关系构造零水印。实验结果表明,本文算法对添加噪声、滤波、JPEG压缩和剪切具有很强的鲁棒性,同时还能抵抗一定程度的旋转、缩放和平移(RST)几何攻击。     

CORDIC based fast algorithm for power-of-two point DCT and its efficient VLSI implementation

—In this paper, we present a coordinate rotation digital computer (CORDIC) based fast algorithm for power-of-two point DCT, and develop its corresponding efficient VLSI implementation. The proposed algorithm has some distinguish advantages, such as regular Cooley-Tukey FFT-like data flow, identical post-scaling factor, and arithmetic-sequence rotation angles. By using the trigonometric formula, the number of the CORDIC types is reduced dramatically. This leads to an efficient method for overcoming the problem that lack synchronization among the various rotation angles CORDICs. By fully reusing the uniform processing cell (PE), for 8-point DCT, only four carry save adders (CSAs)-based PEs with two different types are required. Compared with other known architectures, the proposed 8-point DCT architecture has higher modularity, lower hardware complexity, higher throughput and better synchronization.     

抗JPEG压缩攻击的DWT域图像量化水印算法

分析了DWT域系数对JPEG压缩的稳定性,在此基础提出了一种新的抗JPEG压缩攻击的DWT域图像量化水印算法。此算法在提取水印时无需原始图像。实验结果表明,该算法对嵌入的水印具有很好的透明性,对JPEG压缩攻击具有很强的鲁棒性,对其他常见的图像处理攻击,如亮度调整、对比度调整、加噪声、重采样、颜色抖动和平滑等,均具有很强的鲁棒性。     

High-linear,energy-efficient and area-efficient switching algorithm for high-speed SAR ADCs

Decreasing the size of DAC capacitors is a solution to achieve high-speed and low-power successive-approximation register analog-to-digital converters (SAR ADCs). But decreasing the size of capacitors directly effects the linearity performance of converter. In this paper, the effect of capacitor mismatch on linearity performance of charge redistribution SAR ADCs is studied. According to the achieved results from this investigation, a new tri-level switching algorithm is proposed to reduce the matching requirement for capacitors in SAR ADCs. The integral non-linearity (INL) and the differential non-linearity (DNL) of the proposed scheme are reduced by factor of two over the conventional SAR ADC which is the lowest compared to the previous schemes. In addition, the switching energy of the proposed scheme is reduced by 98.02% as compared with the conventional architecture which is the most energy-efficient algorithms in comparison with the previous algorithms, too. To evaluate the proposed method an 8-bit 50 MS/s SAR ADC is designed in 0.18 um CMOS process technology. According to the obtained simulation results, the designed ADC digitizes a 25-MHz input with 48.16 dB SNDR while consuming about 589 μW from a 1.2-V supply.