3.6 mw low power wireless RF receiver front end using creative current recycle technique

This paper presents the design of low noise amplifier and mixer (LIXER) circuit for wireless receiver front ends using 65 nm CMOS technology. The circuit is implemented with CMOS transistors and uses 65 nm CMOS process. Proposed LIXER circuit achieves a maximum gain of 25 dB and DSB noise figure of 3.5 dB. In the given circuit, current shunt paths had created by using LC tank circuit with transistors Q5 and Q6. By using the creative current recycle technique circuit consumes 3.6 mW power with 1.2 V power supply. The operating frequency of the proposed structure is 2.4 GHz with 25 dB conversion gain and ?13 dBm IIP3. The operating of the receiver front end is 2.4 GHz is used for IEEE 802.11a WLAN, Bluetooth, and ZigBee applications.     

Generation of square and triangular wave with independently controllable frequency and amplitude using OTAs only and its application in PWM

This paper presents a self-generating square/triangular wave generator using only the CMOS Operational Transconductance Amplifiers (OTAs) and a grounded capacitor. The output frequency and amplitude of the proposed circuit can be independently and electronically adjusted. The proposed circuit validates its advantage by consuming less amount of power, which is about 71.3 µW. The theoretical aspects are authentically showcased using the PSPICE simulation results. The performance of the proposed circuit is also verified through pre layout and post layout simulation results using the 90 nm GPDK CMOS parameters. A prototype of this circuit has been made using commercially available IC CA3080 for experimental verification. Experimentation also gives the similar output as per the theoretical proposition. The designed circuit is also made applicable to perform pulse width modulation (PWM).     

CMOS CCII– based on modified dual output-OTA for high frequency applications

A negative CMOS second generation current conveyor (CMOS CCII–) based on modified dual output CMOS folded cascode operational transconductance amplifier (CMOS DO-OTA) is presented. The proposed folded cascode CMOS DO-OTA with attractive features for high frequency operation such as high output impedance, wide bandwidth, high slew rate, with low power consumption is used in the realisation. The proposed CMOS DO-OTA and CMOS CCII– with high performance parameters can be used in many high frequency applications. The proposed CMOS CCII– achieves 1.37 GHz (?3 dB BW), 1.8 ns settling time, 48 V/μs slew rate, and low power consumption around 3.25 mW for ±2.5 V supply. P-Spice simulation results are included for 0.5 μm MIETEC CMOS technology.     

CMOS substrate coupling modeling and analysis flow for submicron SoC design

CMOS technology substrate crosstalk modeling and a respective analysis flow that captures the affected circuit performance is described. The proposed methodology can be seamlessly integrated into any industrial Analog/RF circuit design flow, and be compatible within standard design environments. It provides accurate estimation of the substrate coupling effects and can estimate adequately all the mask design level isolation performance trends by adapting an advanced substrate modeling concept based on geometrical and process data. Different substrate model accuracy constraints can be invoked depending on the design phase and the simulation time needs. The provided accuracy is validated by correlating simulation results versus on wafer silicon measurements in a 28 nm CMOS set of ring oscillators with carrier frequency of 670 MHz. The mean error of the proposed method is 665 μV while the error sigma is 765 μV.     

0.75 V supply nanowatt resistorless sub-bandgap curvature-compensated CMOS voltage reference

This work presents a resistorless self-biased and small area sub-bandgap voltage reference that works in the nano-ampere consumption range with 0.75 V of power supply. The circuit applies a curvature compensation technique that allows an extended temperature range without compromising the temperature stability. The behavior of the circuit is analytically described, and a design methodology is proposed which allows the separate adjustment of the bipolar junction transistor bias current and its curvature compensation. Simulation results are presented for a 180 nm CMOS process, where a reference voltage of 469 mV is designed, with a temperature coefficient of 5 ppm/°C for the ?40 to 125 °C extended temperature range. The power consumption of the whole circuit is 16.3 nW under a 0.75 V power supply at 27 °C. The estimated silicon area is 0.0053 mm².     

Instrumentation amplifier and current injection circuit design for input impedance boosting in biopotential and bioimpedance measurements

This paper describes an instrumentation amplifier (IA) architecture with a mechanism that generates negative capacitances at its input. Two 8-bit programmable capacitors between the input stage and the current feedback loop of the IA allow adaptive cancellation of the input capacitances from the electrode cables and printed circuit board. The proposed negative capacitance generation technique can improve the input impedance from a few megaohms to above 500 MΩ without significant impact on performance parameters such as the common-mode rejection ratio, power supply rejection ratio, total harmonic distortion, and noise. Furthermore, a current injection circuit is introduced for on-chip input impedance estimation. An operational transconductance amplifier and associated key design concepts are presented in this paper that achieve a transconductance of 25 pS and an output impedance above 4 GΩ. The IA and the test current generator were designed and simulated using 0.13 µm CMOS technology.     

Equivalent circuit models in current-mode circuits for time delay calculations

In this paper time delay calculations for current-mode circuits are considered and equivalent circuit models for delay estimation are developed. Three different equivalent circuit structures for the Core Circuit used in the multipurpose IC DU-TCC1209 are examined separately; however the relation obtained for the time delay can be applied to any CMOS current-mode circuit. The proposed calculation methods are verified with SPICE using 0.35 μm TSMC MOSIS technology parameters and with bench-test measurements using DU-TCC1209.     

A 10-Transistor 65 nm SRAM Cell Tolerant to Single-Event Upsets

A novel SRAM cell tolerant to single-event upsets (SEUs) is presented in this paper. By adding four more transistors inside, the proposed circuit can obtain higher critical charge at each internal node compared to the conventional 6-transistor (6T) cell. Arrays of 2k-bit capacitance of these two designs were implemented in a 65 nm CMOS bulk technology for comparison purpose. Radiation experiments showed that, at the nominal 1.0 V supply voltage, the proposed cell achieves 47.1 % and 49.3 % reduction in alpha and proton soft error rates (SER) with an area overhead of 37 %.     

A New Capacitance-to-Frequency Converter for On-Chip Capacitance Measurement and Calibration in CMOS Technology

In this paper, a new capacitance-to-frequency converter using a charge-based capacitance measurement (CBCM) circuit is proposed for on-chip capacitance measurement and calibration. As compared to conventional capacitor measurement circuits, the proposed technique is able to represent the capacitance in term of the frequency so that the variations can be easily handled in measurement or calibration circuits. Due to its simplicity, the proposed technique is able to achieve high accuracy and flexibility with small silicon area. Designed using standard 180 nm CMOS technology, the core circuit occupies less than 50 μm × 50 μm while consuming less than 60 μW at an input frequency of 10 MHz. Post-layout simulation shows that the circuit exhibits less than 3 % measurement errors for fF to pF capacitances while the functionality has been significantly improved.     

Area efficient layout design of CMOS circuit for high-density ICs

Efficient layouts have been an active area of research to accommodate the greater number of devices fabricated on a given chip area. In this work a new layout of CMOS circuit is proposed, with an aim to improve its electrical performance and reduce the chip area consumed. The study shows that the design of CMOS circuit and SRAM cells comprising tapered body reduced source fully depleted silicon on insulator (TBRS FD-SOI)-based n- and p-type MOS devices. The proposed TBRS FD-SOI n- and p-MOSFET exhibits lower sub-threshold slope and higher I_on to I_off ratio when compared with FD-SOI MOSFET and FinFET technology. Other parameters like power dissipation, delay time and signal-to-noise margin of CMOS inverter circuits show improvement when compared with available inverter designs. The above device design is used in 6-T SRAM cell so as to see the effect of proposed layout on high density integrated circuits (ICs). The SNM obtained from the proposed SRAM cell is 565 mV which is much better than any other SRAM cell designed at 50 nm gate length MOS device. The Sentaurus TCAD device simulator is used to design the proposed MOS structure.     

An OTA gain enhancement technique for low power biomedical applications

The performance requirement of an operational trans-conductance amplifier (OTA) for the high gain and low power neural recording frontend has been addressed in this paper. A novel split differential pair technique is proposed to improve the gain of the OTA without any additional bias current requirements. The design demonstrates a significant performance enhancement when compared to existing techniques, such as gain-boosting and recycling. A qualitative and quantitative treatment is presented to explore the impact of the split ratio on the performance parameters of gain, bandwidth, and linearity. A prototype implemented in TSMC 65 nm CMOS technology achieved 68 dB open loop-gain (13 dB higher than the conventional circuit) and a 17 kHz 3-dB bandwidth. A linearity of ? 62 dB has been achieved with 7 mV pk–pk signal at the input. The circuit operates from a 1 V supply and draws 0.6 uA static current. The prototype occupies 3300 um² silicon area.     

A CMOS current-mode log(x) and log(1/x) functions generator

A novel Complementary Metal Oxide Semiconductor (CMOS) current-mode low-voltage and low-power controllable logarithmic function circuit is presented. The proposed design utilises one Operational Transconductance Amplifier (OTA) and two PMOS transistors biased in weak inversion region. The proposed design provides high dynamic range, controllable amplitude, high accuracy and is insensitive to temperature variations. The circuit operates on a ±0.6 V power supply and consumes 0.3 μW. The functionality of the proposed circuit was verified using HSPICE with 0.35 μm 2P4M CMOS process technology.     

Frequency multiplier using pulse-width control loop

A frequency multiplier circuit based on a well-known pulse-width control loop is presented. The proposed circuit can be used to enhance the output frequency range of a phase-locked loop (PLL) by using multiple phases of the voltage-controlled oscillator. It can be used for enhancing the output frequency range of new as well as existing PLL designs with minimum impact on PLL loop dynamics. The circuit is generic in nature and can be used with any multi-phase oscillator type. The circuit is designed in 65 nm complimentary metal oxide semiconductor (CMOS) technology and has been simulated across process, voltage and temperature (PVT) corners with temperature variation from ?40°C to 125°C, analogue supply voltage variation from 1.62 V to 1.98 V, and digital supply voltage variation from 1.1 V to 1.3 V.     

A 20 Gbps inductorless CMOS optical receiver for short-distance VCSEL-based 850 nm optical links

This paper presents a circuit design and experimental results for a 20 Gbps CMOS inductorless optical receiver, a transimpedance amplifier (TIA) and a limiting amplifier, for a vertical-cavity surface emitting laser based 850 nm optical link. The proposed optical receiver apply a power supply noise canceling technique, an additional path from the power supply to the TIA output to generate a reversed phase signal that reduces the power supply noise, and bandwidth enhancement circuit design that dose not require internal inductors. The simulation results shows a power supply rejection ratio of ?96.6 dB at 10 MHz, a total gain of $82.8\,\hbox{dB}\Upomega$ and a ?3 dB bandwidth of 15.5 GHz. A test chip fabricated in 90 nm CMOS technology and demonstrated with a PIN photo-diode, a bandwidth of 17 GHz and a responsibility of 0.53 A/W. The measurement results show a 25 % eye opening and an input sensitivity of ?7.1 dBm at a bit error rate of 10^?12 with a 2⁹ ? 1 pseudo-random test pattern at 20 Gbps. The core circuit of the optical receiver occupies only an area of 0.02 mm².     

A novel VLSI design of radix-4 DFT in current mode

Discrete-time Fourier transform (DFT) is viewed as an important tool in discrete time signal processing. Applications in wireless communication such as OFDM uses DFT/IDFT in its receiver and transmitter. For small battery powered wireless devices, discrete time analogue DFT can be very useful as a low-energy front-end. The quest for a reduction in the effect due to the mismatch of transistors lead to higher radix structure. It becomes very challenging for the designer to build an analogue circuit for implementation of DFT with radix sizes 4, 8, and so on. This is mainly because of hand calculation of circuit-level equations from butterfly algorithm becomes a long process. Thus, a design methodology becomes a necessary option in this regard. Here an algorithm is proposed for the generation of circuit-level equations leading to signal routing table for the circuit of basic radix-4 FFT. Following that algorithm, a current mode all analogue circuit with cascode current mirror is proposed. Simulations are carried out in SPICE using BSIM4 65 nm CMOS process. A mismatch noise model is also made to show the reduction in error with higher radix structure. The non-ideal effects due to mismatch in V_th are analysed through Monte-Carlo simulation.     

A New Linearized CCII-Based Fully Differential CMOS Transconductor Used for \hbox {G}_\mathrm{m}-C Active Filters Implementation

The paper presents a new linearized, of high performance, fully differential transconductor, based on class AB second generation current conveyor (CCII) in CMOS technology. The proposed circuit is composed by two positive CCII cells connected in series and a common mode feedback loop. Unlike other CMOS circuits on the basis of CCII reported in the literature, the proposed transconductor cell allows to obtain a higher transconductance value, an improved linearity and operates at high frequency for a 3.3 V supply voltage. As an application, the new transconductor cell in CMOS technology is used for designing a 4th order differential $\hbox {G}_\mathrm{m}$ -C low-pass filters in different approximations (Butterworth and Chebyshev) operating up to 300 MHz cut-off frequency. The simulations performed in 130 nm CMOS process confirm the theoretical results.     

Ultra-low power FinFET-based domino circuits

Aggressive scaling of single-gate CMOS device face greater challenge in nanometre technology as sub-threshold and gate-oxide leakage currents increase exponentially with reduction of channel length. This paper discusses a double-gate FinFET (DGFET) technology which mitigates leakage current and higher ON state current when scaling is done beyond 32 nm. Here 8 and 16 input OR gate domino logic circuits are simulated on 32 nm FinFET Predictive technology model (PTM) on HSPICE. Simulation results of different 8 input OR gate domino logic circuits like Current-mirror footed domino (CMFD), High-speed clock-delayed (HSCD), Modified-HSCD (M-HSCD), Conditional evaluation domino logic (CEDL) and Conditional stacked keeper domino logic (CSK-DL), all operated in Short Gate (SG) and Low Power (LP) mode, shows tremendous reduction in average power consumption and delay. In this paper, domino logic-based circuit Ultra-Low Power Stack Dual-Phase Clock (ULPS-DPC) is proposed for both CMOS and FinFET (SG and LP modes). Proposed circuit shows maximum reduction in average power consumption of 84.04% when compared with CSK-DL circuit and maximum reduction in delay of 75.4% when compared with M-HSCD circuit at 10 MHz frequency when these circuits are simulated in SG mode.     

红外焦平面阵列非均匀性的校正方法研究

针对读出电路与探测器产生的非均匀性,并对递归最小二乘非均匀校正算法(RLS算法)进行扩展和改进,提高非均匀校正的精度和算法的收敛速度。首先对红外焦平面阵列的非均匀性进行建模仿真,根据建立的模型利用局部恒定统计法对读出电路产生的非均匀性进行校正,然后采用自适应中值滤波算法(RAMF算法)对图像进行预处理,从而提供给后续RLS算法具有较低噪声的图像,实现RLS算法对探测器的非均匀性校正。仿真结果表明提出的算法能够有效地抑制读出电路对校正精度的影响,消除图像的非均匀性,同时采用RAMF算法对图像的预处理过程,能够加快RLS算法的收敛速度,提高信噪比,获得较好的非均匀性校正效果。     

A very high performance self-biased cascode current mirror for CMOS technology

This paper presents a novel high performance self-biased cascode current mirror (CM) for CMOS technology. The proposed circuit shows a resistance compensated high bandwidth CM operating at low voltages. This circuit uses super cascode configuration to obtain high output impedance required for high performance of CM. Active implementation of passive resistances of the proposed circuit is shown. The simulations of proposed CM are carried out by Mentor Graphics Eldospice based on TSMC 0.18 μm CMOS technology, for input current range of 0–500 μA. A bandwidth of 2.26 GHz, input and output resistances of 679 Ω and 482 MΩ respectively, are obtained with a single supply voltage of ?1 V.     

CMOS design of a four-quadrant multiplier based on a novel squarer circuit

In this paper a CMOS current-mode analog multiplier circuit based on a novel current-mode squarer circuit is proposed. The circuit is simulated using HSPICE simulator and designed in 0.35 µm standard CMOS technology with ± 1.5 V supply voltage. The simulation results of proposed multiplier for input current range of ±10 μA demonstrate a ?3 dB bandwidth of 24.5 MHz, 475 μW as maximum power consumption, nonlinearity of 1.3 % and a THD of 0.87 % at 1 MHz.