一种基于BSIM-CMG的FinFET变容管模型

提出了一种适用于FinFET变容管的建模方法.在BSIM-CMG的基础上,模型采用衬底模型和外围寄生模型来表征变容管的射频寄生效应.提出了具体的参数提取方法,将测试的S参数导入到安捷伦IC-CAP建模软件提取参数,测试结构引入高频寄生采用(open+ short)去嵌方法进行去嵌.通过调节模型参数拟合测试曲线得到FinFET变容管模型.该模型可精确表述FinFET变容管全工作区域特性,解决传统MOS变容管模型无法准确描述三维FinFET器件变容特性的问题.模型和模型参数提取方法采用20个硅鳍、16个栅指、158 nm栅长、578 nm栅宽的FinFET变容管进行建模验证,模型仿真和测试所得C-V,R-V和S参数特性吻合良好.     

基于单纯形射线追踪法的研究

单纯形射线追踪相比传统的射线追踪不需要对射线和多面体面做相交测试,从而算法的效率得到了提高,本文改进了射线接受方法,并对一个室内超宽带的信道模型进行了仿真,仿真结果验证了该方法的有效性。     

一种新型高性能FinFET的设计与特性分析

针对CMOS器件随着技术节点的不断减小而产生的短沟道效应和漏电流较大等问题,设计了一种新型直肠形鳍式场效应晶体管(FinFET),并将该新型器件与传统的矩形结构和梯形结构的FinFET通过Sentaurus TCAD仿真软件进行对比。结果表明,当栅极长度控制在10 nm时,新型器件相比于另外两种传统的FinFET具有更小的鳍片尺寸,且鳍片高度不低于抑制短沟道效应的临界值。仿真结果显示,这种新型的FinFET具有更好的开关特性和亚阈值特性。同时,该器件在射频方面的特性参数也显示出该器件具有较高性能,并有一定的实际应用价值。     

表面光电压技术在Si外延过程中的应用

介绍了用表面光电压(SPV)法测试少数载流子的扩散长度、少子寿命和体Fe含量的基本原理及其计算方法,分析了三种常见外延结构中少子扩散长度的测试方法及其影响因素,得出了用于表面光电压测试的外延片及衬底片应满足的条件。提出了在外延工艺前后,用SPV法测试同一p型控片中少子的扩散长度和体Fe含量,对比前后值的大小来监测Si外延工艺过程中的沾污情况。分别给出了衬底片、石墨基座、HCl、SiHCl3、外延腔体等5种Si外延过程中最常见沾污源的监控和识别流程,特别以平板式外延腔体为例,具体说明了识别及排除Fe沾污所运行的工艺程序,并对Fe沾污的测试结果进行了分析,确定了Fe沾污的来源。     

蓝宝石/SiO_2/AlN/GaN多层结构表面热应力仿真分析

为了研究蓝宝石/SiO_2/AlN/GaN光阴极组件外延片热应力分布及影响因素,以直径d为φ40 mm的GaN外延片为研究对象,利用有限元分析法对其表面热应力分布进行了理论计算和仿真,验证了仿真模型的合理性。分析了外延片径向和厚度方向的应力分布,结果显示:在1200℃的生长温度下,径向区域内的热应力分布比较均匀,热应力变化范围为±1.38%;生长温度在400℃到1200℃范围内,外延层表面应力与生长温度呈近似正比关系。分析了外延片生长温度、蓝宝石衬底和SiO_2、AlN过渡层厚度对表面热应力的影响。研究成果可为该类外延片生长工艺研究和低应力外延片的筛选标准制定提供借鉴。     

微波电路通孔结构的改进型矩阵束矩量法仿真

对多层微波电路通孔结构进行RWG片元建模,用矩量法求解通孔表面电流,并运用矩阵束方法提取通孔外部结构相关参数,进一步得到20GHz以内散射参数。为提高求解速度,应用了等效介电常数和高效的矢量化运算,大幅度地提高了算法的效率。通过与全波仿真软件HFSS对比,验证了算法的正确性和高效率。另外加工了一套电路板进行实验测试,实测结果与本文算法计算基本吻合,说明了算法的可靠性。     

14 nm FinFET栅围寄生电容的建模与拟合

提出了一种基于保角映射方法的14 nm鳍式场效应晶体管(FinFET)器件栅围寄生电容建模的方法。对FinFET器件按三维几何结构划分寄生电容的种类,再借助坐标变换推导出等效电容计算模型,准确表征了不同鳍宽、鳍高、栅高和层间介质材料等因素对寄生电容的依赖关系。为了验证该寄生电容模型的准确性,对不同结构参数的寄生电容进行三维TCAD仿真。结果表明,模型计算结果与仿真结果的拟合度好,准确地反映了器件结构与寄生电容之间的依赖关系。     

SiGe HBT非准静态小信号等效电路的参数提取

提出了一种硅锗异质结双极型晶体管（SiGe HBT）非准静态效应的小信号等效电路模型的参数提取方法。整个参数提取过程建立在由非准态效应的小信号等效电路推导出的一系列泰勒级数解析公式并结合参数直接法,该方法依赖于测量的S参数,不使用任何的数值优化法,参数提取结果使用CAD仿真验证。结果表明该参数提取方法简单易行,较为精确,该方法能够用到不同工艺SiGe HBT参数提取。     

金属功函数波动效应快速预测方法及验证

金属功函数波动作为器件制造过程中的主要工艺波动源之一,其波动变化对器件电学特性有极大的影响。本文提出一种简便、快速预测半导体场效应管金属功函数波动效应的方法,并将其与商业软件中计算功函数波动的统计阻抗场法进行对比分析。参考IBM公司发布的14 nm SOI FinFET结构建立FinFET器件仿真模型并与实验数据对比验证后,引入金属功函数波动,分别用统计阻抗场法与本文提出的快速预测方法计算得到对应随机波动下模型的阈值电压V_th、关断电流I_off、工作电流I_on等电学特性参数的随机分布及这些参数结果的期望值、标准差、极差等统计参数,通过两者结果对比验证了快速预测方法的准确性。     

一种低噪声SiGe微波单片放大电路

介绍了一种利用SiGe技术制作的低噪声SiGe微波单片放大电路(MMIC)。该电路以达林顿结构的形式级联,由两个异质结双极型晶体管(HBT)和4个电阻组成;HBT采用准自对准结构,其SiGe基区为非选择性外延。在1 GHz频率下,电路噪声为1.59 dB,功率增益为14.3 dB,输入驻波比为1.6,输出驻波比为2.0。     

Strained p-Channel FinFETs With Extended Π -Shaped Silicon–Germanium Source and Drain Stressors

Further enhancement of performance in a strained p-channel multiple-gate or fin field-effect transistor (FinFET) device is demonstrated by utilizing an extended-Pi-shaped SiGe source/drain (S/D) stressor compared to that utilizing only Pi-shaped SiGe S/D. With the usage of a longer hydrofluoric acid cleaning time prior to the selective-epitaxy-raised S/D growth, a recess in the buried oxide is formed. This recess allows the subsequent SiGe growth on the fin sidewalls of the S/D regions to extend into the recessed buried oxide to provide a larger compressive stress in the channel for enhanced electrical performance compared to a device with SiGe S/D stressor. Process simulation shows that longitudinal compressive stress in the channel region is higher in a FinFET with extended-Pi-SiGe S/D than that with Pi-SiGe S/D. An enhancement of 26% in the drive current was experimentally observed, demonstrating further boost in enhancement of strained p-channel FinFET with little additional cost using this novel process.     

Impact of Channel,Stress-Relaxed Buffer,and S/D Si<Subscript>1−<Emphasis Type="Italic">x</Emphasis></Subscript>Ge<Subscript><Emphasis Type="Italic">x</Emphasis></Subscript> Stressor on the Performance of 7-nm FinFET CMOS Design with the Implementation of Stress Engineering

Stress-engineered fin-shaped field effect transistors (FinFET) using germanium (Ge) is a promising performance booster to replace silicon (Si) due to its high holes mobility. This paper presents a three-dimensional simulation by the Sentaurus technology computer-aided design to study the effects of stressors—channel stress, stress-relaxed buffer (SRB), and source/drain (S/D) epitaxial stress—on different bases of FinFET, specifically silicon germanium (SiGe) and Ge-based, whereby the latter is achieved by manipulating the Ge mole fraction inside the three layers; their effects on the devices’ figures-of-merits were recorded. The simulation generates an advanced calibration process, by which the drift diffusion simulation was adopted for ballistic transport effects. The results show that current enhancement in p-type FinFET (p-FinFET) with 110% is almost twice that in n-type FinFET (n-FinFET) with 57%, with increasing strain inside the channel suggesting that the use of strain is more effective for holes. In SiGe-based n-FinFET, the use of a high-strained SRB layer can improve the drive current up to 112%, while the high-strain S/D epitaxial for Ge-based p-FinFET can enhance the on-state current to 262%. Further investigations show that the channel and S/D doping are affecting the performances of SiGe-based FinFET with similar importance. It is observed that doping concentrations play an important role in threshold voltage adjustment as well as in drive current and subthreshold leakage improvements.     

SiGe source/drain structure for the suppression of theshort-channel effect of sub-0.1-μm p-channel MOSFETs

A bandgap engineering technique is proposed for the suppression of the short-channel effect (SCE) and its effectiveness is quantitatively calculated in the case of the SiGe source/drain structure with a device simulation. The drain-induced barrier lowering (DIBL) and the charge sharing are suppressed by the presence of the valence band discontinuity between the SiGe source/drain and Si channel. In order to obtain the full advantage of this structure, it is necessary to locate the SiGe layers both at the source/drain regions and the SiSe/Si interface at the pn junction or inside the channel region. The effectiveness increases with the increase of the valence band discontinuity (Ge concentration). As a result of the suppression of the SCE and the reduction of the minimum gate length, the drain current increases, and thus high-speed operation can be realized with this technique     

Strained ${rm n}$-MOSFET With Embedded Source/Drain Stressors and Strain-Transfer Structure (STS) for Enhanced Transistor Performance

A novel-channel MOS transistor with a silicon-germanium (SiGe) heterostructure embedded beneath the channel and silicon-carbon source/drain (Si:C S/D) stressors was demonstrated. The additional SiGe structure couples additional strain from the S/D stressors to the overlying Si channel, leading to enhanced strain effects in the channel region. We termed the SiGe region a strain-transfer structure due to its role in enhancing the transfer of strain from lattice-mismatched S/D stressors to the channel region. Numerical simulations were performed using the finite-element method to explain the strain-transfer mechanism. A significant drive current I_DSAT improvement of 40% was achieved over the unstrained control devices, which is predominantly due to the strain-induced mobility enhancement. In addition, the impact of scaling the device design parameters on transistor drive current performance was investigated. Guidelines on further performance optimization in such a new device structure are provided.     

应变硅pMOS晶体管沟道应变的有限元研究

通过有限元方法,研究了一种采用SiGe源漏结构的pMOS晶体管中硅沟道的应变及其分布情况,模拟计算结果与利用会聚束电子衍射方法测量得到的数据能够较好地吻合,验证了模拟模型及方法的正确性。结果表明:提高源漏SiGe中的Ge组分、减小源漏间距、增加源漏的刻蚀深度和抬高高度,能有效增加沟道的应变量,为通过控制应变改善载流子迁移率提供了设计依据。     

Spacer-First Damascene-Gate FinFET Architecture Featuring Stringer-Free Integration

This letter presents a new Damascene-gate FinFET process that inherently suppresses stringers, resulting from gate and spacers patterning. The so-called spacer-first integration scheme relies on the engineering of a hydrogen silsesquioxane layer by electron beam lithography followed by two selective compartmentalized development steps to successively release the Damascene-gate cavity and the source/drain (S/D) contact regions. In contrast to the existing gate-first and gate-last integration approaches, the resulting FinFET process does not impose any restriction or interdependency on the sizing of the fins, gate, spacers, and S/D regions. A complete morphological and electrical validation is proposed in the particular case of wrap-around self-aligned metallic Schottky S/D contacts.     

Suppression of the floating-body effect in partially-depleted SOIMOSFETs with SiGe source structure and its mechanism

SiGe layers were formed in source regions of partially-depleted 0.25-μm SOI MOSFETs by Ge implantation, and the floating-body effect was investigated for this SiGe source structure. It is found that the increase of the Ge implantation dosage suppresses kinks in I_d-V_d characteristics and that the kinks disappear for devices with a Ge dose of 3×10¹⁶ cm^-2. The lowering of the drain breakdown voltage and the anomalous decrease of the subthreshold swing are also suppressed with this structure. It is confirmed that this suppression effect originates from the decrease of the current gain for source/channel/drain lateral bipolar transistors (LBJTs) with the SiGe source structure. The temperature dependence of the base current indicates that the decrease of the current gain is ascribed to the bandgap narrowing of the source region     

Source/drain optimization of underlapped lightly doped nanoscale double-gate MOSFETs

The impact of the spacer length at the source (L_s) and drain (L_d) on the performance of symmetrical lightly-doped double-gate (DG) MOSFET with gate length L = 20 nm is analyzed, with the type and doping concentration of the spacers kept the same as in the channel material. Using the transport parameters extracted from experimental data of a double-gate FinFET, simulations were performed for optimization of the underlapped gate-source/drain structure. The simulation results show that the subthreshold leakage current is significantly suppressed without sacrificing the on-state current for devices designed with asymmetrical source/drain extension regions, satisfying the relations L_s = L/2 and L_d = L. In independent drive configuration, the top-gate response can be altered by application of a control voltage on the bottom-gate. In devices with asymmetrical source/drain extension regions, simulations demonstrate that the threshold voltage controllability is improved when the drain extension region length is increased.     

New Observations in LOD Effect of 45-nm P-MOSFETs With Strained SiGe Source/Drain and Dummy Gate

Length of thin oxide definition area (LOD) effects and the incorporation of the dummy poly gates on the performance of 45-nm P-MOSFETs with and without strained SiGe source/drain (S/D) are systematically investigated. In the non-SiGe devices, the LOD effect is dominated by the STI stress and shows a little dependence of dummy poly gates. However, in the SiGe device, the LOD effect is strongly dependent on the location of the dummy poly gate. For dummy poly gate located outside the active area, the compressive stress from the SiGe S/D dominates the LOD effect, but for dummy poly gate located within the active area, the LOD effect is controlled by both the SiGe S/D stress within the dummy gate and the STI stress. The mechanisms of our new observations are analyzed with TCAD simulations.      

Quantum mechanical analytical modeling of nanoscale DG FinFET: evaluation of potential,threshold voltage and source/drain resistance

Two-dimensional (2D) quantum mechanical analytical modeling has been presented in order to evaluate the 2D potential profile within the active area of FinFET structure. Various potential profiles such as surface, back to front gate and source to drain potential have been presented in order to appreciate the usefulness of the device for circuit simulation purposes. As we move from source end of the gate to the drain end of the gate, there is substantial increase in the potential at any point in the channel. This is attributed to the increased value of longitudinal electric field at the drain end on application of a drain to source voltage. Further, in this paper, the detailed study of threshold voltage and its variation with the process parameters are presented. A threshold voltage roll-off with fin thickness is observed for both theoretical and experimental results. The fin thickness is varied from 10 nm to 60 nm. The percentage roll-off for our model is 77% and that for experimental result it is 75%. Form the analysis of source/drain (S/D) resistance, it is observed that for a fixed fin width, as the channel length increases, there is an enhancement in the parasitic S/D resistance. This can be inferred from the fact that as the channel length decreases, quantum confinement along the S/D direction becomes more extensive. For our proposed devices a close match is obtained with the results through the analytical model and reported experimental results, thereby validating our proposed QM analytical model for DG FinFET device.