Three-dimensional simulation of the conformality of copper layers deposited by low-pressure chemical vapor deposition from Cu(tmvs)(hfac)

In this paper, an approach is presented which is suitable for predicting the shape of copper layers deposited by low-pressure chemical vapor deposition (LPCVD) on three-dimensional (3D) features as used in semiconductor technology. The 3D simulations are based on a physical model assuming reactive molecules arriving at the substrate. These molecules react with a certain probability, the so-called sticking coefficient. In order to be able to predict the topography of the deposited layers, the sticking coefficient has to be determined for the set of process conditions under investigation. In this work, values for copper LPCVD from the literature were used, which were obtained by comparing 2D simulations to 2D measurements. As a result of the 3D simulations, the step coverage for contact holes of different aspect ratios is predicted. The simulator used does not make any restriction concerning the shape of the feature to be simulated. As an example, copper deposition into a dual-damascene structure is investigated by means of 3D simulation.     

Complete transient simulation of flash EEPROM devices

A two-dimensional device simulator which allows the complete transient simulation of nonvolatile memories is presented. The simulator has been derived from HFIELDS and incorporates models to account for Fowler-Nordheim tunneling, hot electron injection through silicon dioxide, and band-to-band tunneling in silicon. The physical models have been verified by comparing simulations with measurements performed on suitable test structures where good agreement has been obtained. The tool has been used to investigate flash EEPROM device scaling and to evaluate a published scaling scenario     

Plane Wave and Gaussian Beam Scattering by Long Dielectric Cylinders: 2.5D Simulations versus Measurements

For the development of millimeter wave imaging systems, it is important to be able to simulate some representative scattering configurations. Typically, Gaussian beams are used in active imaging systems. Since these beams only illuminate a spatially limited region, many objects can be treated as infinitely long 2D (in)homogenous cylinders. However, the incident Gaussian beams have a 3D character. Therefore, a dedicated 2.5D scattering simulator was developed. In this paper, simulation results obtained with this simulator are compared to measurements obtained from a bi-static microwave set-up and from a W-band millimeter wave set-up. Comparison of simulations and measurements proves that the 2.5D algorithm is a good simulation tool to study scattering of long inhomogeneous cylinders, illuminated by 3D plane waves or 3D Gaussian beams under different elevation angles.     

Circuit-level simulation of TDDB failure in digital CMOS circuits

An efficient circuit-level simulator for the prediction of time-dependent dielectric breakdown effects in digital CMOS circuits has been developed and integrated into the reliability simulation tool BERT (Berkeley Reliability Tools). The new module enhances the capability of the earlier SPICE-based oxide breakdown simulator by enabling practical simulations of large digital circuits. We discuss burn-in simulation for digital circuits and show that a significant reduction in oxide breakdown failure probability is possible     

Electrothermal simulation and design of integrated circuits

An accurate prediction of the electrothermal behavior of power integrated devices is required to design circuits in an efficient way. An electrothermal simulator (ETS) is a combination of SPICE with finite element code, in a relaxation procedure. It simulates the full electrothermal behavior of integrated circuits. Static and dynamic simulations of typical examples, reveal the value of ETS for high-power applications. Some specific design rules are derived. They are simple formulas, which estimate the temperature (gradients) on chip. They can be used before any CPU-time consuming simulation takes place which allows a more efficient design and prototype phase     

Dry etching topography simulator with a new surface reaction model:MODERN

A new simulator for dry-etching has been developed to predict topological evolutions in geometries with submicrometer dimensions. Ever-changing adsorbed particle layers on the film surface being etched are modeled. Surface reaction rates are calculated by taking into account the interaction between incoming ion/radical fluxes and the adsorbed particle layer with finite surface coverage. Silicon-dioxide etching by hydrofluorocarbon gases is studied as an application. Unknown parameters of ion/radical fluxes, radical sticking coefficients and sputtering rate of deposited polymer film are partially determined a priori based on a profile fitting method between simulations and experiments by using an overhang test structure. Simulation results of surface profiles after etching show good match with experimental data for trench and hole configurations, where the competition between etching and deposition on the sidewall are reasonably well described     

Development of a specimen heating holder with an evaporator and gas injector and its application for catalyst

A specimen heating holder equipped with a gas injector and an evaporator has been developed for use with conventional transmission electron microscopes (TEMs). The developed specimen holder allows both synthesis of metal oxide support and deposition of catalyst nano-particles in situ. Since the holder is designed to be used in small gapped high-resolution objective lens pole-piece, all the procedure from the synthesis of support material to the deposition of catalyst as well as the behavior of the catalyst nano-particles on the support can be observed at near atomic resolution. The developed specimen holder was applied to the study of AuPd catalyst. First, air was injected onto heated aluminum particles via a gas injector to synthesize Al(2)O(3) support. Then, nano-particles of AuPd were deposited on the Al(2)O(3) support. After the deposition, the synthesized Al(2)O(3) support was heated and air was injected again to observe behaviors of the deposited AuPd nano-particles at elevated temperatures in the aerial environment. Behaviors of the AuPd nano-particles such as coalescence, segmentation and diffusion to the Al(2)O(3) support were dynamically observed at atomic level high resolution.     

New plating bath for electroless copper deposition on sputtered barrier layers

A new copper plating bath for electroless deposition directly on conductive copper-diffusion barrier layers has been developed. This plating bath can be operated at temperatures between 20 and 50°C and has good stability. High temperature processing allows for increased deposition rates and decreased specific resistivity values for the deposited copper films. Electroless Cu films deposited from this bath showed a conformal step coverage in high aspect ratio trenches and, therefore, are promising as seed layers for copper electroplating. The effect of the bath composition, activation procedure and processing temperature on the plating rate and morphology of the deposited copper has been studied and is presented here.     

Analysis of Threshold Voltage Distribution Due to Random Dopants: A 100 000-Sample 3-D Simulation Study

Using the Glasgow ldquoatomisticrdquo simulator, we have performed 3D statistical simulations of random-dopant-induced threshold voltage variation in state-of-the-art 35- and 13-nm bulk MOSFETs consisting of statistical samples of 10⁵ or more microscopically different transistors. Simulation on such an unprecedented scale has been enabled by grid technology, which allows the distribution and the monitoring of very large ensembles on heterogeneous computational grids, as well as the automated handling of large amounts of output data. The results of these simulations show a pronounced asymmetry in the distribution of the MOSFET threshold voltages, which increases with transistor scaling. A comprehensive statistical analysis enabled by the large sample size reveals the origin of this observed asymmetry, provides a detailed insight into the underlying physical processes, and enables the statistical enhancement of simulations of random-dopant-induced threshold voltage variation.     

Thin-film silicon formation on foreign substrates by rapid thermal chemical vapour deposition for photovoltaic application

Polycrystalline silicon thin-film layers were deposited on foreign substrates such as SiO₂, alumina, mullite and graphite. The deposition studies were carried out in a single-wafer, horizontal, rapid thermal chemical vapour phase reactor at temperatures ranging from 900°C to 1250°C at atmospheric pressure. We employed the gas precursor trichlorosilane and the layers were doped with boron from the dopant source trichloroborine rarified in a hydrogen carrier gas. The surface structures and grain sizes of the thin films obtained were evaluated by Nomarski microscopy and scanning electron microscopy characterization methods. X-ray diffraction analyses were used to determine the preferential crystalline orientations at various operational parameters. Furthermore, electrical properties in terms of Hall mobility and lifetimes of the minority carriers were investigated by means of Van-der-Pauw and photoconductivity decay methods, respectively. Generally, it has been shown that at elevated deposition temperatures maximum grain sizes of 3–20 μm for 10-μm thick layers can be found, depending critically on the type of the substrate. For polycrystalline silicon deposited at 1100°C on silicon dioxide, alumina, and graphite substrates, a preferred crystallographic orientation of (220) was observed, implying columnar grain structures. © 1998 John Wiley & Sons, Ltd.     

Structural and electrical properties of polycrystalline silicon films deposited by low pressure chemical vapor deposition with and without plasma enhancement

Silicon thin films prepared by chemical vapor deposition of silane at very low pressures (4 mTorr) in an experimental reactor that allows deposition with and without plasma enhancement have been characterized. The temperature range of the substrates on which the films were deposited was varied from 500 to 800° C for plasma-enhanced depositions and 600 to 800° C for nonplasma depositions. Conductivity measurements as a function of temperature as well as average grain size and crystallographic texture measurements were performed. The results indicate that the films deposited with the assistance of a plasma were amorphous at deposition temperatures of 650° C and below and polycrystalline at deposition temperatures of 700° C and above. In the temperature regime investigated, this amorphous-to-crystalline transition was not observed in films deposited without the assistance of a plasma. Furthermore, all the films deposited at temperatures of 650° C and below have been found to have significantly different properties from the similarly prepared films deposited at higher temperatures.     

Simulation techniques for mixed analog/digital circuits

The techniques used in the iSPLICE3 simulator for the analysis of mixed analog/digital circuits are described. iSPLICE3 combines circuit, switch-level timing, and logic simulation modes and uses event driven selective-trace techniques. It also uses a hierarchical schematic capture package called iSPI (Simulation Program Interface) for design entry, circuit partitioning, and simulation control. The contributions here include a new DC solution method, a mixed-mode interface modeling technique, and an automatic partitioning approach for MOS logic circuits. The details of these three methods are provided, along with the architecture and transient simulation algorithms used in iSPLICE3. The results of circuit simulations and mixed-mode simulations of a CMOS static RAM, two A/D converters, and a phase-locked loop are presented. These results indicate that iSPLICE3 is between one and two orders of magnitude faster than SPICE2 with negligible loss in accuracy     

Study of oriented growth of oligofluorene–thiophene films onto aligned vacuum-deposited polytetrafluoroethylene layers

An analysis of a vacuum-deposited fluorene-thiophene-based material 5,5′-Di(9,9′-di-(butyl)-fluorene-2,2′-bithiophene) (DBFBT) onto different substrates, which can act as dielectric gate for organic field-effect transistor is made. Also a new method for preparation of high-quality dielectric thin films made of polytetrafluoroethylene (PTFE) is described. This method includes film formation by means of a special kind of vacuum deposition polymerization (VDP) of PTFE, assisted by electron cloud activation. Rubbing of these layers makes them orienting substrate materials which induce spontaneous ordering of deposited organic semiconductor layers. We investigated structure and morphology of PTFE layers deposited by vacuum process in dependence on deposition parameters: deposition rate, deposition temperature, electron activation energy and activation current. The molecular structure of the PTFE films was investigated by use of infrared spectroscopy. By means of ellipsometry, values of refractive index between 1.33 and 1.36 have been obtained for PTFE films in dependence on deposition conditions. Using the cold friction technique orienting PTFE layers with unidirectional grooves are obtained. We have shown that DBFBT layers growth on top of rubbed PTFE films present a certain alignment suitable for building organic field-effect transistors with better transport parameters.     

Impact of space-time block codes on 802.11 network throughput

By employing more than one antenna at the transmitter and by properly coding data across the transmit antennas, physical layers (PHYs) with space-time block codes (STBCs) promise increased data rates with minimal decoding complexity at the receiver. This paper presents a comprehensive study of how the STBC gains at the PHY translate to significant network performance improvement in 802.11a wireless local area networks. We base our study on a detailed, across-all-layers, simulation of an 802.11a system. We have extended the network simulator with an implementation of the 802.11a PHY, which allows us to assess the impact of STBC not only at the PHY layer, but at the higher layers as well. An extensive set of simulations illustrates the merits of transmit diversity (in the form of STBC) and sheds light on how performance can be improved for transmission control protocol (TCP) traffic. Essentially, STBC presents to TCP a "smoother" wireless channel; this is corroborated by a brief theoretical analysis as well.     

Inverter EMI modeling and simulation methodologies

A numerical prediction of electromagnetic interference (EMI) allows evaluation of EMI performances at the design stage and before prototyping. It can also help reduce the post-prototype electromagnetic compatibility cost by minimizing late redesign and modifications of a drive implementation. This paper describes two simulation approaches with time- and frequency-domain simulations and verifies them with experimental results. Both time- and frequency-domain simulation approaches are found effective as long as the noise source and propagation path are properly modeled. The three-dimensional (3-D) finite-element-analysis (FEA)-based parasitic parameter extraction tool-Ansoft Spicelink has been used substantially. To gain additional degree of confidence, the results obtained from FEA are verified with closed-form solutions and actual measurements.     

Electroless deposition of Co(W) thin films

Thin films of cobalt that contain small amounts of tungsten [Co(W)] were deposited by the electroless process. Those films do not contain either phosphorus or boron which are included in most electroless cobalt films processes. The deposition bath for Co(W) thin films include Co ions, tungstate ions as a source for tungsten, di-methyl-amine-borane (DMAB) complex as a reducing agent, ammonium hydrate as a complexing agent, acetic acid for buffering and surfactants. Co(W) layers were deposited on two types of seed layers: (a) thin sputtered cobalt or copper films on 100 nm SiO₂/Si and (b) bare silicon wafers activated by an aqueous Pd/PdCl₂ solution. The deposited layer thickness range was 40–1000 nm with deposition rate at 90 °C and pH 9 of 7 nm/s for both Pd activated Si and sputtered Co seed, and 5 nm/s for the sputtered Cu seed. Lowering the temperature to 70 °C lowered the deposition rate to 0.7 nm/s for the Pd activated Si. The deposited layers were bright coloured, uniform, and with low defect density under visual inspection. The thin films composition was found to be Cobalt with 3–4 at.% tungsten for all types of seed layers. The Co(W) thin films specific resistivity was in the range of 60–90 μΩ cm. Finally we present the thin film morphology as it was characterized using atomic force microscopy and scanning electron microscopy.     

Characterization of ZnO and ZnO:Al films deposited by MOCVD on oriented and amorphous substrates

Zinc oxide (ZnO) and ZnO:Al-doped films were deposited by metal organic chemical vapour deposition (MOCVD) using the Zn(tta)₂·tmeda (H-tta=2-thenoyltrifluoroacetone, tmeda=N,N,N′,N′-tetramethylethylendiamine) and Al(acac)₃ (H-acac=acetylacetone) precursors on different substrates. The deposited layers were characterised by X-ray diffraction (XRD) and field-emission scanning electron microscopy (FE-SEM). Film structure is strongly dependent on the substrate nature and deposition conditions. AFM and XRD measurements show a good film texture and a preferential orientation along the c-axis. The Al concentration of ZnO:Al film has been confirmed by energy dispersive X-ray (EDX) analysis. Optical transparency of these ZnO layers has been studied in order to evaluate their applications as a transparent conducting oxide (TCO) material.     

Control of the crystalline phase and morphology of CdS deposited on microstructured surfaces by chemical bath deposition

Chemical bath deposition (CBD) has been used extensively to deposit thin films of CdS for window layers in solar cells. The microtopography or roughness of the surface, however, can affect the quality of the film by influencing the morphology, uniformity, or crystal phase of the CdS film. Here, we have demonstrated that thin films of CdS can be successfully patterned on surfaces bearing micropillars as a model surface for roughness. The phase purity of CdS deposited on the micropillar surfaces is uniform and conformal with the formation of packed clusters on the micropillars at pH 10 that form flower-like structures at long deposition times. Smaller crystallites were observed on micropillar arrays at pH 8 with “network” like structures observed at long deposition times. Additionally, by controlling the pH of the chemical bath, the hexagonal and cubic crystal phases of CdS were both accessible in high purity at temperatures as low as 85 °C.