基于CNN的康普顿背散射图像中违禁品分割方法

康普顿背散射(CBS)技术是一项较新的射线安检技术,可以提高复杂背景下安检设备对爆炸物等有机违禁品的探测力度,这其中一个重要环节就是图像中违禁品的分割问题.本文提出了一种基于细胞神经网络(CNN)的CBS图像滤波及分割方法,在此基础上又提出了一种基于CNN和数学形态学的孤立点滤除方法,并对这两种方法进行了详细分析,给出...     

一种低资源消耗的运动估计VLSI实现算法

现有的VLSI(verylarge scale integration)视频编码芯片多使用全搜索运动估计(ME)方法,且没有搜索中心偏移(CB)的并行实现方法。本文提出一种适合VLSI的H.264、AVS CB并行搜索方案,减少搜索点数量,降低逻辑资源的消耗,并且使用预测高概率区域的方法,保证ME精度。实验表明,本方法具备较好的率失真性能。在现场可编程门阵列(FPGA)平台上实现了本算法,逻辑综合的数据表明,硬件资源消耗降低了64%。本算法可应用于标清和高清电视(HDTV,hign-definition television)视频编码器。     

基于局部Lax-Friedrichs通量分裂格式的透视SFS

提出了一种基于局部Lax-Friedrichs通量分裂格式的快速扫描算法,用以解决透视投影下的SFS问题.先对透视投影SFS进行建模,将其转换为静态Hamilton-Jacobi方程,再结合局部Lax-Friedrichs通量分裂格式和快速扫描算法对静态Hamilton-Jacobi方程进行求解,从而得到物体表面.本文算法可以用于非凸Hamiltonian函数的情况,提高了局部分析能力,不需要对初始高度进行估计,且算法简单,易于实现.对合成图像和实际图像的实验表明本文算法可以得到较好的透视投影SFS的恢复结果.     

一种GF(2k)域的高效乘法器及其VLSI实现

在分析全串行和全并行GF(2k)域乘法的基本原理基础上提出了一种适合于任意GF(2k)域的乘法器UHGM(Unified Hybrid Galois Field Multiplier)．它为当前特别重要的k为素数的GF(2k)域乘法,提供了一种高效的实现方法．该乘法器具有结构规整、模块化好的特点,特别适合于VLSI实现,同时这种结构具有粗粒度的面积和速度的可伸缩性,方便了在大范围内进行实现面积和速度的权衡．最后给出了GF(2163)域上乘法器的ASIC综合的结果．     

离散余弦变换的改进的算术傅立叶变换算法

离散余弦变换(DCT)是数字图像处理等许多领域的重要数学工具.本文通过一种新的傅立叶分析技术——算术傅立叶变换(AFT)来计算DCT.本文对偶函数的AFT进行了改进.改进的AFT算法不但把AFT所需样本点数减少了一半,从而使所需加法计算量减少了一半,更重要的是它建立起AFT和DCT的直接联系,因而提供了适合用于计算DCT的AFT算法.本文推导了用改进的AFT计算DCT的算法并对算法进行了简要的分析.这种算法的乘法量仅为O(N),并且具有公式一致,结构简单,易于并行,适合VLSI设计等特点,为DCT的快速计算开辟了新的途径.     

基于卷积神经网络与注意力机制的高光谱图像分类

由于浅层卷积神经网络(convolutional neural network,CNN)模型感受野的限制,无法捕获远距离特征,在高光谱图像 (hyperspectral image,HSI) 分类问题中无法充分利用图像空间-光谱信息,很难获得较高精度的分类结果。针对上述问题,本文提出了一种基于卷积神经网络与注意力机制的模型(model based on convolutional neural network and attention mechanism,CNNAM),该模型利用CA (coordinate attention)对图像通道数据进行位置编码,并利用以自注意力机制为核心架构的Transformer模块对其进行远距离特征提取以解决CNN感受野的限制问题。CNNAM在Indian Pines和Salinas两个数据集上得到的总体分类精度分别为97.63%和99.34%,对比于其他模型,本文提出的模型表现出更好的分类性能。另外,本文以是否结合CA为参考进行了消融实验,并证明了CA在CNNAM中发挥重要作用。实验证明将传统CNN与注意力机制相结合可以在HSI分类问题中获得更高的分类精度。     

超荧光光纤光源相对强度噪声数字抑制系统

超荧光光纤光源(SFS)具有高稳定性,是光纤传感器(FOSs)中一种理想的光源。SFS 光源的相对强度噪声(RIN)是影响FOSs 性能的一个重要的因素。由于使用模拟抑制电路的噪声抑制系统无法很好的抑制RIN,文中提出了使用强度调制器的数字RIN 抑制系统。为了验证此想法,建立了半实物仿真模型,该模型可以在中心频率处抑制RIN 达到20 dB。该数字系统相对原有模拟系统,性能有了很大的提高,因此对FOSs 性能的提高有很大的贡献。     

VLSI局部电源网络的宏模型研究

针对大规模VLSI电源网络分析效率问题,提出一种局部电源网络宏模型求解方法,根据其结构特点,结合电路等效变换与电路合并,对电路模型进行简化,并建立其宏模型.在全局电源网络分析中,利用各局部电源网络宏模型替代其完整电路模型,以降低分析问题的规模与复杂度.实验结果表明,在电源网络分析中应用宏模型技术,可以将分析效率提高1.7倍,且性能随电源网络规模的增大而提高.     

TD-SCDMA标准的CDMA/TDMA改革方案

文章证明了TD-SCDMA标准所定义的智能天线在TD-SCDMA标准中的不可用性,因此必须对该标准进行大规模改造。文章给出一种在上/下行信道分别使用码分多址/时分多址(CDMA/TDMA)的TD-SCDMA标准的改革方案。该方案在下行信道中可以继续使用TD-SCDMA标准所定义的智能天线,使中国唯一具有自主知识产权的移动通信标准获得新生。在下行信道中还可以使用八相相移键控(8PSK)、16进制正交调幅(16QAM)等高频谱利用率的调制方法,能将富裕的下行功率变换为频谱利用率。改革后的TD-SCDMA标准将能满足移动因特网的应用要求。     

融合多元经验模态分解与Hilbert空间填充曲线的sEMG处理方法

基于卷积神经网络(convolutional neural network, CNN)的表面肌电信号(surface electromygraphy, sEMG)手势识别算法通常将一维sEMG转换成二维肌电图作为CNN的输入。针对sEMG瞬时样本量偏少、以及一维sEMG转换成二维肌电图时带来的局部时序特征丢失等问题,提出了将多元经验模态分解(multivariate empirical mode decomposition, MEMD)算法与Hilbert空间填充曲线相结合的方法,以提升手势识别算法的准确率。采用开源数据集NinaPro-DB1作为实验数据集;通过MEMD算法对sEMG进行分解;将分解后的本征模态函数(intrinsic mode functions, IMFs)作为Hilbert曲线的填充域(Hilb-IMFs)映射成二维肌电图;选择DenseNet作为手势识别的基本网络。实验结果表明,提出的方法相对于传统信号升维方法在手势识别准确率上约有4%的性能提升,验证了该方法的有效性。     

Analytic and VLSI Specific Design of Robust CNN Templates

Parameter learning or design is a key issue in cellular neural network (CNN) theory. If the CNN is implemented as an analog VLSI chip, additional constraints are posed due to its restricted accuracy. Only robust parameters will still guarantee the correct network behavior. We present an analytical design approach for the class of bipolar CNNs which yields optimally robust template parameters. We give a rigorous definition of absolute and relative robustness and show that all well-defined CNN tasks are characterized by a finite set of linear and homogeneous inequalities. This system of inequalities can be analytically solved for the most robust template by simple matrix algebra. Focusing on a particular implementation of the CNN universal chip, we demonstrate that the proposed method can cope with the manufacturing inaccuracies.     

Signal processing using cellular neural networks

The cellular neural network (CNN) architecture combines the best features from traditional fully-connected analog neural networks and digital cellular automata. The network can rapidly process continuous-valued (gray-scale) input signals (such as images) and perform many computation functions which traditionally were implemented in digital form. Here, we briefly introduce the the theory of CNN circuits, provide some examples of CNN applications to image processing, and discuss work toward a CNN implementation in custom CMOS VLSI. The role of analog computer-aided design (CAD) will be briefly presented as it relates to analog neural network implementation.This work is supported in part by the Office of Naval Research under Contract N00014-89-J1402, and the National Science Foundation under grant MIP-8912639.     

CNN-Based Hybrid-Order Texture Segregation as Early Vision Processing and Its Implementation on CNN-UM

In this paper, a biologically inspired, CNN-based, multi-channel, texture boundary detection technique is presented. The proposed approach is similar to human vision system. The algorithm is simple and straightforward such that it can be implemented on the cellular neural networks (CNNs). CNN contains several important advantages, such as efficient real-time processing capability and feasible very large-scale integration (VLSI) implementation. The proposed algorithm also had been widely tested on synthetic texture images. Those texture images are randomly selected from the Brodatz textures database (1966). According to our simulation results, the boundaries of uniform textures can be detected quite successfully. For the nonuniform or nonregular textures, the results also indicate meaningful properties, and the properties also are consistent to the human visual sensation. The proposed algorithm also has been implemented on the CNN universal machine (CNN-UM), and yields similar results as the simulation on the PC. Based on the efficient performance of CNN-UM, the algorithm becomes very fast.     

Analog VLSI implementation of wavelet transform using switched-current circuits

For applications requiring low-voltage low-power and real-time processing, a novel scheme for the VLSI implementation of wavelet transform (WT) using switched-current (SI) circuits is presented. SI circuits are well suited for these applications since the dilation constant across different scales of the transform can be implemented, and controlled by both the aspect-ratio of the transistors and the clock frequency. The quality of such implementation depends on the accuracy of the corresponding wavelet approximation. First, an optimized procedure based on differential evolution algorithm (DE) is applied to approximate the transfer function of a linear steady-state system whose impulse response is the required wavelet. The proposed approach significantly improves the accuracy of approximation wavelets. Next, the approximation of time-domain wavelet function is implemented by the SI analog filters. Finally, the design of the complete SI filter based on first-order and biquad section as main building block is detailed. Simulations demonstrate the performance of the proposed approach to analog WT implementation.     

JPEG2000小波变换器的VLSI结构设计

新一代静止图像压缩标准JPEG2000将离散小波变换(DWT)作为其核心变换技术,并推荐采用推举体制(lifting)快速算法来实现.空间组合推举体制算法(SCLA)大大降低了lifting的运算量.当选用9/7小波滤波器时,SCLA的乘法运算量只有lifting的7/12.本文提出了一种实现SCLA算法的VLSI结构,降低了基于lifting实现的运算量, 加快了变换的速度,减小了电路的规模.本文的二维正反小波变换器已经作为单独的IP核应用于我们目前正在开发的JPEG2000图像编解码芯片中.     

离散傅里叶变换的算术傅里叶变换算法

离散傅里叶变换(DFT)在数字信号处理等许多领域中起着重要作用.本文采用一种新的傅里叶分析技术—算术傅里叶变换(AFT)来计算DFT.这种算法的乘法计算量仅为O(N);算法的计算过程简单,公式一致,克服了任意长度DFT传统快速算法(FFT)程序复杂、子进程多等缺点;算法易于并行,尤其适合VLSI设计;对于含较大素因子,特别是素数长度的DFT,其速度比传统的FFT方法快;算法为任意长度DFT的快速计算开辟了新的思路和途径.     

Time multiplexed color image processing based on a CNN withcell-state outputs

A practical system approach for time-multiplexing cellular neural network (CNN) implementations suitable for processing large and complex images using small CNN arrays is presented. For real size applications, due to hardware limitations, it is impossible to have a one-on-one mapping between the CNN hardware cells and all the pixels in the image involved. This paper presents a practical solution by processing the input image, block by block, with the number of pixels in a block being the same as the number of CNN cells in the array. Furthermore, unlike other implementations in which the output is observed at the hard-limiting block, the very large scale integrated (VLSI) architecture hereby described monitors the outputs from the state node. While previous implementations are mostly suitable for black and white applications because of the thresholded outputs, our approach is especially suitable for applications in color (gray) image processing due to the analog nature of the state node. Experimental complementary metal-oxide-semiconductor (CMOS) chip results in good agreement with theoretical results are presented     

Focal-Plane and Multiple Chip VLSI Approaches to CNNs

In this paper, three alternative VLSI analog implementations of CNNs are described, which have been devised to perform image processing and vision tasks: a programmable low-power CNN with embedded photo-sensors, a compact fixed-template CNN based on unipolar current-mode signals, and basic CMOS circuits to implement an extended CNN model using spikes. The first two VLSI approaches are intended for focal-plane image processing applications. The third one allows, since its dynamics is defined by process-independent local ratios and its input/outputs can be efficiently multiplexed in time, the construction of very large multiple chip CNNs for more complex vision tasks.     

On the VLSI implementation of real-time order statistic filters

Real-time implementation of an order-statistic filter (OSF) or ranked order filter requires the computation of the order statistic (ranked order) of the samples in a window which gets periodically updated with the arrival of a new sample(s). The authors give an algorithm for the computation of the running order statistic. A highly parallel architecture suitable for VLSI implementation is presented. The architecture is very versatile, with programmable window size and rank order. An expansion algorithm and its VLSI architecture, which permit the usage of two r-bit OSFs to implement an (r+1)-bit OSF, where r is the resolution of the input signal samples, are given. In a special case where one is satisfied with at most one LSB error, the hardware complexity of the proposed architecture can be reduced by almost one half. It is further shown how a VLSI chip incorporating the proposed architecture can be used as the basic building block in the real-time implementation of other forms of nonlinear filters