双边单元的LSI自动布局算法

本文采用带冗余通道的双边单元模型,提出了一种有效的LSI自动布局算法.算法中运用“等分接点法”进行单向的布局初始构造,并用多种方式进行布局的迭代优化处理.由于在布局过程中对所有纵向连线的通道分配进行了统一的考虑,提高了设计的整体合理性.本文提出的布局算法和我们提出的“通道区布线的通道损益分析法”可望成为一个有效的布图设计系统的基础.     

CMOS单元版图生成算法综述

基于库单元的ASIC设计方法对单元版图自动生成工具提出了很高的要求。CMOS单元版图生成可分成MOS管布局、单元内布线和版图压缩三步。文章从不同的单元版图布图样式出发,综述布局、布线及压缩算法的发展现状,具体介绍几个单元版图生成系统,最后指出了该研究领域存在的问题。     

VLSI积木块布图设计的通道定序与布线

本文研究了VLSI积木块布图设计中的通道定序与布线问题。首先提出了T形约束图的概念和通道分级的思想,针对布局中出现的循环通道约束,基于三边通道的布线,通过引入一类通道——预定通道来破坏约束环。在此基础上,给出了一个在给定积木块的布局和总体布线条件下通道定序与布线的有效算法。算法已在UNIVAC1100/10上用FORTRAN77实现,结果令人满意。     

一种针对QCA电路自动布局布线的混合策略研究

量子元胞自动机（Quantum Cellular Automata,QCA）电路的自动布局布线是在相关约束条件下自动放置电路单元、自动形成连线，实现门级或元胞级电路的设计过程，是QCA电路设计大型化、复杂化和系统化的必要工具.布局布线算法设计过程中最大的难题是如何解决“时钟同步”，随着二维时钟方案提出，该问题的解决方案变得更加策略化，但仍存在诸多缺陷，如成功率低，布局面积较大等.本文将二维时钟方案的布局布线问题抽象成组合优化模型，提出了一种基于遗传算法GA(Genetic Algorithm)和改进A*算法的混合策略.两种算法相互配合搭建可能的电路布局，并通过精心设计的适应度函数，搜索满足时钟同步的个体，最终实现从硬件电路到二维时钟方案上的门级布局.实验结果表明，本算法在目前被广泛应用的二维时钟方案USE(Universal,Scalable and Efficient)上的布局成功率接近100%.相较当前世界上最先进的两个QCA布局布线工具fiction和Ropper，本算法可适用电路规模更大（逻辑门数量大于10），在成功率和生成布局面积上都有大幅度的优化.     

门阵列布局合理化研究

本文对门阵列的子单元和电源线的布局结构进行了分析,用图论理论对通道和二次布线做了研究。给出了门阵列子单元和电源线的合理化布局,所需通道的最少数和二次布线长度最短的方法。     

LSIS-2自动布图设计系统

<正> LSIS-2布图设计系统是一个用于LSI/VLSI芯片自动布图设计的系统,LSIS-2系统采用多元胞(polycell)兼容宏单元(macrocell) 的设计模式,系统的主要部份有:分级布图设计描述语言及其编译子系统,二级单元库及其管理子系统.设计描述正确性验证子系统,自动布局及总体布线设计子系统,多目标优化的自动布线设计子系统,实体化设计,输出转换及人机交互设计子系统.     

实现从Multisim到Protel 99 SE中的自动布线

主要阐述Protel99SE利用Multisim生成的网络表进行自动布线的原理及实现的方法。具体包括Multisim网络表的生成、接口的修改、自动布线等,同时指出从Multisim到Protel99SE文件兼容性方面存在的问题,并提出解决方案。通过实例结果可以看出此方案完全能够实现从Multisim到Protel99SE中自动布线。此方法对于解决从Multisim到Protel99SE中的自动布线具有很好的实用价值。     

基于Multisim 9的数字电子钟设计与仿真

数字电子钟广泛应用于各个公共场所,其电路设计的一般方法是连线多而杂,不便于理解其电路构成。利用中规模集成电路,设计了数字电子钟,由于采用了层次电路设计方法,将其分成各个单元电路设计成层次块,最后将各层次块连线成整机电路,连线美观,便于理解各单元电路功能,其整机电路功能也一目了然。     

基于线网路径总体分配的LSI环形通道全局布线方法

大规模集成电路(LSI)中,在芯片周界的环形区域内,环形通道布线完成线网与压焊块的自动连接与压焊块的最终定位.基于环形通道区的特征与线网路径约束关系的分析,本文提出一个新的环形通道自动全局布线方法.文中详细地讨论了线网拓扑路径总体分配的图模型和轨道优化分配公式,并介绍实现的算法.实例结果十分令人满意,优于国外同类问题的最新算法的结果.     

IO单元自动排布算法IOAP

提出了一种应用于芯片物理设计过程中IO单元自动排布的新算法。IO单元排布是芯片物理设计过程中长期依赖经验的环节。IO单元排布的优化对布线,电源网格和设计收敛性的优化有很大贡献。文章重点研究边缘IO单元排布,提出了IO单元自动排布算法(IOAP)。此算法及其相关软件直接应用于视频解码芯片和无线传感器网络处理器芯片(已流片成功)的物理设计流程中。结果表明,IOAP有效改善了芯片的电源网格,时序和布线结果,减少了布线努力,提高了设计收敛性。     

ThunderBird: a complete standard cell layout package

The generalized standard cell layout style handled by ThunderBird is characterized by horizontal rows of standard cells with pads placed around the periphery of the chip. Furthermore, macro blocks may be present on the chip. The standard cells are permitted to have varying heights. The two key components of ThunderBird are TimberWolf3.2, a standard cell placement and global routing package, and the YACR II channel router. The placement and global routing proceed over three distinct stages: (1) cell placement for minimum interconnect length, (2) insertion of feedthrough cells or location of built-in feeds, and another interconnect-length minimization; and (3) local changes in placement to reduce the number of wiring tracks required. This channel router features a 100% routing completion rate while usually routing each channel using a number of tracks equal to a density of the channel. Results on industrial circuits versus numerous automatic and manual layout methods showed that ThunderBird yielded area savings ranging from 15 to 75%     

Middle terminal cell models for efficient over-the-cell routing inhigh-performance circuits

A new class of cell models called middle terminal models (MTM) is introduced. MTM-based cells allow flexibility in the selection of terminal locations and therefore utilize the over-the-cell (OTC) area more efficiently, as compared to cells based on existing models. For MTM-based designs, two new routers, MTM+V and MTM-V are presented. The first router is suitable for processes that allow vias over-the-cell and is based on an optimal Θ(K) algorithm for terminal row selection for over-the-cell channel routing, where K is the number of cell rows. The second router is suitable for the processes which do not allow vias in over-the-cell areas. This router consists of two key steps. The first step consists of the selection of a maximum planar set of nets for routing in between the terminal rows. For the second step, an optimal algorithm is developed for planar routing between the terminal row and the cell boundary. The experimental results on the PRIMARY I benchmark show that for a two-layer model, MTM-V performs 4.20% better than the best existing routers     

ECOP：一种基于单元行划分的标准单元模式增量布局算法

针对标准单元模式超大规模集成电路增量式布局问题,提出了一个全新的增量布局算法ECOP.该算法一改以往布局算法中以单元为中心的做法，变为以单元行为中心，围绕单元行来进行单元的插入，移动以及各种约束条件的处理.在划分单元行时，始终保持单元行的内部连通性，并对单元移动路径进行搜索与优化.对一组来自美国工业界的设计实例进行了测试.实验结果表明，ECOP算法是非常实用而高效的.     

ECOP:一种基于单元行划分的标准单元模式增量布局算法

针对标准单元模式超大规模集成电路增量式布局问题 ,提出了一个全新的增量布局算法 ECOP.该算法一改以往布局算法中以单元为中心的做法 ,变为以单元行为中心 ,围绕单元行来进行单元的插入 ,移动以及各种约束条件的处理 .在划分单元行时 ,始终保持单元行的内部连通性 ,并对单元移动路径进行搜索与优化 .对一组来自美国工业界的设计实例进行了测试 .实验结果表明 ,ECOP算法是非常实用而高效的     

MGS—CMOS宏单元模块自动生成系统

本文介绍一个CMOS宏单元模块自动生成系统,该系统根据宏单元的电路描述,经过逻辑综合后自动完成布局、布线工作。并将布图结果转换成版图描述文件,从而实现了宏单元建库及模块生成的自动化。为了保证布通率及生成模块的正确性,系统提供了交互布图环境和模块正确性验证工具。     

基于整数规划的优化拥挤度的增量式布局算法

提出了一种降低走线拥挤的标准单元增量式布局算法C-ECOP.首先通过一种新型的布线模型来估计芯片上的走线情况,然后构造一个整数线性规划问题来解决可能出现的相邻拥挤区域冲突问题.实验结果表明该算法能够有效地降低走线拥挤,保证初始布局的质量,并且具有很高的效率.     

基于整数规划的优化拥挤度的增量式布局算法

提出了一种降低走线拥挤的标准单元增量式布局算法C- ECOP.首先通过一种新型的布线模型来估计芯片上的走线情况,然后构造一个整数线性规划问题来解决可能出现的相邻拥挤区域冲突问题.实验结果表明该算法能够有效地降低走线拥挤,保证初始布局的质量,并且具有很高的效率     

Aladin: A Layout Synthesys Tool for Analog Integrated Circuits

This paper presents a layout synthesis tool called ALADIN for analog integrated circuits. It is developed especially for analog circuit designers who can bring their special knowledge and experience into the synthesis process to create high quality layouts. The layout generation is based on relatively complex sub-circuits rather than non-optimal single devices. A flexible module generator environment is developed for designers to write and maintain technology and application independent module generators of sub-circuits. Based on the thorough study of simulated annealing and genetic algorithm applications in the analog module placement, a genetic placement approach with simulated annealing and a very fast simulated re-annealing placement approach have been developed. A two-stage placement technique is proposed. Analog module routing consists of two phases including global routing and detailed routing. The minimum-Steiner-tree based global routing can be integrated into the placement procedure to improve the routability of placement solutions. The compaction based constructive detailed routing finally realizes the layout of the whole circuit. This tool is integrated into commercial software with convenient interfaces provided. The benefit of ALADIN providing layouts comparable to expert manual ones is demonstrated with several circuits showing its competition compared to other existing tools.     

KOAN/ANAGRAM II: new tools for device-level analog placement androuting

The authors describe KOAN and ANAGRAM II, new tools for device-level analog placement and routing. Analog layout tools that merely apply known digital macrocell techniques fall short of achieving the density and performance of handcrafted analog cells. KOAN and ANAGRAM II differ from previous approaches by using general algorithmic techniques to find critical device-level layout optimizations rather than relying on a large library of fixed-topology module generators. New placement algorithms implemented in KOAN handle complex layout symmetries, dynamic merging and abutment of individual devices, and flexible generation of wells and bulk constants. New routing algorithms implemented in ANAGRAM II handle arbitrary gridless design rules in addition to over-the-device, crosstalk-avoiding, mirror-symmetric, and self-symmetric wiring. Examples of CMOS and BiCMOS analog cell layouts produced by these tools are presented