自对准结构α—Si：H TFT特性的分析和研究

本文描述了用自对准工艺制备自对准结构的αＳｉ：Ｈ ＴＦＴ。从理论上分析了有源层α－Ｓｉ：Ｈ的厚度对α－Ｓｉ：Ｈ ＴＦＴ特性的影响，据此提出一种新型的双有源层结构的α－Ｓｉ ＴＦＴ。它可以有效地提高自对准αＳｉ：Ｈ ＴＦＴ的开态ＩＯＮ，其通断电流比ＩＯＮ／ＩＯＦＦ＞１０＾５。     

自对准结构α－Si：HTFT特性的分析和研究

本文描述了用自对准工艺制各自对准结构的α－Ｓｉ：ＨＴＦＴ。从理论上分析了有源层α－Ｓｉ：Ｈ的厚度对α－Ｓｉ：ＨＴＦＴ特性的影响，据此提出一种新型的双有源层结构的α－ＳｉＴＦＴ。它可以有效地提高自对准α－Ｓｉ：ＨＴＦＴ的开态Ｉ＿（ＯＮ），其通断电流比Ｉ＿（ＯＮ）／Ｉ＿（ＯＦＦ）＞１０￣５。     

a—Si：H TFT有源矩阵制造技术的研究

对ａ：Ｓｉ：Ｈ ＴＦＴ有源矩阵的一些关键制造工艺进行研究。研究了Ｔａ２Ｏ５／ａ－ＳｉＮｘ双绝缘层的制备技术，提出了一种新的双有源层结构ａ－Ｓｉ：Ｈ ＴＦＴ来降低背光源对器件特性的影响，研制的ａ－Ｓｉ：Ｈ ＴＦＴ有源矩阵实现了彩色视频信号的动态显示。     

薄有源层非晶硅薄膜晶体管特性的研究

本文研究了薄ａ－Ｓｉ：Ｈ有源层结构的ａ－Ｓｉ：Ｈ ＴＦＴ的特性，实验结果表明，当ａ－Ｓｉ：Ｈ层的厚度小于一个临界值时，ａ－Ｓｉ：Ｈ厚度的变化对ａ－Ｓｉ：Ｈ ＴＦＴ静态特性的影响明显增大，本文中详细分析了有源层背面空间电荷层对ａ－Ｓｉ：Ｈ ＴＦＴ特性的影响，从表面有效空间电荷层的概念出发，从理论上分析了有源层厚度与阈值电压的关系，计算的临界有源层厚度为１３０ｎｍ，这与实验结果基本一致。     

a—Si：H TFT电流—电压特性研究

本文发展了一种研究ａ－Ｓｉ：Ｈ ＴＦＴ电流－电压特性的新方法。基于局域态电荷密度解析统一模型，提出并深入分析了沟道区有效温度参数的概念，并由此推导出了ａ－Ｓｉ：Ｈ ＴＦＴ电流－电压特性的解析表达式。其理论值与实验值符合很好。该模型可用于ａ－Ｓｉ：Ｈ ＴＦＴ静态特性分析及其电路优化。     

a—SiN：：H的退火自理及其对a—Si：HTFT性能与可靠性的影响

研究了ａ－ＳｉＮ：Ｈ的退火行为及其作为栅介质使用时，退火对ａ－Ｓｉ：ＨＴＦＴ工作特性和可靠性的影响，实验事实表明，在３８０℃以下的退火处理ａ－ＳｉＮ：Ｈ介电常数的变化呈单调上升趋势，对ａ－ＳｉＮ：Ｈ ＴＦＴ的工作特性和可靠性有明显的改善，温度进一步升高时，介电常数减小，ａ－Ｓｉ：ＨＴＦＴ的特性变坏。     

a－SiN∶H的退火处理及其对a－Si∶H TFT性能与可靠性的影响

研究了ａ－ＳｉＮ：Ｈ的退火行为及其作为栅介质使用时，退火对ａ－Ｓｉ：ＨＴＦＴ工作特性和可靠性的影响．实验事实表明，在３８０℃以下的退火处理使ａ－ＳｉＮ：Ｈ介电常数的变化呈单调上升趋势，对ａ－Ｓｉ：ＨＴＦＴ的工作特性和可靠性有明显的改善，温度进一步升高时，介电常数减小，ａ－Ｓｉ：ＨＴＦＴ特性变坏．     

a-SiOx:H/a-SiOy:H多层薄膜微结构的退火行为

采用ＰＥＣＶＤ技术在Ｐ型硅衬底上制备了ａ－ＳｉＯｘ：Ｈ／ａ－ＳｉＯｙ：Ｈ多层薄膜,利用ＡＥＳ和ＴＥＭ技术研究了这种薄膜微结构的退火行为,结果表明：ａ－ＳｉＯｘＬ：Ｈ／ａ－ＳｉＯｙ：Ｈ多层薄膜经退火处理形成ｎｃ－Ｓｉ／ＳｉＯ２多层量子点复合膜,膜层具有清晰完整的结构界面,纳米硅嵌埋颗粒呈多晶结构,颗粒大小随退火温度升高而增大小随退火温度升高而增大,在一定的实验条件下,样品在６５０℃下退火可形成尺寸大     

a－SiFET电流－电压特性研究

本文对ａ－ＳｉＦＥＴ的电流－电压特性的理论研究提出一种新的方法。其不需要引入ａ－Ｓｉ隙态密度分布的具体假设模型，采用合理的数学方法，推导出ａ－ＳｉＦＥＴ电流－电压关系的解析表达式，对ａ－ＳｉＦＥＴ电流－电压特性进行合理的解释。并且理论分析结果与实验结果能很好符合，为ａ－ＳｉＦＥＴ的理论分析开辟了一条新途径。     

a—SiFET电流—电压特性研究

本文对ａ－ＳｉＦＥＴ的电流－电压特性的理论研究提出一种新的方法。其不需要引入ａ－Ｓｉ隙态密度分布的具体假设假设模型，采用合理的数学方法，推导出ａ－ＳｉＦＥＴ电流－电压关系的解析表达式，对ａ－ＳｉＦＥＴ电流－电压特性进行合理的解释。并且理论分析结果与实验结果能很好符合，为ａ－ＳｉＦＥＴ的理论分析开辟了一条新途径。     

High-performance hydrogenated amorphous-Si TFT for AMLCD and AMOLED applications

A novel technology for manufacturing high-performance hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) is developed in this letter. In the bottom gate light-shield a-Si:H TFT structure, the side edge of a-Si:H island is capped with extra deposition of heavily phosphorous-doped a-Si layer. Such an ingenuity can effectively eliminate the leakage path between the parasitic contacts of source/drain metal and the sidewall of a-Si:H island edge. In addition, electrical performance of the novel a-Si:H TFT device exhibits superior effective carrier mobility as high as 1.05 cm/sup 2//Vs, due to the enormous improvement in parasitic resistance. The impressively high performance of the proposed a-Si:H TFT provides the potential to apply foractive matrix liquid crystal display and active matrix organic light-emitting diode technology.     

A polycrystalline silicon thin-film transistor with a thinamorphous buffer

We have developed a novel, low off-state leakage current polycrystalline silicon (poly-Si) thin-film transistor (TFT) by introducing a very thin hydrogenated amorphous silicon (a-Si:H) buffer on the poly-Si active layer. The a-Si:H buffer is formed on the whole poly-Si and thus no additional mask step is needed. With an a-Si:H buffer on poly-Si, the off-state leakage current of a coplanar TFT is remarkably reduced, while the reduction of the on-state current is relatively small. The poly-Si TFT with an a-Si:H buffer exhibited a field effect mobility of 12 cm²/Vs and an off-state leakage current of 3 fA/μm at the drain voltage of 1 V and the gate voltage of -5 V     

High mobility tri-layer a-Si:H thin-film transistors with ultrathinactive layer

We show that hydrogenated amorphous silicon thin-film transistors (a-Si:H TFT's) with active layer thickness of 13 nm perform better for display applications than devices with thicker 50-nm active layers. A direct comparison of a-Si:H TFT's fabricated using an i-stopper TFT structure shows that ultrathin active layers significantly improve the device characteristics. For a 5-μm channel length TFT, the linear region (V_DS=0.1 V) and saturation region mobilities increase from 0.4 cm²/V·s and 0.7 cm²/V·s for a 50-nm thick active layer a-Si:H device to 0.7 cm²/V·s and 1.2 cm²/V·s for a 13-nm thick active layer a-Si:H layer device fabricated with otherwise identical geometry and processing     

用于TFT有源层的Ar~+激光结晶a-Si:H的性质(英文)

This paper demonstrates the technological approach to the high performance a-Si:H thin film transistor (TFT) fabricated by the Ar+ laser-crystallization technique on the fused quartz substrates. The a-Si:H films for the active layer of TFT were prepared in a capacitively coupled glow-discharge deposition system. The films were crystallized by CW Ar+ laser scanning at low speeds (3-5 cm/s). The laser power ranges from 2.5W to 5.0W. The TEM cross-section micrograph illustrates that a liquid phase laser crystallization region (LP-LCR) has defect-free of structure with a grain size of the order of handreds of micron. In the Raman spectrum of LP-LCR, 475 cm-1 peak of a-Si:H disappears and 520 cm-1 peak of c-Si becomes stronger and sharper. The value of conductivity in the layer of LP-LCR is five orders of magnitude larger than the one in asepositedd a-Si:H film. We also discussed some problems to be overcome in application of a-Si : H TFTs in LCD.     

A new a-Si:H TFT pixel circuit compensating the threshold voltage shift of a-Si:H TFT and OLED for active matrix OLED

We propose a new hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) pixel circuit for an active matrix organic light-emitting diode (AMOLED) employing a voltage programming. The proposed a-Si:H TFT pixel circuit, which consists of five switching TFTs, one driving TFT, and one capacitor, successfully minimizes a decrease of OLED current caused by threshold voltage degradation of a-Si:H TFT and OLED. Our experimental results, based on the bias-temperature stress, exhibit that the output current for OLED is decreased by 7% in the proposed pixel, while it is decreased by 28% in the conventional 2-TFT pixel.     

Amorphous silicon thin film transistor circuit integration for organic LED displays on glass and plastic

This paper presents design considerations along with measurement results pertinent to hydrogenated amorphous silicon (a-Si:H) thin film transistor (TFT) drive circuits for active matrix organic light emitting diode (AMOLED) displays. We describe both pixel architectures and TFT circuit topologies that are amenable for vertically integrated, high aperture ratio pixels. Here, the OLED layer is integrated directly above the TFT circuit layer, to provide an active pixel area that is at least 90% of the total pixel area with an aperture ratio that remains virtually independent of scaling. Both voltage-programmed and current-programmed drive circuits are considered. The latter provides compensation for shifts in device characteristics due to metastable shifts in the threshold voltage of the TFT. Various drive circuits on glass and plastic were fabricated and tested. Integration of on-panel gate drivers is also discussed where we present the architecture of an a-Si:H based gate de-multiplexer that is threshold voltage shift invariant. In addition, a programmable current mirror with good linearity and stability is presented. Programmable current sources are an essential requirement in the design of source driver output stages.     

Hydrogen dilution effect on the properties of coplanar amorphoussilicon thin-film transistors fabricated by inductively-coupled plasmaCVD

The electrical and optical properties of the hydrogenated amorphous silicon (a-Si:H) films deposited by inductively-coupled plasma (ICP) chemical vapor deposition (CVD) with a variation of H₂ flow rate have been studied. The photosensitivity of a-Si:H is ~10⁷ when the H₂/SiH₄ ratio is between 3 and 8. With increasing H₂/SiH₄, the SiH₂ mode infrared absorption has a minimum at a H₂/SiH₄ ratio of 8. Coplanar a-Si:H thin-film transistors (TFT's) were fabricated using a triple layer of thin a-Si:H, silicon-nitride, and a-Si:H deposited by ICP-CVD using ion doping and low resistivity Ni silicide. After patterning the thin a-Si:H/silicon-nitride layers on the channel region, the gate and source/drain regions were ion-doped and then heated at 230°C to form Ni silicide layers. The low resistive Ni silicide formed on the a-Si:H reduces the offset length between gate and source/drain, leads to a coplanar a-Si:H TFT. The TFT exhibited a field effect mobility of 0.6 cm²/Vs and a threshold voltage of 2.3 V at the H₂/SiH₄ ratio of 8. The effect of H₂ dilution in SiH₄ on the coplanar a-Si:H TFT performance has been investigated. We found that the performance of the TFT is the best when the SiH₂ mode density in a-Si:H is the minimum. The coplanar TFT is very suitable for large-area, high density TFT displays because of its low parasitic capacitance between gate and source/drain contacts     

A novel coplanar amorphous silicon thin-film transistor usingsilicide layers

A novel, coplanar, hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) was fabricated by depositing a triple layer consisting of a-Si:H, silicon-nitride, and a-Si:H. After patterning the top two layers in the gate stack, the devices were doped and a 30 nm Ni layer was deposited. The devices were then annealed for 1 h at 230°C to form self-aligned, low resistive Ni-silicide. The fabricated coplanar a-Si:H TFT exhibits a field effect mobility of 0.6 cm²/Vs, a threshold voltage of 2 V, a subthreshold slope of 0.4 V/dec, and an on/off current ratio of ~10⁷