铜互连可靠性分析

在简要的对铜互连和铝互连进行了比较后,本文从材料特性和集成工艺两方面讨论了铜互连和铝互连对可靠性的不同影响,并详细的分析了一个关键的可靠性失效机理:电迁移(包括通孔损耗和连线损耗).最后讨论了影响铜电迁移的一些工艺要素,如通孔、阻挡层和覆盖层.     

ULSI中金属互连系统上的热点分析

针对金属互连系统上的热点将对集成电路芯片的性能和可靠性产生重大的影响,详细讨论了ULSI金属互连系统上的热点位置和温度分布模型,并通过该模型比较了不同通孔直径和高度情况下,金属互连系统上的热点位置和温度的差别。结果表明,通孔直径和高度对金属互连系统上的热点有重大的影响。     

Cu互连应力迁移失效有限元分析

为研究铜互连系统中各因素对残余应力及应力迁移失效的影响,建立了三维有限元模型,用ANSYs软件分析计算了Cu互连系统中的残余应力分布情况,并对比分析了不同结构、位置及层间介质材料的互连系统中的残余应力及应力梯度.残余应力在金属线中通孔正下方M2互连顶端最小,在通孔内部达到极大值,应力梯度在Cu M2互连顶端通孔拐角底部位置达到极大值.双通孔结构相对单通孔结构应力分布更为均匀,应力梯度更小.结果表明,空洞最易形成位置由应力和应力梯度的大小共同决定,应力极大值随通孔直径和层间介质介电常数的减小而下降,随线宽和重叠区面积的减小而上升.应力梯度随通孔直径、层间介质介电常数和重叠区面积的减小而下降,随线宽减小而上升.     

一种金属填充硅通孔工艺的研究

硅通孔(Through silicon via)的互连技术是3D IC集成中的一种重要工艺。报道了一种高深宽比的垂直互连穿透硅通孔工艺,其通孔的深宽比达到50以上;研究了利用钨填充硅通孔的一些关键工艺,包括阻挡层淀积工艺和钨填充工艺,分析了不同填充工艺所造成的应力的变化。最后获得了一种深宽比达到58∶1的深硅通孔无缝填充。     

ULSI互连系统热特性的模拟

应用基于有限元算法的软件 ANSYS对 0 .15 μm工艺条件下的一个 U L SI电路的五层金属互连结构进行了热特性模拟和分析 .模拟了这个经多目标电特性优化了的互连结构在采用不同金属 (Cu或 Al)互连线及不同电介质 (Si O2 或低介电常数材料 xerogel)填充条件下的热分布情况 ,计算了这些条件下此互连结构的温度分布 .并将结果与 Stanford大学模拟的另一种五层金属布线结构的热特性结果进行了比较 .讨论了低介电常数材料的采用对于互连结构散热情况的影响 .此外 ,还简要地介绍了 ANSYS的性能和用于热模拟的原理和特色     

互连铝通孔电迁移特征及其可靠性研究

研究了超大规模集成电路铝互连系统中铝通孔的电迁移失效机理及其可靠性寿命评价技术.试验采用CMOS和BiCMOS两种工艺各3组的铝通孔样品,分别在三个温度、恒定电流的加速条件下试验,以通孔开路为电迁移失效判据,最后得到了在加速条件下互连铝通孔的电迁移寿命,其结果符合标准的威布尔分布,试验准确可行.通过电迁移模型对试验数据进行了拟合,得到了激活能、电流加速因子和温度加速因子,计算出了正常工作条件下通孔电迁移的寿命,完成了对铝通孔电迁移的研究和寿命评价.     

铜互连线静水应力的有限元模拟

本文根据工业上使用的铜大马士革互连线尺寸建立了三维有限元模型,模拟计算了铜大马士革互连线中对应力诱导形成空洞很关键的静水应力分布,对比分析了不同低k介质、阻挡层材料和互连线深宽比对静水应力的影响。研究结果表明,静水应力受k介质、阻挡层材料和互连线深宽比影响很大,静水应力在铜大马士革互连线中分布不均匀且最大应力出现在互连线表面。     

铜互连线内电流拥挤效应的影响

提出了一种新的测试结构(S结构),通过实验、理论推导和有限元分析,研究了铜与TaN扩散阻挡层界面的电流拥挤效应对电迁移致质量输运特性的影响.实验和有限元分析表明,铜互连线内由于电流拥挤效应的存在,在用户温度下沿特定通道输运的局部原子通量显著增大,而焦耳热所产生的温度梯度对原子通量和通量散度增大的影响则相对有限.     

一种低成本的硅垂直互连技术

采用KOH刻蚀工艺制作硅垂直互连用通孔,淀积SiO2作为硅垂直互连的电绝缘层,溅射Ti和Cu分别作为Cu互连线的黏附层/扩散阻挡层和电镀种子层.电镀10μm厚的Cu作为硅垂直互连的导电层.为实现金属布线的图形化,在已有垂直互连的硅片上试验了干膜光刻工艺.采用化学镀工艺,在Cu互连线上沉积150～200 nm厚的NiMoP薄膜作为防止Cu腐蚀和Cu向其上层介质扩散的覆盖层.高温退火验证了Ti阻挡层和NiMoP覆盖层的可靠性.     

铜互连应力模拟分析

建立了三维有限元模型,采用ABAQUS有限元分析软件,模拟计算了Cu互连系统中的热应力分布;通过改变通孔直径、铜线余量、层间介质等,对比分析了互连结构对热应力分布的影响。结果表明,互连应力在金属线中通孔正下方铜线顶端处存在极小值,应力和应力梯度在下层铜线互连顶端通孔两侧处存在极大值。应力和应力梯度随着通孔直径或层间介质材料介电常数的减小而下降,应力随铜线余量长度的减小而增大。双通孔结构相对于单通孔结构而言,靠近下层金属线末端的通孔附近应力较大,但应力梯度较小。     

Diode lasers emitting at 3 μm with 300 mW of continuous-wave output power

Type-I double-quantum-well GaSb-based diode lasers operating at 3 mum with room-temperature continuous-wave output power above 300 mW and peak power-conversion efficiency near 8 were designed and fabricated. Laser heterostructure comprised quinary AlGaInAsSb alloy as barrier and waveguide material. Use of quinary alloy resulted in adequate hole confinement. The waveguide thickness was chosen to maximise modal differential gain. Continuous-wave threshold current density about 100 A/cm² per quantum-well and slope efficiency of 100 mW/A were demonstrated at 17degC.     

印刷电路板散热过孔导热率计算方法及优化

为了对电源设备的印刷电路板(PCB)散热过孔的导热性能做优化提高,推导了一套理论计算公式,采用数值仿真、实验测试的方法验证了该公式的可靠性。通过该理论计算公式,研究了散热过孔的孔径、填充的材料以及过孔镀铜厚度对导热率的影响。研究结果显示,过孔内孔直径为0.45 mm为最优直径;填充材料为FR4或者Rogers时没有明显的改善,但是如果用焊锡等高导热率的材质填充时导热率有明显的提高;过孔镀层厚度对导热率的影响非常大,呈线性的增长关系。采用该结果推荐的三种散热过孔优化方案,能使导热率分别提高6.5%,35%及51%。     

利用反应离子刻蚀实现GaAs晶片通孔工艺

贯穿晶片的背面通孔已成为ＧａＡｓＭＭＩＣ和功率ＭＥＳＦＥＴ的有效接地方式。本文介绍了利用Ｃｌ２／ＳｉＣｌ４作为反应气体，以正性光刻胶为掩模的反应离子刻蚀背孔工艺。利用该工艺刻蚀出的深孔具有倾斜的剖面和光滑的侧壁，孔的横向侧蚀小，在５０ｍｍＧａＡｓ圆片上获得了良好的均匀性和重复性。     

Highly efficient blue polyfluorenes using blending materials as hole transport layer

Efficient blue polyfluorenes have been generated by incorporating the hole transport material N-([1,1′-biphenyl]-4-yl)-9,9-dimethyl-N-(4-(9-phenyl-9H-carbazol-3-yl)- phenyl)-9H-fluoren-2-amine (BCFN) into poly(9,9-dioctylfluorene) (PFO) as an emissive layer. BCFN has an appropriate highest occupied molecular orbital (HOMO) energy level and high hole transport/electron barrier properties, which can effectively reduce the hole injection barrier and improve the charge carrier injection and transport. These properties resulted in a significant improvement in the electroluminescent (EL) performance of PFO. To further improve the EL performance of PFO, the blend hole transport layer, PVK [Poly(N-vinylcarbazole)]:BCFN with weight ratio of 3:7, was inserted between the PEDOT:PSS and the emissive layer. The blend hole transport layer effectively reduced exciton quenching and markedly decreased the hole injected barrier. A maximum luminous efficiency (LE_max) of 4.31 cd A⁻¹ was obtained with the CIE coordinates of (0.17, 0.13). The device maintained a LE_max of 4.27 cd A⁻¹ at a luminance of 1000 cd m⁻². In addition, stable EL spectra were obtained and were nearly identical when the applied voltage was increased from 5 to 11 V. These results indicate that blending the appropriate hole transport material can be an efficient method to improve device performance based on the large band gap of blue-lighting materials.     

双空穴注入层对有机电致蓝光器件性能的改善

CuI/CuPc被采用作为有机电致蓝光CBP:BCzVBi器件 的双空穴注入层。采用双空穴注入层后使得CBP:BCzVBi蓝光器件的启亮电压降低至 3.4 V,较采用CuPc单空穴注入层的CBP:BCzVBi蓝光器件低0.4 V。在驱动电流20 mA/cm²的情况下,与单空穴注入层器件 相比,采用该双空穴注入层结构使得器件电流效率提升约19%,亮度 增加约17%,驱动电压降低0.9 V。采用Fowler -Nordheim (F-N)隧穿注入理论对器件空穴注入电流的影响因素进行了分析,发现双空穴 注入层形成的能级台阶可以有效地改善发光器件的空穴注入效率,进而起到改善器件发光电 流效率和降低驱动电压的目的。     

Electromigration characteristics in dual-damascene copper interconnects by difference of via structures

In order to improve the interconnect performance, copper has been used as the interconnect material instead of aluminum. One of the advantages of using copper interconnects instead of aluminum is better electromigration (EM) performance and lower resistance for ultralarge-scale integrated (ULSI) circuits. Dual-damascene processes use different approaches at the via bottom for lowering the via resistance. In this study, the effect of a Ta/TaN diffusion barrier on the reliability and on the electrical performance of copper dual-damascene interconnects was investigated. A higher EM performance in copper dual-damascene structures was obtained in barrier contact via (BCV) interconnect structures with a Ta/TaN barrier layer, while a lower EM performance was observed in direct contact via (DCV) interconnect structures with a bottomless process, although DCV structures had lower via resistance compared to BCV structures. The EM failures in BCV interconnect structures were formed at the via, while those in DCV interconnect structures were formed in the copper line. The existence of a barrier layer at the via bottom was related to the difference of EM failure modes. It was confirmed that the difference in EM characteristics was explained to be due to the fact that the barrier layer at the via bottom enhanced the back stress in the copper line.     

An analytical subthreshold current modeling of cylindrical gate all around (CGAA) MOSFET incorporating the influence of device design engineering

An analytical model of CGAA MOSFET incorporating material engineering, channel engineering and stack engineering has been proposed and verified using ATLAS 3D device simulator. A comparative study of short channel effects for various device structures has also been carried out incorporating the effect of drain induced barrier lowering (DIBL), threshold voltage lowering and degradation of subthreshold slope. The effectiveness of applying the three region doping profile concept in the channel such as high-medium-low and low-high-low and its comparison with Gaussian doping profile to the cylindrical GAA MOSFET has been examined in detail. Reduced SCEs have been evaluated in combined designs i.e. TM–GC–GS, GCGS and DM–GC–GS. Out of several design engineering, GC–GS CGAA gives nearly ideal subthreshold slope whereas TM–GC–GS CGAA provides overall superior performance to reduce SCEs in deep nano-meter. The results so obtained are in good agreement with the simulated data which validate the model.     

垂直线不良分析与改善

针对栅极绝缘层和栅极引线接触处形成过孔倒角造成的一种垂直线不良进行分析和改善。研究气相沉积、干法刻蚀和磁控溅射对过孔倒角的影响,通过扫描电子显微镜对过孔形貌进行表征,并用成盒检测设备检测不良发生情况。实验结果表明:通过过孔刻蚀功率、气压、气体流量的变更可以消除倒角现象,垂直线不良由1.4%降为0.7%。     

Hole diffusion length in high purity n-GaAs

Measurements on high purity epitaxial n-GaAs surface barrier diodes with the scanning electron microscope have shown that the hole diffusion length is 200 ωm. This is in agreement with the value of hole lifetime calculated from Hall's theory of recombination processes. The lower values obtained in earlier work are attributed to the lower purity of the material used.     

Effect of anode material on high-field-induced hole current in SiO2 layer of metal-oxide-semiconductor field-effect transistor

The effects of three anode materials: polysilicon (semiconductor), aluminium and gold (metals) on hole currents in oxide layers of MOSFET's are presented for both thin (19 nm) and the thick (78 nm) oxide layers. Similar anode material effects were observed in both the thin and the thick oxide layers. The results suggest that anode hole generation plays the same role for both the thin and the thick oxide layers in our experiment. The larger the anode electron barrier height, the larger the hole current generation efficiency. The observable anode material effect decreases with increase of oxide electric field. When the oxide electric field is larger than 10 MV/cm, the observable anode material effect disappears. Our results show that the anode hole generation is the dominant mechanism on both the thin and thick oxide layers for oxide electric fields smaller than 10 MV/cm. For oxide electric fields larger than 10 MV/cm, further analysis is needed to identify the dominant mechanism of high-field-induced oxide hole currents