微电子学、集成电路

TN4TN015 01040497集成电路矩形互连线二维电容及随频率变化电感的联合计算方法/方蜀州,汤小波,王泽毅,洪先龙(清华大学计算机科学与技术系)刀计算机辅助设计与图形学学报.一2000,12(12),一887一890提出一种电容电感联合算法,可计算全频率范围内随频率变化的电感,同时得到电容矩阵.该算法利用电路模型法得到低颇{、若卜频率的电感值;利用边界元法得到电容矩阵,并对电容知阵求逆得到电流完全分布在导体表面时的电感值,由集肤深)划导到该电感值对应的频率.对上述离散频率的电感值利用三次徉条函数插值,得到整个频率范围内电感的变化曲线算法…     

Buck-Boost变换器的能量传输模式 及输出纹波电压分析

根据电感电流最小值与输出电流的比较,将Buck-Boost 变换器的能量传输模式(ETM)分为完全电感供能模式(CISM)和不完全电感供能模式(IISM),得出了CISM和IISM的临界条件和临界电感.将电感电流最小值与零和输出电流进行比较,得出Buck-Boost 变换器存在三种工作模式,即CISM、不完全电感供能且连续导电模式(IISM-CCM)和不完全电感供能且不连续导电模式(IISM-DCM).推导出了变换器工作于三种模式时的输出纹波电压表示式,指出对于给定负载、电容和开关频率的Buck-Boost变换器,CISM的输出纹波电压最小且与电感无关,而IISM-CCM和IISM-DCM的输出纹波电压较大且随电感减小而增大.CISM和IISM的临界电感即为使得变换器的输出纹波电压最低的最小电感.文中给出实例,实验结果与理论分析一致,但因未考虑器件参数输出纹波电压略高于理论分析值,实验结果验证了理论分析的正确性.     

基板锚定特性对液晶盒电容的影响

基板的锚定特性,包括锚定能大小和锚定易取方向,影响液晶指向矢的分布,直接导致液晶盒电容的改变,因此可以通过液晶盒电容的测量确定基板表面的锚定特性。基于液晶弹性理论和变分原理,理论推导弱锚定平行排列向列相和混合排列向列相液晶盒系统的平衡态方程和边界条件,采用差分迭代方法数值模拟得到了液晶盒约化电容随电压、锚定能系数及锚定易取方向变化的曲线。结果表明:液晶盒电容随基板锚定能系数的增加而减小;随预倾角的增加,液晶盒电容随锚定能系数的变化缩小;同一电压和基板锚定能系数下,平行排列向列相液晶盒电容不会大于混合排列向列相液晶的电容。     

重复频率脉冲氙灯电流中两个问题的研究

本文讨论主回路放电规律和趋肤效应对放电的影响问题.一、电容充电结束后,通过电感、氙灯的放电规律。电容、电感、氙灯串联谐振时,电流变化规律已有简要论述,然而细节问题尚未详尽交待.我们用数字解法计算了16种不同条件下的电容、电感、氙灯串联回路中放电的电流、电感、电压随时间变化规律。放电方程为     

关于电容电压和电感电流跃变的讨论

本文针对电路教科书指出的有两种情况可能会出现冲激电流和冲激电压的情况,通过举例说明,电容电压和电感电流的跃变可以在多种情况下发生。笔者还讨论了电容电压和电感电流跃变与换路定律之间的关系,即电容电压和电感电流跃变是对实际电路理想化建模的结果。本文通过实例指出正确理解电容电压和电感电流的跃变,有助于简化电路的分析。     

应用纳米材料添加剂制备高压高能压敏电阻

为了解决高压型压敏电阻与高能型压敏电阻应用上的“死区“,提出添加纳米材料进行压敏电阻改性实验研究,制得高压高能型压敏电阻,将能大幅度提高电压梯度、非线性系数和能量密度.     

普遍意义下介观RLC并联电路的量子化及在真空态下的量子涨落

对具有普遍意义的介观RLC并联电路进行量子化并对各支路电流与电压的量子涨落进行研究, 同时分析耗散电阻对两个支路的量子涨落所产生的影响. 结果表明:各支路的量子涨落均与电路元件的参数有关并且随时间而衰减; 而耗散电阻对电感支路和电容支路量子涨落的衰减因子及其系数均产生影响, 对两个支路电流与电压的量子涨落的衰减因子产生的影响相同, 而对其系数产生的影响不同.当电感支路与电容支路的耗散电阻相同时, 两个支路的电压涨落与耗散电阻有关, 而电流涨落不受耗散电阻的影响.     

海森堡对应原理在含时介观耦合电路中的应用

对于一般形式的含时电容和电感耦合电路，利用Heisenberg对应原理研究了体系的量子经典对应关系以及量子涨落。通过海森堡绘景中的波函数和运动方程的精确解，在大量子数极限下由量子解得到了经典解。对矩阵元中初始相位求平均得到了体系中电荷和磁通量的量子涨落。当电路中的电感随时间指数增加，而电容指数减小时，电路中的电荷和电流的量子涨落也随时间指数减小；当两个分回路中的电容和电感不随时间变化且相等时，发现耦合电容趋于减小电流的量子涨落，而耦合电感趋于减小电荷的量子涨落。     

3.7 GHz宽带CMOS LC VCO的设计

设计了一款3.7 GHz宽带CMOS电感电容压控振荡器.采用了电容开关的技术以补偿工艺、温度和电源电压的变化,并对片上电感和射频开关进行优化设计以得到最大的Q值.电路采用和舰0.18 μm CMOS混合信号制造工艺,芯片面积为0.4 mm×1 mm.测试结果显示,芯片的工作频率为3.4～4 GHz,根据输出频谱得到的相位噪声为-100 dBc/Hz@1 MHz,在1.8 V工作电压下的功耗为10 mW.测试结果表明,该VCO有较大的工作频率范围和较低的相位噪声性能,可以用于锁相环和频率合成器.     

电容电流(或电感电压)中的冲激分量计算方法

众所周知,当电容电压(或电感电流)在换路时刻发生跃变时,其电容电流(或电感电压)中包含有冲激分量.那么如何正确地求出这些冲激分量呢?例如一般求电容电流时,可对电容电压的表达式求导而得,但利用这种方法有时并不能正确地求出电容电流中的冲激分量.例如利用三要素法可求出电容电压的表达式为     

基于电流控制传送器的电可调梯形滤波器

利用电流控制传送器（CCCII）实现浮地和接地电感，而无源器件只有接地电容，通过调制CCCII的偏置电流，可以调整等效电感的大小。使用这种等效电感来设计5阶梯形Butterworth低通和高通滤波器时使用较少的无源器件，并且中心频率具有电可调性。进行PSPICE分析，仿真结果表明设计是可行的。     

Cutoff frequency of microwave coaxial multimode limiter

Broad-band microwave diode limiters are realized in a coaxial low-pass filter structure. It is shown here that there is a cutoff frequency of the coaxial limiter above which the limiter will not function as a limiter. The cutoff frequency depends on diode package inductance, package capacitance, and the capacitances of the coaxial structure used to realize the limiter.     

Analysis of a low-pass filter employing a 4-pin capacitor

Capacitors with two or three leads tend to make poor low-pass filters at high frequencies (e.g., >100 MHz) due to the mutual inductance between the input and output sides of the filter. This work proposes a four-lead low-pass filter capacitor design that minimizes the magnetic flux coupling between the input and output. Measurements of a prototype capacitor confirm that it performs significantly better than a typical two-lead capacitor at high frequencies.     

Wide-band amplifiers for television

The maximum uniform amplification that can be secured over a wide frequency band by means of a single vacuum tube is much greater than that of the usual simple circuits. It can be secured by either of two arrangements, one using an individual filter coupling each tube to the next, and the other using degenerative feedback in each stage to make the stage behave as a section of a confluent filter. In either case, the shunt capacitance on each side of each tube is included in an individual full-shunt arm of a band-pass or low-pass filter. One end of each interstage filter, or of each filter including one or more feedback stages, is extended to a dead-end termination with resistance approximately matching the image impedance. The other end is terminated at one of the tubes in a full-shunt arm, where the filter presents the maximum uniform impedance that can be built up across the tube capacitance. These concepts in terms of wave filters lead to practical wide-band circuits adapted to meet any given requirements. The following general formula is shown to express the maximum uniform amplification that can be secured in one tube: A = gm/πfw√CgCpin which A is the voltage ratio between input and output circuits of equal impedance, gmis the transconductance of the tube, Cgand Cpare the grid and plate capacitance of the tube, and fwis the width of the frequency band.     

Current-Fed Dual-Bridge DC–DC Converter

A new isolated current-fed pulsewidth modulation dc-dc converter-current-fed dual-bridge dc-dc converter-with small inductance and no deadtime operation is presented and analyzed. The new topology has more than 3times smaller inductance than that of current-fed full-bridge converter, thus having faster transient response speed. Other characteristics include simple self-driven synchronous rectification, simple housekeeping power supply, and smaller output filter capacitance. Detailed analysis shows the proposed converter can have either lower voltage stress on all primary side power switches or soft switching properties when different driving schemes are applied. A 48-V/125-W prototype dc-dc converter with dual output has been tested for the verification of the principles. Both simulations and experiments verify the feasibility and advantages of the new topology     

Overvoltage suppression filter design methods based on voltage reflection theory

To reduce voltage overshoot at the motor terminal, RLC filters are used at the inverter side with an objective of increasing the rise time, while RC filters are used at the motor side as a means of reducing the load impedance at high frequency. However, no clear optimal method for determining the filter parameters has appeared. In this work, we propose filter design methods that fully utilize given conditions such as cable length, cable inductance, cable capacitance, and the reflection coefficient at the inverter side. For determining the parameters of the RLC filter, the filter transfer function is utilized to make the rise time long enough to achieve desirable overshoot level at motor terminals. In choosing the parameters of the RC filter, the reflection coefficient is regarded as a transfer function between the incident and reflected voltages, and the capacitance is chosen so that cancellation occurs between the reflected voltage and its resulting incident voltage. The validity of the proposed design method is supported by simulation results, which are also compared with the experimental results.     

Analysis of simple two-capacitor low-pass filters

The performance of typical low-pass capacitor filters is limited by the mutual inductance between the input and output sides of the filter. This paper describes how two appropriately spaced capacitors can be used to construct a low-pass filter with significantly better high-frequency performance than a one-capacitor filter. Laboratory measurements and numerical simulations are used to quantify the mutual inductance and compare the performance of one- and two-capacitor low-pass filters.     

二阶压控电压源低通滤波器设计

本文详细介绍二阶压控电压源低通滤波器的设计方法,给出了其通用表达式。设计方法是根据所需转折频率,在1:2至1:10较宽的范围内灵活取两电容值,再计算出与灵活选取的电容准确匹配的电阻阻值。相对于查表法、图示法取值更具灵活性和实用性,由于不需要精确匹配成本较高的电容,此方法还具有成本较低的优势。用Multisim-10仿真软件对所设计的二阶压控电压源低通滤波器进行模拟仿真,结果表明与理论计算符合得很好。     

Compact distributed RLC interconnect models-Part II: Coupled linetransient expressions and peak crosstalk in multilevel networks

For pt. I see ibid., vol. 47, no. 11, (Nov. 2000). Novel compact expressions that describe the transient response of high-speed resistance, inductance, and capacitance (RLC) coupled interconnects are rigorously derived. These new distributed rlc models reveal that peak crosstalk voltage is over 60% larger for 3 GHz high-speed interconnects than predicted by current distributed RC models. Simplified forms of the compact models enable physical insight and accurate estimation of peak crosstalk voltage between two and three distributed RLC interconnects     

Voltage Regulator Optimization Using Multiwinding Coupled Inductors and Extended Duty Ratio Mechanisms

This paper examines design optimization of voltage regulators (VRs) for microprocessor applications. Optimality of competing VR topologies, such as conventional (Conv) buck, coupled inductor, and extended duty ratio converters, is examined using efficiency norms and a new cost-per-watt metric to compare the amount of output capacitance (which is strongly correlated to the VR cost) to the efficiency. Coupled inductors provide a higher steady-state inductance than transient inductance. Lower transient inductance allows for smaller output capacitance. However, lower output capacitance requires a higher switching frequency and thus yields greater switching losses and lower efficiency. Extended duty ratio mechanisms reduce the switching voltage, and hence, reduce switching losses and increase efficiency. Experimental data are provided that the coupled inductor extended duty ratio converter has the same average efficiency, has higher light-load efficiency, and uses one-third of the output capacitance as the Conv multiphase buck converter. Hence, the combination of multiwinding coupled inductors and extended duty ratio mechanisms is shown to be the optimal VR configuration. The optimality concepts contributed in this paper resolve the ambiguity between VR cost and efficiency, and are essential for selecting the best solution among several competing VR designs.