Finite-length rate-compatible LDPC codes: a novel puncturing scheme - [transactions letters]

In this paper, we study rate-compatible puncturing of finite-length low-density parity-check (LDPC) codes. We present a novel rate-compatible puncturing scheme that is easy to implement. Our scheme uses the idea that the degradation in performance is reduced by selecting a puncturing pattern wherein the punctured bits are far apart from each other in the Tanner graph of the code. Although the puncturing scheme presented is tailored to regular codes, it is also directly applicable to irregular parent ensembles. By simulations, the proposed rate-compatible puncturing scheme is shown to be superior to the existing puncturing methods for both regular and irregular LDPC codes over the binary erasure channel (BEC) and the additive white Gaussian noise (AWGN) Channel.     

中长帧非规则LDPC码译码器的FPGA实现

LDPC(低密度奇偶校验码)是一种优秀的线性分组码,是目前距香农限最近的一类纠错编码。与Turbo码相比,LDPC码能得到更高的译码速度和更好的误码率性能,从而被认为是下一代通信系统和磁盘存储系统中备选的纠错编码。简要介绍了适于硬件实现的LDPC码译码算法,并基于软判决译码规则,使用Verilog硬件描述语言,在X ilinx V irtex2 6000 FPGA上实现了码率为1/2、帧长504bit的非规则LDPC码译码器。     

On construction of rate-compatible low-density Parity-check codes

In this letter, we present a framework for constructing rate-compatible low-density parity-check (LDPC) codes. The codes are linear-time encodable and are constructed from a mother code using puncturing and extending. Application of the proposed construction to a type-II hybrid automatic repeat request (ARQ) scheme with information block length k=1024 and code rates 8/19 to 8/10, using an optimized irregular mother code of rate 8/13, results in a throughput which is only about 0.7 dB away from Shannon limit. This outperforms existing similar schemes based on turbo codes and LDPC codes by up to 0.5 dB.     

Results on Punctured Low-Density Parity-Check Codes and Improved Iterative Decoding Techniques

This paper first introduces an improved decoding algorithm for low-density parity-check (LDPC) codes over binary-input-output-symmetric memoryless channels. Then some fundamental properties of punctured LDPC codes are presented. It is proved that for any ensemble of LDPC codes, there exists a puncturing threshold. It is then proved that for any rates R₁ and R₂ satisfying 012<1, there exists an ensemble of LDPC codes with the following property. The ensemble can be punctured from rate R₁ to R₂ resulting in asymptotically good codes for all rates R₁lesRlesR₂. Specifically, this implies that rates arbitrarily close to one are achievable via puncturing. Bounds on the performance of punctured LDPC codes are also presented. It is also shown that punctured LDPC codes are as good as ordinary LDPC codes. For BEC and arbitrary positive numbers R₁2<1, the existence of the sequences of punctured LDPC codes that are capacity-achieving for all rates R₁ lesRlesR₂ is shown. Based on the above observations, a method is proposed to design good punctured LDPC codes over a broad range of rates. Finally, it is shown that the results of this paper may be used for the proof of the existence of the capacity-achieving LDPC codes over binary-input-output-symmetric memoryless channels     

具有不等错误保护特性的LDPC 编码调制方案

针对LDPC（low-density parity-check）编码调制系统，提出了一种新的具有不等错误保护特性的调制方案，在一个码字内，利用不同的调制方式对于重要的比特给予较强的保护，对于次要的比特给予较弱的保护，该方案既适用于非规则LDPC码，也适用于规则LDPC码。计算机仿真结果表明，新方案的性能是传统16QAM及4QAM的折衷，当采用1／2码率时，其频带利用率与8PSK相同，但是误码率性能优于8PSK。新方案的性能优于现有文献中基于比特可靠性的调制映射方案，并采用EXIT（extrinsic information transfer）图对新方案的优异性能给出了解释。     

非规则LDPC码的不等错误保护性能研究

提出了一种具有不等错误保护性能的非规则低密度校验(LDPC,low-density parity-check)码信道编码方案, 构造了重量递增校验(weight-increasing parity-check)矩阵,系统编码时,重要信息比特映射到LDPC码的“精华”比特上。AWGN和Rayliegh衰落信道的仿真结果表明,与随机构造的非规则LDPC码相比,WICP-LDPC码具有好的UEP性能。     

Rate-compatible puncturing of low-density parity-check codes

In this correspondence, we consider puncturing of low-density parity-check (LDPC) codes for additive white Gaussian noise (AWGN) channels. We show that good puncturing patterns exist and that the puncturing can be performed in a rate-compatible fashion. Furthermore, rate-compatible puncturing results in a small loss of performance with respect to threshold, namely, the punctured code is good (in terms of threshold) across a range of rates when compared with the optimal codes for each rate. This allows one to implement a single "mother" encoder and decoder that is good across a wide range of rates.     

Optimized low-density parity-check codes for partial response channels

We optimize irregular low-density parity-check (LDPC) codes to closely approach the independent and uniformly distributed (i.u.d.) capacities of partial response channels. In our approach, we use the degree sequences optimization method for memoryless channels proposed by Richardson, Shokrollahi, and Urbanke and appropriately modify it for channels with memory. With this optimization algorithm we construct codes whose noise tolerance thresholds are within 0.15 dB of the i.u.d. channel capacities. Our simulation results show that irregular LDPC codes with block lengths 10/sup 6/ bits yield bit error rates 10/sup -6/ at signal-to-noise ratios 0.22 dB away from the channel capacities.     

Design of rate-compatible structured LDPC codes for hybrid ARQ applications

In this paper, families of rate-compatible protograph-based LDPC codes that are suitable for incrementalredundancy hybrid ARQ applications are constructed. A systematic technique to construct low-rate base codes from a higher rate code is presented. The base codes are designed to be robust against erasures while having a good performance on error channels. A progressive node puncturing algorithm is devised to construct a family of higher rate codes from the base code. The performance of this puncturing algorithm is compared to other puncturing schemes. Using the techniques in this paper, one can construct a rate-compatible family of codes with rates ranging from 0.1 to 0.9 that are within 1 dB from the channel capacity and have good error floors.     

Accumulate-Repeat-Accumulate Codes

In this paper, we propose an innovative channel coding scheme called accumulate-repeat-accumulate (ARA) codes. This class of codes can be viewed as serial turbo-like codes or as a subclass of low-density parity check (LDPC) codes, and they have a projected graph or protograph representation; this allows for high-speed iterative decoding implementation using belief propagation. An ARA code can be viewed as precoded repeat accumulate (RA) code with puncturing or as precoded irregular repeat accumulate (IRA) code, where simply an accumulator is chosen as the precoder. The amount of performance improvement due to the precoder will be called precoding gain. Using density evolution on their associated protographs, we find some rate-1/2 ARA codes, with a maximum variable node degree of 5 for which a minimum bit SNR as low as 0.08 dB from channel capacity threshold is achieved as the block size goes to infinity. Such a low threshold cannot be achieved by RA, IRA, or unstructured irregular LDPC codes with the same constraint on the maximum variable node degree. Furthermore, by puncturing the inner accumulator, we can construct families of higher rate ARA codes with thresholds that stay close to their respective channel capacity thresholds uniformly. Iterative decoding simulation results are provided and compared with turbo codes. In addition to iterative decoding analysis, we analyzed the performance of ARA codes with maximum-likelihood (ML) decoding. By obtaining the weight distribution of these codes and through existing tightest bounds we have shown that the ML SNR threshold of ARA codes also approaches very closely to that of random codes. These codes have better interleaving gain than turbo codes     

Design of Rate-Compatible Irregular Repeat Accumulate Codes

We consider the design of efficient rate-compatible (RC) irregular repeat accumulate (IRA) codes over a wide code rate range. The goal is to provide a family of RC codes to achieve high throughput in hybrid automatic repeat request (ARQ) scheme for high-speed data packet wireless systems. As a subclass of low-density parity-check codes, IRA codes have an extremely simple encoder and a low-complexity decoder while providing capacity approaching performance. We focus on a hybrid design method which employs both puncturing and extending. We propose a simple puncturing method based on minimizing the maximal recoverable step of the punctured nodes. We also propose a new extending scheme for IRA codes by introducing the degree-1 parity bits for the lower rate codes and obtaining the optimal proportions of extended nodes through density evolution analysis. The throughput performance of the designed RC-IRA codes in hybrid ARQ is evaluated for both AWGN and block fading channels. Simulation results demonstrate that our designed RC codes offer good error correction performance over a wide rate range and provide high throughput, especially in the high and low signal-to-noise ratio regions.     

关于非规则LDPC码的基于度分布HARQ性能研究

该文提出了一种非规则LDPC码字基于度分布HARQ技术的改进方案。该方案在选择重传信息的过程中,不仅考虑了节点度分布的影响,而且考虑了非规则LDPC码字自身的不均等错误保护特性。与原始的基于度分布的HARQ方案相比,该方案使系统的误比特率和吞吐量指标得到了明显改善。     

Low-density parity-check codes for space-time wireless transmission

Irregular low-density parity-check (LDPC) codes have shown exceptionally good performance for single antenna systems over a wide class of channels. In this paper, we investigate their application to multiple antenna systems in flat Rayleigh fading channels. For small transmit arrays, we focus mainly on space-time coding with 2/sup p/-ary LDPC codes, where p equals the number of encoded bits transmitted by the transmit antenna array during each signaling interval. For large transmit arrays, we study a layered space-time architecture using binary LDPC codes as component codes of each layer: We show through simulation that, when applied to multiple antenna systems with high diversity order, LDPC codes of quasi-regular construction are able to achieve higher coding gain and/or diversity gain than previously proposed space-time trellis codes, space-time turbo codes, and convolutional codes in a number of fading conditions. Extending the work of density evolution with Gaussian approximation, we study 2/sup p/-ary LDPC codes on multiple antenna fading channels, and search for the optimum 2/sup p/-ary quasi-regular codes in quasi-static fading. We also show that on fast fading channels, 2/sup p/-ary irregular LDPC codes, though designed for static channels, have superior performance to nonbinary quasiregular codes and binary irregular codes specifically designed for fast fading channels.     

Performance analysis and code optimization of low densityparity-check codes on Rayleigh fading channels

A numerical method has been presented to determine the noise thresholds of low density parity-check (LDPC) codes that employ the message passing decoding algorithm on the additive white Gaussian noise (AWGN) channel. In this paper, we apply the technique to the uncorrelated flat Rayleigh fading channel. Using a nonlinear code optimization technique, we optimize irregular LDPC codes for such a channel. The thresholds of the optimized irregular LDPC codes are very close to the Shannon limit for this channel. For example, at rate one-half, the optimized irregular LDPC code has a threshold only 0.07 dB away from the capacity of the channel. Furthermore, we compare simulated performance of the optimized irregular LDPC codes and turbo codes on a land mobile channel, and the results indicate that at a block size of 3072, irregular LDPC codes can outperform turbo codes over a wide range of mobile speeds     

Early detection of successful decoding for dual-diagonal block-based LDPC codes

Low-density parity-check (LDPC) codes [1] have attracted much attention in the last decade owing to their capacityapproaching performance. LDPC codes with a dual-diagonal blockbased structure can be encoded in linear time with lower encoder hardware complexity [2]. This class of LDPC codes is adopted by a number of standards such as wireless LAN (IEEE 802.11n) [3], wireless MAN (IEEE 802.16e, WiMAX) [4] and satellite TV (DVB-S2) [5]. LDPC codes are commonly decoded by the iterative belief-propagation (BP) algorithm. The decoder checks the parity-check equations to detect successful decoding at the end of the iteration. The Tanner graph of an irregular LDPC code consists of nodes with different degrees such that coded bits have unequal error protection [6]. Coded bits associated with higher degree nodes tend to converge to the correct answer more quickly. Hence, in order to give better protection to the transmitted data, data bits are always mapped to higher degree nodes whereas parity bits are mapped to lower degree nodes in the encoding process. The commonly used parity-check equations Hc t ? 0t will be satisfied after all the coded bits are correctly decoded. However, as discussed above, data bits converge to the correct answer much more quickly than parity bits, so some unnecessary iterations are wasted waiting for the parity bits to be decoded. In this Letter, a new set of low-complexity check equations are derived for dual-diagonal block-based LDPC codes. Early detection of successfully decoded data can be achieved by exploiting the structure and degree of distribution of the dual-diagonal parity check matrix. The decoder power, speed and complexity can be improved by adopting these equations. Simulation shows that the coding gain performance is little changed.     

Scalable image and video transmission using irregular repeat-accumulate codes with fast algorithm for optimal unequal error protection

This paper considers designing and applying punctured irregular repeat-accumulate (IRA) codes for scalable image and video transmission over binary symmetric channels. IRA codes of different rates are obtained by puncturing the parity bits of a mother IRA code, which uses a systematic encoder. One of the main ideas presented here is the design of the mother code such that the entire set of higher rate codes obtained by puncturing are good. To find a good unequal error protection for embedded bit streams, we employ the fast joint source-channel coding algorithm in Hamzaoui et al. to minimize the expected end-to-end distortion. We test with two scalable image coders (SPIHT and JPEG-2000) and two scalable video coders (3-D SPIHT and H.26L-based PFGS). Simulations show better results with IRA codes than those reported in Banister et al. with JPEG-2000 and turbo codes. The IRA codes proposed here also have lower decoding complexity than the turbo codes used by Banister et al.     

HIGH-PERFORMANCE SIMPLE-ENCODING GENERATOR-BASED SYSTEMATIC IRREGULAR LDPC CODES AND RESULTED PRODUCT CODES

Low-Density Parity-Check (LDPC) code is one of the most exciting topics among the coding theory community.It is of great importance in both theory and practical communications over noisy channels.The most advantage of LDPC codes is their relatively lower decoding complexity compared with turbo codes,while the disadvantage is its higher encoding complexity.In this paper,a new ap- proach is first proposed to construct high performance irregular systematic LDPC codes based on sparse generator matrix,which can significantly reduce the encoding complexity under the same de- coding complexity as that of regular or irregular LDPC codes defined by traditional sparse parity-check matrix.Then,the proposed generator-based systematic irregular LDPC codes are adopted as con- stituent block codes in rows and columns to design a new kind of product codes family,which also can be interpreted as irregular LDPC codes characterized by graph and thus decoded iteratively.Finally, the performance of the generator-based LDPC codes and the resultant product codes is investigated over an Additive White Gaussian Noise (AWGN) and also compared with the conventional LDPC codes under the same conditions of decoding complexity and channel noise.     

Power- and bandwidth-efficient communications using LDPC codes

We apply low-density parity-check (LDPC) codes to a bandwidth-efficient modulation scheme using multilevel coding, multistage decoding, and trellis-based signal shaping. Performance results based on density evolution and simulations are presented. Using irregular LDPC component codes of block length 10/sup 5/ and a 64-quadrature amplitude modulation signal constellation operating at 2 bits/dimension, a bit-error rate of 10/sup -5/ is achieved at an E/sub b//N/sub 0/ of 6.55 dB. At this value of E/sub b//N/sub 0/, the Shannon channel capacity, computed assuming equally likely signaling, is below 2 bits/dimension.     

LDPC码在802.16a协议中的应用

基于LDPC码的优越性能，找出一组优秀的非正则LDPC码应用于IEEE802．16a OFDM环境中，并对其性能进行仿真。仿真结果表明，LDPC码在衰落信道下具有良好的纠错能力，适用于WMAN等采用OFDM的无线通信系统。     

Efficient GPU and CPU-based LDPC decoders for long codewords

The next generation DVB-T2, DVB-S2, and DVB-C2 standards for digital television broadcasting specify the use of low-density parity-check (LDPC) codes with codeword lengths of up to 64800 bits. The real-time decoding of these codes on general purpose computing hardware is useful for completely software defined receivers, as well as for testing and simulation purposes. Modern graphics processing units (GPUs) are capable of massively parallel computation, and can in some cases, given carefully designed algorithms, outperform general purpose CPUs (central processing units) by an order of magnitude or more. The main problem in decoding LDPC codes on GPU hardware is that LDPC decoding generates irregular memory accesses, which tend to carry heavy performance penalties (in terms of efficiency) on GPUs. Memory accesses can be efficiently parallelized by decoding several codewords in parallel, as well as by using appropriate data structures. In this article we present the algorithms and data structures used to make log-domain decoding of the long LDPC codes specified by the DVB-T2 standard??at the high data rates required for television broadcasting??possible on a modern GPU. Furthermore, we also describe a similar decoder implemented on a general purpose CPU, and show that high performance LDPC decoders are also possible on modern multi-core CPUs.