A bipolar four-quadrant analog quarter-square multiplier consistingof unbalanced emitter-coupled pairs and expansions of its input ranges

A bipolar four-quadrant analog multiplier based on the quarter-square technique, which is constituted from unbalanced emitter-coupled pairs, and some methods for extending the input voltage range, are described. The building blocks for the circuit consist of an unbalanced emitter-coupled pair with different emitter areas, an emitter-coupled pair with an input bias offset, and an unbalanced emitter-coupled pair with unbalanced emitter degeneration. A basic squaring circuit is realized from two identical unbalanced emitter-coupled pairs with emitter area ratio K and cross-coupled inputs and parallel-connected outputs. The quarter-square multipliers proposed in this paper can operate under low supply voltage (typically <3 V, and a minimum of 1 V). Therefore, the Gilbert multiplier, which has been the most popular analog multiplier in bipolar technology over the past few decades, can be replaced     

Design of a low-power, high performance, 8×8 bit multiplier using a Shannon-based adder cell

In this paper, we have developed a new full-adder cell using multiplexing control input techniques (MCIT) for the sum operation and the Shannon-based technique to implement the carry. The proposed adder cell is applied to the design of several 8-bit array multipliers, namely a Braun array multiplier, a CSA multiplier, and Baugh–Wooley multipliers. The multiplier circuits are designed using DSCH2 VLSI CAD tools and their layouts are generated by Microwind 3 VLSI CAD tools. The output parameters such as propagation delay, total chip area, and power dissipation are calculated from the simulated results. We have also calculated energy per instruction (EPI), throughput, latency, signal-to-noise ratio (SNR), and the effect of temperature on the drain current by using the generated layout output parameter of a BSIM 4 advanced analyzer. The simulated results of the proposed adder-based multiplier circuit are compared with a cell multiplier that utilizes a MCIT-based adder, a cell multiplier composed of complementary pass transistor logic-based (CPL) adders and those of other published multipliers circuits. From the analysis of these simulated results, it was found that the proposed multiplier circuit gives better performance in terms of power, propagation delay, latency and throughput than other published results.     

Digit-Serial Complex-Number Multipliers on FPGAs

This paper presents an optimized implementation on FPGA of digit-serial Complex-Number Multipliers (CMs) using Booth recoding techniques and tree adders based on Carry Save (CS) and Ripple Carry Adders (RCA). This kind of Complex-Number multipliers can be pipelined at the same level independent of the digit-size. Variable and fixed coefficient CMs have been considered. In the first case an efficient mapping of the modified Booth recoding and the partial product generation is presented which results in a logic depth reduction. The combination of 5:3 and 4:3 converters in the CS structure and the utilization of RCA trees lead to a minimum area requirement. In the case of fixed coefficient CMs, partial products generator is based on look-up tables and multi-bit Booth recoding is used to reduce the area and increase the performance of the circuit. The study reveals that efficient mapping of the 5-bit Booth recoding to generate the partial products is the optimum multibit recoding when Xilinx FPGA devices are used.     

An efficient and high-speed VLSI implementation of optimal normal basis multiplication over GF(2m)

Finite field multiplication is one of the most important operations in the finite field arithmetic and the main and determining building block in terms of overall speed and area in public key cryptosystems. In this work, an efficient and high-speed VLSI implementation of the bit-serial, digit-serial and bit-parallel optimal normal basis multipliers with parallel-input serial-output (PISO) and parallel-input parallel-output (PIPO) structures are presented. Two general multipliers, namely, Massey–Omura (MO) and Reyhani Masoleh–Hassan (RMH) are considered as case study for implementation. These multipliers are constructed by using AND, XOR–AND and XOR tree components. In the MO multiplier, to have strong input signals and have a better implementation, the row of AND gates are implemented by using inverter and NOR components. Also the XOR–AND component in the RMH structure is implemented using a new low-cost structure. The XOR tree in both multipliers consists of a high number of logic stages and many inputs; therefore, to optimally decrease the delay and increase the drive ability of the circuit for different loads, the logical effort method is employed as an efficient method for sizing the transistors. The multipliers are first designed for different load capacitances using different structures and different number of stages. Then using the logical effort method and a new proposed 4-input XOR gate structure, the circuits are modified for acquiring minimum delay. Using 0.18 μm CMOS technology, the bit-serial, digit-serial and bit-parallel structures with type-1 and type-2 optimal normal basis are implemented over the finite fields GF(2²²⁶) and GF(2²³³) respectively. The results show that the proposed structures have better delay and area characteristics compared to previous designs.     

Highly efficient, limited range multipliers for LUT-based FPGA architectures

A novel design technique for deriving highly efficient multipliers that operate on a limited range of multiplier values is presented. Using the technique, Xilinx Virtex field programmable gate array (FPGA) implementations for a discrete cosine transform and poly-phase filter were derived with area reductions of 31%-70% and speed increases of 5%-35% when compared to designs using general-purpose multipliers. The technique gives superior results over other fixed coefficient methods and is applicable to a range of FPGA technologies.     

Two quadrant analogue squarer circuit based on MOS square-law characteristic

A novel analogue CMOS circuit is presented which performs the arithmetical squaring of a voltage, using the square-law characteristic of the MOS transistor in saturation. The core circuit is constructed from four identical building blocks, which are connected so as to eliminate all unwanted offset terms. Simulation results from HSPICE are presented where the circuit is used for doubling the frequency of a sinusoidal input.<>     

Design of highly efficient elliptic curve crypto-processor with two multiplications over GF（2^163）

In this article, a parallel hardware processor is presented to compute elliptic curve scalar multiplication in polynomial basis representation. The processor is applicable to the operations of scalar multiplication by using a modular arithmetic logic unit (MALU). The MALU consists of two multiplications, one addition, and one squaring. The two multiplications and the addition or squaring can be computed in parallel. The whole computations of scalar multiplication over GF(2163) can be performed in 3 064 cycles. The simulation results based on Xilinx Virtex2 XC2V6000 FPGAs show that the proposed design can compute random GF(2163) elliptic curve scalar multiplication operations in 31.17 μs, and the resource occupies 3 994 registers and 15 527 LUTs, which indicates that the crypto-processor is suitable for high-performance application.     

基于FPGA的色彩空间双向转换电路设计

RGB和YUV色彩空间的转换电路广泛应用于视频、图像的压缩和传输中。为减小RGB和YUV色彩空间转换电路的芯片面积,通过采用可编程逻辑器件中嵌入的PLL(Phase Locked Loop)和流水线算法,复用矩阵乘法器结构,只需单一模块电路便可以实现RGB和YUV色彩空间的双向转换。结果表明电路设计只需3个乘法器和3个加法器,最大工作频率达到105.89 MHz。因此,该设计在满足高清数据传输的情况下,大幅节省了芯片面积。     

Series Expansion based Efficient Architectures for Double Precision Floating Point Division

Floating point division is a complex operation among all floating point arithmetic; it is also an area and a performance dominating unit. This paper presents double precision floating point division architectures on FPGA platforms. The designs are area optimized, running at higher clock speed, with less latency, and are fully pipelined. Proposed architectures are based on the well-known Taylor series expansion, using relatively smaller amount of hardware in terms of memory (initial look-up table), multiplier blocks, and slices. Two architectures have been presented with various trade-offs among area, memory and accuracy. Designs are based on the use of the partial block multipliers, in order to reduce hardware usage while minimizing the loss of accuracy. All the implementations have been targeted and optimized separately for different Xilinx FPGAs to exploit their specific resources efficiently. Compared to previously reported literature, the proposed architectures require less area, reduced latency, with the advantage of higher performance gain. The accuracy of the designs has been both theoretically analyzed and validated using random test cases.     

Finite field inversion over the dual basis

In this transaction brief we consider the design of dual basis inversion circuits for GF(2^m). Two architectures are presented-one bit-serial and one bit-parallel-both of which are based on Fermat's theorem. Finite field inverters based on Fermat's theorem have previously been presented which operate over the normal basis and the polynomial basis. However there are two advantages to be gained by forcing inversion circuits to operate over the dual basis. First, these inversion circuits can be utilized in circuits using hardware efficient dual basis multipliers without any extra basis converters. And second, the inversion circuits themselves can take advantage of dual basis multipliers, thus reducing their own hardware levels. As both these approaches require squaring in a finite field to take place, a theorem is presented which allows circuits to be easily designed to carry out squaring over the dual basis     

Design and implementation of an FPGA-based control IC forAC-voltage regulation

This paper presents a field-programmable gate army (FPGA)-based control integrated circuit (IC) for controlling the pulsewidth modulation (PWM) inverters used in power conditioning systems for AC-voltage regulation. We also propose a multiple-loop control scheme for this PWM inverter control IC to achieve sinusoidal voltage regulation under large load variations. The control scheme is simple in architecture and thus facilitates realization of the proposed digital controller for the PWM inverter using the FPGA-based circuit design approach. Bit-length effect of the digital PWM inverter controller has also been examined in this paper. The designed PWM inverter control IC has been realized using a single FPGA XC4005 from Xilinx Inc., which can be used as a coprocessor with a general-purpose microprocessor in application of AC-voltage regulation. Owing to the high-speed nature of FPGA, the sampling frequency of the constructed IC can be raised up to the range that cannot be reached using a conventional digital controller based merely on microcontrollers or a digital signal processor (DSP). Experimental results show the designed PWM inverter control IC using the proposed control scheme can achieve good voltage regulation against large load variations     

Novel electrical squaring circuit with an output bandwidth from DCto 2·6 GHz

The author has proposed a novel squaring circuit consisting of two double-balanced mixers, with the first mixer serving as an upconverter and the second mixer performing the squaring function. Using commercially available mixers, an experimental squaring circuit was demonstrated with an output bandwidth from DC to 2·6 GHz and with over 30 dB suppression of the unsquared signal power relative to the squared signal power, for input signal powers from -5 to +3 dBm. This circuit is promising for electrical signal processing applications which require a DC-coupled squaring operation with bandwidths in excess of 1 GHz. One such application is in coherent optical phase diversity receivers     

Combinational logic approach for implementing an improvedapproximate squaring function

The Viterbi algorithm is a fundamental signal-processing technique used in different communication systems. An improved, implemented, and tested approximate squaring function for the Viterbi algorithm is introduced in this paper. The implementation of this improved squaring function is based on combinational logic design. The performance of this new approach has been verified by implementing a 7-bit squaring function chip in a 2-μm CMOS technology. The active integrated circuit area of the chip was 380×400 μm², and the delays through this area were 5.7 and 3.0 ns for rising and falling edges, respectively. Compared with a previous design, this approach reduces error associated with approximation, simplifies the complexity of realization, reduces the integrated circuit area by at least 40%, and increases the speed by about 100%     

A Systolic, High Speed Architecture for an RSA Cryptosystem

An architecture based on the RSA public key cryptography algorithm is presented. The circuit includes two components, one for modular squaring and one for modular multiplication. Each component is based on the Montgomery algorithm and implements the modular operations using two modified serial-parallel multipliers. A full modular exponentiation is completed every n(n + 3) clock cycles. All circuits are systolic, operate with 100% efficiency and their maximum combinational delay is equal to one gated Full-Adder. Thus, high-speed performance is achieved while the low cell hardware complexity enables an efficient VLSI implementation.     

Design of a new squaring function for the Viterbi algorithm

An approximate squaring method has been developed for the Viterbi algorithm that is faster and more area efficient than conventional exact squaring methods and table look-up. Using Monte-Carlo simulations, it is shown here that the performance of the Viterbi algorithm is not degraded using this approximation. The circuit performance is verified by implementing a 7-b approximate squaring function in a 2-μm CMOS process. It operates at a maximum speed of 20 MHz, consumes 95 pW/Hz of power, and occupies an active area of 380 μm×650 μm     

FPGA realization of space-vector PWM control IC for three-phase PWMinverters

This paper presents a new circuit realization of the space-vector pulse-width modulation (SVPWM) strategy. An SVPWM control integrated circuit (IC) has been developed using state of-the-art field-programmable gate array (FPGA) technology. The proposed SVPWM control scheme can be realized using only a single FPGA (XC4010) from Xilinx, Inc. The output fundamental frequency can be adjusted from 0.094 to 1500 Hz. The pulse-width modulation (PWM) switching frequency can be set from 381 Hz to 48.84 kHz. The delay time for the PWM gating signals is adjustable. This SVPWM IC can also be included in the digital current control loop for stator current regulation. The designed SVPWM IC can be incorporated with a digital signal processor (DSP) to provide a simple and effective solution for high-performance AC drives. Simulation and experimental results are given to verify the implemented SVPWM control IC     

Parallel reduced area multipliers

As developed by Wallace and Dadda, a method for high-speed, parallel multiplication is to generate a matrix of partial products and then reduce the partial products to two numbers whose sum is equal to the final product. The resulting two numbers are then summed using a fast carry-propagate adder. This paper presents Reduced Area multipliers, which employ a modified reduction scheme that results in fewer components and less interconnect overhead than either Wallace or Dadda multipliers. This reduction scheme is especially useful for pipelined multipliers, because it minimizes the number of latches required in the reduction of the partial products. The reduction scheme can be applied to either unsigned (sign-magnitude) or two's complement numbers. Equations are given for determining the number of components and a method is presented for estimating the interconnect overhead for Wallace, Dadda, and Reduced Area multipliers. Area estimates indicate that for non-pipelined multipliers, the reduction in area achieved with Reduced Area multipliers ranges from 3.7 to 6.6 percent relative to Dadda multipliers, and from 3.8 to 8.4 percent relative to Wallace multipliers. For fully pipelined multipliers, the reduction in area ranges from 15.1 to 33.6 percent relative to Dadda multipliers, and from 2.9 to 9.0 percent relative to Wallace multipliers.     

有效的模(2n+1)乘算法及其VLSI设计

模乘运算在剩余数值系统、数字信号处理系统及其它领域都具有广泛的应用,模乘法器的硬件实现具有重要的作用。提出了一种改进的模(2~n 1)余数乘法器的算法及其硬件结构,其输入为通常的二进制表示,因此无需另外的输人数据转换电路而可直接用于数字信号处理应用。通过利用模(2~n 1)运算的周期性简化其乘积项并重组求和项,以及采用改进的进位存储加法器和超前进位加法器优化结构以减少路径延时和硬件复杂度。比较其它同类设计,新的结构具有较好的面积、延时性能。     

Low‐Power and Low‐Hardware Bit‐Parallel Polynomial Basis Systolic Multiplier over GF(2m) for Irreducible Polynomials

Multiplication in finite fields is used in many applications, especially in cryptography. It is a basic and the most computationally intensive operation from among all such operations. Several systolic multipliers are proposed in the literature that offer low hardware complexity or high speed. In this paper, a bit‐parallel polynomial basis systolic multiplier for generic irreducible polynomials is proposed based on a modified interleaved multiplication method. The hardware complexity and delay of the proposed multiplier are estimated, and a comparison with the corresponding multipliers available in the literature is presented. Of the corresponding multipliers, the proposed multiplier achieves a reduction in the hardware complexity of up to 20% when compared to the best multiplier for m = 163. The synthesis results of application‐specific integrated circuit and field‐programmable gate array implementations of the proposed multiplier are also presented. From the synthesis results, it is inferred that the proposed multiplier achieves low power consumption and low area complexitywhen compared to the best of the corresponding multipliers.