基于淘汰判决的跳频同步捕获方案设计

跳频通信同步捕获方案中,串行自同步捕获方案与并行自同步捕获方案是目前应用最广的同步捕获方案,但是串行捕获方案同步捕获时间较长,并行捕获方案系统太复杂,对此提出了基于淘汰判决的同步捕获方案。从捕获时间、抗干扰性能以及系统复杂度3个方面评价了捕获方案的性能。实验结果表明,基于淘汰判决的捕获方案,在保证抗干扰性能与系统复杂度的同时,捕获时间约为串行自同步捕获方案的1/5。     

MC-CDMA系统中定时同步分析

简单介绍了MC-CDMA系统,重点讨论了两种同步方案,即基于循环前缀、基于导频的同步方案。针对在有干扰存在的信道,分析这两种方案实现定时同步的可靠性。通过仿真,得出结论:基于导频的同步方案在噪声信道中能够准确实现定时同步,并且在有衰落存在的条件下,也能很好的实现定时同步。     

卷积码大数译码的节点同步

本文对卷积码大数译码一种节点同步方案进行了分析,从理论分析与实验均证实这种方案的局限性。本文提出了另一种节点同步方案,能克服上一方案的局限性,并能实现自动同步。     

AOS可变帧长的帧同步方案的研究

通过对AOS标准的研究,设计了AOS可变帧长的帧格式,将可变帧长的帧同步过程分为四种基本状态,并在漏检、虚警现象的基础上研究了基本同步方案方案和抗衰落帧同步方案的归一化帧同步保持时间,通过仿真说明了空间信道下,抗衰落帧帧同步方案更优。     

一种新的高速跳频同步方法

跳频电台同步系统要求具有良好的抗干扰性能和保密性能,同时达到快速同步.针对传统的时间信息和同步字头相结合的同步方案,提出了一种基于差分跳频原理的高速跳频同步方案.发送端利用载波的前后相关性来传送同步信息,接收端通过频率侦测获取同步信息,简化了传统方案中同步信息的编码、调制等过程.仿真结果表明,方案的同步性能有较大改善,同步时间短,抗干扰能力强.     

抗衰落帧同步潜在技术性能

本文从基本抗衰落帧同步方法出发,提出了四种综合抗衰落帧同步方案,并从理论上分析了CCITT推荐的帧同步方案和几种抗衰落帧同步方案的技术性能.     

正码速调整数字复接中帧同步方案的改进

本文讨论一个帧同步方案,该方案充分利用了插手指示比特的信息,总的同步恢复时间要比现有方案短一些。     

分布式全相参雷达系统时间与相位同步方案研究

分布式全相参雷达是一种新体制雷达,它解决了大口径雷达难以机动部署、造价昂贵等问题,是下一代雷达的发展方向,目前实现分布式全相参雷达所面临的关键技术问题是时间同步和相位同步。对此,该文分析了时间同步误差和相位同步误差的来源,建立了相应的数学模型,仿真了同步误差对相参性能的影响,给出了时间同步误差及相位同步误差的指标要求。并基于有线传输的非相关传输方式提出了时间同步方案,基于定标的方式提出了相位同步方案,以分别实现分布式全相参雷达的时间同步和相位同步。该文所提出的分布式全相参雷达同步方案,对于这一新体制雷达的实现具有一定的指导意义。      

基于附加频移的跳频同步组网设计与分析

为了提高跳频同步组网的频点利用率,提出了一种基于附加频移的跳频同步组网方案。首先,给出了基于附加频移跳频通信的基本模型和收发双方的实现方案;然后,基于该跳频通信模型,给出了同步组网的网络拓扑结构。该方案在整个工作频段内能够使用所有可用频点进行同步组网,提高了频点利用率。分析结果表明,在相同子网数下,该方案较常规跳频同步组网还具有更小的碰撞概率和比特差错率,同时该方案还增加了敌方的侦察分选难度和干扰难度。     

无人机宽带数据链中的高阶调制技术研究

针对无人机机载平台功率资源受限、 频谱资源受限等问题,开展了高阶调制技术在无人机宽带数据链中的应用研究.重点研究了调制方式选择、 定时同步和载波同步等关键技术,提出了一种适用于高阶调制信号的定时同步、 载波同步方案,并利用Matlab搭建高阶调制信号收发模型,对定时同步、 载波同步方案进行了仿真,验证了方案的有效性.研...     

脉冲信号对载波提取锁相环的干扰分析

载波提取锁相环是电子攻击的一个重要对象。环路在不同干扰样式下的失锁门限不尽相同。大部分文献中,通常以环路信噪比6dB作为环路的失锁门限,实验中发现此门限值对人为干扰并不适用。文中就白噪声、连续波信号和脉冲信号对载波提取锁相环的干扰进行了分析,给出了脉冲干扰条件下环路失锁门限的计算方法,阐述了脉冲干扰造成环路的闪锁和失锁现象。实验数据证实了脉冲干扰条件下载波提取锁相环的失锁门限更低。     

The Optimum Closed-Loop Transfer Function of a Phase-Locked Loop Used for Synchronization Purposes

This paper presents an expression for the optimum closed-loop transfer function of a phase-locked loop (PLL) which estimates the phase of an unmodulated sinuosoid corrupted by an additive random disturbance. This matter has been extensively treated (e.g., [1, ch. 4]) in the conventional PLL theory, where the disturbance is a stationary noise process. However, for an important class of synchronizers operating on a PAM waveform corrupted by stationary noise, the disturbance at the input of the PLL cannot be treated as a stationary process. In this case we show that the PLL transfer function which is optimized according to the conventional PLL theory is far from optimum. Therefore, we derive the closed-loop transfer function which is optimum for a more general disturbance. This extension of the conventional PLL theory applies to most synchronizers.     

基于微波YIG振荡器的锁相技术研究

本文介绍了一种基于微波YIG振荡器的锁相技术.主要叙述了YIG振荡器的原理以及其在微波领域优良的特性,比如极低的相位噪声、极宽的频带等等.然后重点介绍了用国家半导体(NS)的新一代锁相芯片LMX2471对YIG锁相的技术.     

Phase-locked loop techniques. A survey

Phase-locked loop (PLL) is a technique which has contributed significantly toward the technology advancement in communication and motor servo control systems in the past 30 years. Inventions in PLL schemes combined with novel integrated circuit (IC) technology have made PLL devices important system components. The development of better modular PLL ICs is continuing. As a result, it is expected that they will contribute to the improvement in performance and reliability of future communication systems. They will also contribute to the development of higher accuracy and higher reliability servo control systems, such as those involved in machine tools. This paper provides a concise review of the basic PLL principles applicable to communication and servo control systems, gives the configurations of PLL applications and reports a number of popular PLL chips     

一种自偏置锁相环结构的分析

介绍了一种自偏置结构形式的锁相环设计方法,在一定程度上可以对锁相频率源输出信号质量进行改善,提升产品性能,简化设计。在没有增加额外环外混频频率信号的情况下,对改进后的锁相环电路进行测试,其相位噪声指标提高约10 dB,具有较大的工程应用优势。     

基于ADF4350锁相频率合成器的频率源设计与实现

介绍了ADF4350锁相频率合成器的内部结构,在此基础上,分析和探讨了ADF4350锁相频率合成器的基本原理和工作特性.结合ADF4350的工作特性,给出了一种用AVR单片机控制ADF4350锁相频率合成器的频率源设计方法.对于环路滤波器,运用ADIsimPLL软件进行仿真和设计.通过对锁相环硬件电路的调试和编写相关单片机控制程序,实现了一个性能较好的频率源.     

A 10-GHz SiGe BiCMOS phase-locked-loop frequency synthesizer

A SiGe BiCMOS phase-locked-loop (ILL) circuit is presented. A maximum operational frequency of 10 GHz and a current consumption of 7.6 mA, i.e., 17 mW, is demonstrated. For a 9-mW low-power version, a maximum frequency of 4.7 GHz is determined. In a GSM direct conversion application, an in-band phase noise of -79 dBc/Hz at 2 kHz and a spurious suppression of -75 dBc at 400 kHz was measured at 3.4 GHz, which corresponds to a PLL phase noise floor of -214 dBc/Hz. For low-power applications, the PLL can be operated at supply voltages as low as 2.2 V and at RF input powers as low as -20 dBm while having a large output voltage range of 0.2 V to (V_cc-0.3 V). This demonstrates the speed and power advantage of the SiGe BiCMOS over Si BiCMOS and CMOS technologies for wireless communications     

A low-noise phase-locked loop design by loop bandwidth optimization

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter from a given PLL circuit topology. An optimal loop-bandwidth design method, derived from a discrete-time PLL model, further improves the jitter characteristics of a PLL already somewhat enhanced by optimizing individual circuit components. The described method not only estimates the timing jitter of a PLL, but also finds the optimal bandwidth minimizing the overall PLL jitter. A prototype PLL fabricated in a 0.6-μm CMOS technology is tested. The measurement shows significant performance improvement by using the proposed method, The measured rms and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 3.1 and 22 ps, respectively     

A multiple-crystal interface PLL with VCO realignment to reduce phase noise

An enhancement to a conventional integer-N phase-locked loop (PLL) is introduced, analyzed, and demonstrated experimentally to significantly reduce voltage-controlled oscillator (VCO) phase noise. The enhancement, which involves periodically injection locking the VCO to a buffered version of the reference, has the effect of widening the PLL bandwidth and reducing the overall phase noise. It is demonstrated in a 3-V 6.8-mW CMOS reference PLL with a ring VCO capable of converting most of the popular crystal reference frequencies to a 96-MHz RF PLL reference and baseband clock for a direct conversion Bluetooth wireless LAN. The peak in-band phase noise at an offset of 20 kHz is -102 dBc/Hz with the technique enabled and -92 dBc/Hz with the technique disabled. A theoretical analysis is presented and shown to be in close agreement with the measured results.