用高低温循环加速试验评估光源模块长期贮存寿命的研究

Light source modules are the most crucial and fragile devices that affect the life and reliability of the interferometric fiber optic gyroscope （IFOG）. While the light emitting chips were stable in most cases, the module packaging proved to be less satisfactory. In long-term storage or the working environment, the ambient temperature changes constantly and thus the packaging and coupling performance of light source modules are more likely to degrade slowly due to different materials with different coefficients of thermal expansion in the bonding interface. A constant temperature accelerated life test cannot evaluate the impact of temperature variation on the performance of a module package, so the temperature cycling accelerated life test was studied. The main failure mechanism affecting light source modules is package failure due to solder fatigue failure including a fiber coupling shift, loss of cooling efficiency and thermal resistor degradation, so the Norris-Landzberg model was used to model solder fatigue life and determine the activation energy related to solder fatigue failure mechanism. By analyzing the test data, activation energy was determined and then the mean life of light source modules in different storage environments with a continuously changing temperature was simulated, which has provided direct reference data for the storage life prediction of IFOG.     

晶体管加速寿命研究

Choosing small and medium power switching transistors of the NPN type in a 3DK set as the study object,the test of accelerating life is conducted in constant temperature and humidity,and then the data are statistically analyzed with software developed by ourselves.According to degradations of such sensitive parameters as the reverse leakage current of transistors,the lifetime order of transistors is about more than 10~4 at 100℃and 100% relative humidity(RH) conditions.By corrosion fracture of transistor outer leads and other failure modes,with the failure truncated testing,the average lifetime rank of transistors in different distributions is extrapolated about 10~3. Failure mechanism analyses of degradation of electrical parameters,outer lead fracture and other reasons that affect transistor lifetime are conducted.The findings show that the impact of external stress of outer leads on transistor reliability is more serious than that of parameter degradation.     

Electromigration failure in ultra-fine copper interconnects

This paper presents experimental evidence suggesting that electromigration (EM) can be a serious reliability threat when the dimension of Cu interconnects approaches the nanoscale range. To understand the failure mechanism prevailing in nanoscale Cu interconnects, single-level, 400-μm long interconnects with various effective widths, ranging from 750 nm to 80 nm, were made, EM tested, and characterized in this investigation. The results indicate that interface EM (Cu/barrier) may be the predominant EM mechanism in all line widths. The evidence supporting the active Cu/barrier interface EM includes the fact that the EM lifetime is inversely proportional to the interface area fraction. Microscopic analysis of the failure sites also supports the conclusion of interface EM because voids and hillocks are found at the ends of the test strip, which is not possible if lines fail by grain-boundary EM in the test structure used in this study. In addition, our study finds evidence that failure is assisted by a secondary mechanism. The influence of this factor is particularly significant when the feature size is small, resulting in more uniform distribution of failure time in narrower lines. Although limited, evidence suggests that the secondary factor is probably attributed to pre-existing defects or grain boundaries.     

Mechanism of electromigration failure in submicron Cu interconnects

This paper reports on two different electromigration-failure mechanisms competing in Cu interconnects. Accelerated electromigration tests are conducted on identical single-level, 0.25-μm Cu interconnects with SiN or SiCN passivation. The results indicate that the failure mechanism can vary with the interface condition of the capping layer. The first failure mechanism, seen primarily in SiN-capped samples, is characterized by extensive interface damage, believed to be a result of failure led by interface electromigration. In this failure mode, damage initiates at the capping interface but gradually spreads along all interfaces of the Cu to form an isolated strand. The competing failure mechanism, found in SiCN-capped samples, is characterized by the formation and growth of a localized void without extensive interface damage. The absence of interface damage, in addition to the higher activation energy for failure, suggests that the failure occurs at a more localized inhomogeneity than the interface, such as grain boundaries. While the exact mechanism of how the capping layer suppresses one mechanism and promotes the other is unknown, this study reveals that the passivation-interface material and condition have a decisive role in determining the failure mechanism in Cu interconnects.     

Electromigration studies on Sn(Cu) alloy lines

The Cu alloying effect in the Sn(Cu) solder line has been studied. The Sn0.7Cu solder line has the most serious electromigration (EM) damage compared to pure Sn and Sn3.0Cu solder lines. The dominant factor for the fast EM rate in Sn0.7Cu could be attributed to the relatively small grain size and the low critical stress, i.e., the yielding stress of the Sn0.7Cu solder line. Also, we found that the shortest Sn0.7Cu solder line, 250 μm, has the most serious EM damage among three solder lines of different lengths. The back stress induced by EM might not play a significant role on the EM test of long solder lines. A new failure mode of EM test was observed; EM under an external tensile stress. The external stress is superimposed on the stress profile induced by EM. As a result, the hillock formation was retarded at the anode side, and void formation was enhanced at the cathode.     

Gas selectivity of SILAR grown CdS nano-bulk junction

Nano-particles of cadmium sulphide were deposited on cleaned copper substrate by an automated sequential ionic layer adsorption reaction (SILAR) system.The grown nano-bulk junction exhibits Schottky diode behavior.The response of the nano-bulk junction was investigated under oxygen and hydrogen atmospheric conditions.The gas response ratio was found to be 198％ for Oxygen and 34％ for Hydrogen at room temperature.An increase in the operating temperature of the nano-bulk junction resulted in a decrease in their gas response ratio.A logarithmic dependence on the oxygen partial pressure to the junction response was observed,indicating a Temkin isothermal behavior.Work function measurements using a Kelvin probe demonstrate that the exposure to an oxygen atmosphere fails to effectively separate the charges due to the built-in electric field at the interface.Based on the benefits like simple structure,ease of fabrication and response ratio the studied device is a promising candidate for gas detection applications.     

Stress control of silicon nitride films deposited by plasma enhanced chemical vapor deposition

Stress controllable silicon nitride(Si Nx) films deposited by plasma enhanced chemical vapor deposition(PECVD) are reported. Low stress Si Nx films were deposited in both high frequency(HF) mode and dual frequency(HF/LF) mode. By optimizing process parameters, stress free(-0.27 MPa) Si Nx films were obtained with the deposition rate of 45.5 nm/min and the refractive index of 2.06. Furthermore, at HF/LF mode, the stress is significantly influenced by LF ratio and LF power, and can be controlled to be 10 MPa with the LF ratio of 17% and LF power of 150 W. However, LF power has a little effect on the deposition rate due to the interaction between HF power and LF power. The deposited Si Nx films have good mechanical and optical properties, low deposition temperature and controllable stress, and can be widely used in integrated circuit(IC), micro-electro-mechanical systems(MEMS) and bio-MEMS.     

Temperature Dependent Raman Scattering of Phonon Modes and Defect Modes in GaN and p-Type GaN Films

Raman spectra of undoped GaN and Mg-doped GaN films grown by metal-organic chemical-vapor deposition on sapphire are investigated between 78 and 573K.A peak at 247cm－1 is observed in both Raman spectra of GaN and Mg-doped GaN.It is suggested that the defect-induced scattering is origin of the mode.The electronic Raman scattering mechanism and Mgrelated local vibrational mode are excluded.Furthermore,the differences of E2 and A1(LO) modes in two samples are also discussed.The stress relaxation is observed in Mg-doped GaN.     

Characteristics of high power LEDs at high and low temperature

The high power light emitting diodes(LEDs) based on InGaN and AlGaInP individually are tested on line at temperatures from -30 to 100℃.The data are fitted to measure the relationship between temperature and the properties of forward voltage,relative light intensity,wavelength,and spectral bandwidth of two different kinds of LEDs.Why these properties changed and how these changes reflected on applications are also analyzed and compared with each other.The results show that temperature has a great influence on the performance and application of power LEDs.For applications at low temperature,the forward voltage rising and the peak wavelength blue-shifting must be considered;and at high temperature,the relative light intensity decreasing and the peak wavelength red-shifting must be considered.     

Modeling the defect distribution and degradation of ultrathin CdTe films

The defect distribution across an ultrathin film Cd Te layer of a Cd S/Cd Te solar cell is modelled by solving the balance equation in steady state. The degradation of the device parameters due to the induced defects during ion implantation is considered where the degradation rate is accelerated if the defect distribution is considerable.The defect concentration is maximum at the surface of the Cd Te layer where implantation is applied and it is minimum at the junction with the Cd S layer. It shows that ultrathin devices degrade faster if the defect concentration is high at the junction rather than the back region(Cd Te/Metal). Since the front and back contacts of the device are close in ultrathin films and the electric field is strong to drive the defects into the junction, the p-doping process might be precisely controlled during ion implantation. The modeling results presented here are in agreement with the few available experimental reports in literature about the degradation and defect configuration of the ultrathin Cd Te films.     

A combined fuzzy-logic and physics-of-failure approach toreliability prediction

An original reliability prediction procedure is presented. The physics of failure accounts for the failure mechanisms involved (a lognormal distribution was presumed); the interactions (synergies) between the technology factors depending on the manufacturing techniques are considered. The basis of this methodology (called SYRP=synergetic reliability prediction) is the assessment of failure-risk coefficients (FRC), based on fuzzy logic, for the potential failure mechanisms induced at each manufacturing step. These FRC are corrected at the subsequent steps by considering the synergy of the manufacturing factors, At the end of the manufacturing process, final FRC are obtained for each potential failure mechanism; the parameters of the lognormal distribution are calculated with a simple algorithm. Experimental results for four lots of the same type of semiconductor devices, each lot being manufactured with a slightly different technology, were obtained. SYRP forecasts for these four lots agree well with accelerated life test results. This is a fairly good result, because SYRP was used early, at the design phase     

基于MAM的白光OLED恒定应力加速寿命试验研究

为了短时间内获得白光有机发光显示器(OLED)的可靠性寿命信息,通过对其开展三组恒定电流应力加速寿命试验采集样品失效试验数据,应用对数正态分布函数描述白光OLED的寿命分布。在图分析法(MAM)的基础上,基于自行开发的寿命预测软件,绘制了对数正态概率双坐标纸,计算出白光OLED的平均寿命和中位寿命。数值结果表明,白光OLED寿命服从对数正态分布,加速寿命方程符合逆幂定律,精确计算的加速参数使得对其寿命的快速估算成为可能。结果可为生产厂商和用户提供参考和指导。     

基于加速环境的可靠性指标验证试验

首先进行了电子产品失效模型的理论研究,并利用加速退化试验技术而研究了某通信产品失效机理一致的应力范围,通过对试验数据进行的统计分析,计算出失效机理一致情况下的激活能。在可靠性指标验证的试验研究中,将试验样品分成若干组分别进行恒温加速验证试验,并将试验结果与现场统计数据进行比较,最终确定产品的MTBF。     

真空荧光显示屏恒定及步进应力加速寿命试验的研究

为了解决在较短的时间内预测真空荧光显示屏（VFD）寿命的问题,降低寿命预测成本,通过加大灯丝温度进行了恒定和步进应力相组合的加速寿命试验,研究制定了其加速寿命试验的设计方案。应用威布尔分布函数描述其寿命分布,利用最小二乘法完成了试验数据的统计和分析,并开发了寿命预测软件。研究结果表明．试验设计方案是正确可行的,VFD的寿命服从威布尔分布,其加速模型符合阿伦尼斯方程,加速参数的精确计算确保以后在很短的时间内便可估算出VFD在正常应力下的寿命。     

Reliability matrix solution to multiple mechanism prediction

We present a method for predicting the failure rate and thus the reliability of an electronic system by summing the failure rate of each known failure mechanism. We use a competing acceleration factor methodology by combining the physics of failure for each mechanism with its own effect as observed by High/Low temperature and High/Low voltage stresses. Our Multiple High Temperature Overstress Life-test (M-HTOL) method assumes that the lifetime of each failure mechanism follows constant rate distribution whereby each mechanism is independently accelerated by its own stress factors. Stresses include temperature, frequency, current, and other factors that can be entered into a reliability model. The overall failure rate thus, also follows an exponential distribution and is described as the standard FIT (Failure unIT or Failure in Time). This method combines mathematical models for known failure mechanism and solves them simultaneously for a multiplicity of accelerated life test results to find a consistent set of weighting factors for each mechanism. The result of solving the system of equations is a more accurate and a unique combination for each system model by proportional summation of each of the contributing failure mechanisms.     

航天InGaAs短波红外探测器步进应力加速寿命试验研究

随着航天应用InGaAs短波红外探测器的迅速发展,其可靠性问题日益突出。选择温度为加速应力,通过步进应力加速寿命试验方法对800×2双波段集成的InGaAs焦平面探测器进行了研究,获得了InGaAs焦平面模块失效机理保持不变的最大温度应力范围和失效模式,利用温度斜坡模型计算得到了样品的失效激活能,为进一步研究该器件的可靠性问题提供了依据。     

Optimum simple step-stress accelerated life-tests with competingcauses of failure

Optimum simple step-stress accelerated life tests (ALTs) for products with competing causes of failure are presented. The life distribution of each failure cause, which is independent of the others, is assumed to be exponential with a mean that is a log-linear function of the stress, and a cumulative exposure model is assumed. Optimum plans for time-step and failure-step ALTs are obtained which minimize the sum over all failure causes of asymptotic variances of the maximum likelihood estimators of the log mean lives at design stress. The competing causes of failure affect the optimum test plan only through the product of two ratios-the ratio of the sums of the mean lives and the ratio of the sums of the failure rates over all failure causes at low and high stress levels. The effect of this product (of two ratios) is studied     

High current bond design rules based on bond pad degradation and fusing of the wire

In this paper design rules for maximum current handling capability of gold bond wires are derived based on two failure mechanisms: (1) fusing of the wire; and (2) degradation of the interface between gold bond balls and the aluminum bond pads under high current/high temperature stress. For determination of the fuse current as a function of the length an analytical model is used to calculate the temperature and power distribution in the wire as a function of the position. The current level at which the melt temperature of gold is reached is the fuse current. The degradation mechanism under high current stress (up to 2.5 A) was studied by in-situ monitoring of the gold bond ball–aluminum interconnect contact resistance under high current stress at various temperatures and stress currents. The cumulative failure distributions were used to fit a model for lifetime as a function of current and temperature that shows an order of magnitude difference in lifetime between positive and negative current stress. Finally, fuse current and the lifetime model result in data-driven high current design rules for bond pad and wire.     

Analyzing accelerated degradation data by nonparametric regression

This paper presents a nonparametric regression accelerated life-stress (NPRALS) model for accelerated degradation data wherein the data consist of groups of degrading curve data. In contrast to the usual parametric modeling, a nonparametric regression model relaxes assumptions on the form of the regression functions and lets data speak for themselves in searching for a suitable model for data. NPRALS assumes that various stress levels affect only the degradation rate, but not the shape of the degradation curve. An algorithm is presented for estimating the components of NPRALS. By investigating the relationship between the acceleration factors and the stress levels, the mean time to failure estimate of the product under the usual use condition is obtained. The procedure is applied to a set of data obtained from an accelerated degradation test for a light emitting diode product. The results look very promising. The performance of NPRALS is further checked by a simulated example and found satisfactory. We anticipate that NPRALS can be applied to other applications as well     

Die degradation effect on aging rate in accelerated cycling tests of SiC power MOSFET modules

In order to distinguish the die and bond wire degradations, in this paper both the die and bond wire resistances of SiC MOSFET modules are measured and tested during the accelerated cycling tests. It is proved that, since the die degradation under specific conditions increases the temperature swing, bond wires undergo harsher thermo-mechanical stress than expected. The experimental results confirm the die-related thermal failure mechanism. An improved degradation model is proposed for the bond-wire resistance increase in case of die degradation.