数字电路设计中有限状态机的应用

有限状态机的设计及使用是数字电路设计中的重要内容,本文通过对有限状态机的设计过程及使用VHDL语言描述做了介绍,并通过ADC0809进行AD采样的有限状态机的设计实例,总结了有限状态机VHDL设计的一般过程。     

SystemC中一类特殊线程与状态机研究

作为一种系统建模语言,SystemC支持各个抽象级别的硬件描述以及软硬件协同设计和验证。在SystemC中定义了一类特殊的线程称为钟控线程,虽然是行为级描述,却是面向综合优化的。该类线程最适合描述一种隐式的有限状态机。本文描述了该类线程的特点,并以一个总线控制器的设计为例,比较了隐式有限状态机相对于一般显式有限状态机的优点。     

基于Verilog HDL的可综合有限状态机设计

Verilog HDL(硬件描述语言)不仅可以在门级和寄存器传输级进行硬件描述,也可以在算法级对硬件加以描述。有限状态机是数字系统中的重要组成部分。文中研究了用Verilog HDL设计有限状态机时可以采用的不同的编码方式和描述风格,并介绍了有限状态机综合的一般原则。最后以存储控制器状态机为例,分别用Synplify Pro和QuartusⅡ对设计进行了综合和仿真验证。     

Verilog HDL代码描述对状态机综合的研究

verilog HDL语言在芯片设计中应用广泛，而有限状态机的设计是数字系统设计的关键部分。本文介绍了有限状态机的设计，探讨了Verilog HDL代码描述会对状态机的综合结果产生的影响，最后通过一个序列检测器的设计进行实例说明，     

移动IPv6测试中的层次化协议描述和测试生成方法

移动IPv6协议是一种庞大的分布式协议，这为协议描述和测试生成带来了困难．提出分层次描述协议的思想，定义了描述协议的有限状态机和多节点有限状态机模型，分四个层次分别对协议运行流程、协议节点类型、内部数据结构处理、离散功能进行了形式化描述．把描述协议的状态机模型转化为有向图，设计了针对有向图的测试序列集产生算法，最终生成了覆盖整个移动IPv6协议的测试序列集．     

基于VHDL的MTM总线主模块有限状态机设计

为了能够更简洁严谨地描述MTM总线的主模块有限状态机的状态转换,同时减少FPGA芯片功耗,提高系统稳定性．文中在分析MTM总线结构和主模块有限状态机模型的基础上,基于VHDL语言采用“单进程”式对该有限状态机进行了设计。并在Quartus II开发软件中实现了对语言代码的编译及程序的时序仿真和功能仿真;通过对仿真波形图的分析验证了该状态机设计的正确性和有效性。     

基于Verilog HDL的高效状态机设计

用Verilog HDL(硬件描述语言)进行有限状态机电路设计,由于设计方法不同,综合出来的电路结构、速度、面积和时延特性都会有很大的差别,甚至某些臃肿的电路还会产生难以预料的问题。因此,很有必要深入探讨在用Verilog HDL进行有限状态机设计中,如何简化电路结构、优化电路设计的问题。文中根据有限状态机的设计原理,描述了有限状态机设计的几种设计方法,分析了影响状态机设计时延、速度和电路综合面积问题,提出了一种高效状态机设计方法,并给出了基于Veril-og HDL程序综合得到的电路图,验证了方法的正确性。     

BACnet应用层测试状态机自动生成研究

协议状态机测试是通信协议一致性测试的重要内容，状态机的自动测试有利于提高协议测试的效率。本文首先介绍了扩展有限状态机模型，然后采用扩展有限状态机模型对BACnet应用层状态机进行了详细的分析．讨论了BACnet应用层测试状态机自动生成的可能性，最后提出了一个基于规则推理的测试状态机生成方法．该方法能够根据协议一致性声明自动生成测试状态机。     

面向工程化教育的有限状态机教学设计

有限状态机是"硬件描述语言"课程教学的重点和难点。本文深入分析当前有限状态机教学的现状,指出有限状态机教学与工程化人才培养需求的之间差距。在此基础上,论文提出并阐述了一种问题驱动的有限状态机教学体系,对算法状态机图和模板式编码风格等有限状态机设计的相关概念和方法进行了阐述。     

基于EAP-TLS的认证机制研究与实现

描述了TLS(transport layer security)协议、EAP(extensible authentication protocol)、EAP-TLS协议流程和消息格式,给出了EAP-TLS协议的有限状态机设计,并根据有限状态机在Ubanto系统下实现EAP-TLS认证机制。测试结果表明,开发的软件具有良好的规范性、可靠性和稳定性,能有效实现用户和服务器间的双向认证。     

有限状态机的Verilog设计与研究

本文研究了用Verilog实现有限状态机的各种不同的编码方式和描述风格，并从综合，毛刺，面积，速度这几方面研究了不同实现方式的利弊。最后，以SoC芯片中DMA Arbitor有限状态机为例，我们用Design Complier（DC）对七种设计进行了综合，并分析了综合后的面积和时延信息。     

Low-power state encoding for partitioned FSMs with mixed synchronous/asynchronous state memory

Partitioned finite state machine (FSM) architectures in general enable low-power implementations and it has been shown that for these architectures, state memory based on both synchronous and asynchronous storage elements gives lower power consumption compared to their fully synchronous counterparts. In this paper we present state encoding techniques for a partitioned FSM architecture based on mixed synchronous/asynchronous state memory. The state memory, in this case, is composed of a synchronous local state memory and an asynchronous global state memory. The local state memory uses synchronous storage elements and is shared by all sub-FSMs. The global state memory operates asynchronously and is responsible for handling the interaction between sub-FSMs. Even though the partitioned FSM contains the asynchronous mechanism, its input/output behaviour is still cycle by cycle equivalent to the original monolithic synchronous FSM. In this paper, we discuss the low-power state encoding method for the implementation of partitioned FSM with mixed synchronous/asynchronous state memory. For the local state assignment a, what we call, state-bundling procedure is presented to enable states residing in different sub-FSMs to share the same state codes. Based on state-bundles, two state encoding techniques, in which one is the employment of binary encoding and the other is the further optimization for low power, are compared.     

一种可逆有限状态机的电路设计

不同以往通过重构电路行为实现可逆有限状态机方法,本文提出了一种可逆有限状态机的电路结构.该电路主要包括次态与输出计算电路以及状态预置与采样锁存电路两部分,且提出的可逆有限状态机电路中不存在独立的可逆触发器,但可以实现可逆JK,D,T等触发器功能.同时,文中也提出了基于该可逆有限状态机电路的可逆时序电路综合方法,并用实例进行了验证.相比于基于行为重构的可逆有限状态机的综合方法,本文提出的综合方法可以避免原始状态机的逆状态机的求解和增加额外的信号位,从而使得综合过程变得更加简单.     

Minimization of mealy finite state machines via internal state merging

The problem of minimizing Mealy finite state machines (FSMs) arises when digital devices based on programmable logic integrated circuits are synthesized. A distinctive feature of the approach proposed is that merging of two states is used and an FSM is represented as a transition list. The conditions used to merge states, the functioning identity and the FSM’s behavior determinacy, are presented. Situations leading to wait state formation caused by state merging are discussed. The algorithms for minimizing the internal states, transition paths, and input variable of FSMs are described. The features of application of the method proposed are discussed.     

Finite state machine synthesis with embedded test function

We propose a synthesis for a testability method in which the test function is incorporated into the state diagram of the finite state machine (FSM). The test function is specified as an FSM with the same number of state variables as the given object machine. Based upon the chosen test methodology, a variety of test functions can be defined. As an illustration, we construct a test machine in which each state is uniquely set and observed by an input sequence no longer than log _k n, wheren is the number of states and the integerk is a design parameter. The state transition graph of the test machine is superimposed on the state graph of the object function such that a minimal number of new transitions are added. State assignment, logic minimization, and technology mapping are carried out for the combined graph. By design, the embedded test machine is fully testable. Also, since the test machine can control all memory elements, the circuit is effectively tested by a combinational circuit test generator. Scan register is shown to be a special case in this methodology.     

Theoretical bounds for switching activity analysis in finite-statemachines

The objective of this paper is to provide lower and upper bounds for the switching activity on the state lines in finite state machines (FSMs). Using a Markov chain model for the behavior of the FSM states, we derive theoretical bounds for the average Hamming distance on the state lines which are valid irrespective of the state encoding used in the final implementation. Such lower and upper bounds, in addition to providing a target for any state assignment algorithm, can also be used as parameters in a high-level power model and thus provide an early indication about the performance limits of the target FSM     

Implicit FSM decomposition applied to low-power design

Clock-gating techniques are very effective in the reduction of the switching activity in sequential logic circuits. In this paper, we describe a clock-gating technique based on finite-state machine (FSM) decomposition. The approach is based on the computation of two sub-FSMs that together have the same functionality as the original FSM. For all the transitions within one sub-FSM, the clock for the other sub-FSM is disabled. To minimize the average switching activity, we search for a small cluster of states with high stationary state probability and use it to create the small sub-FSM. Explicit manipulation of the state transition graph requires time and space exponential on the number of registers in the circuit, thereby restricting the applicability of explicit methods to relatively small circuits. The approach we propose is based on a method that implicitly performs the FSM decomposition. Using this technique, the FSM decomposition is performed by direct manipulation of the circuit. We provide a set of experiments that show that power consumption can be substantially reduced, in some cases by more than 70%.     

ROM-based FSM implementation using input multiplexing in FPGA devices

A new approach for ROM implementation of finite state machines (FSM) is proposed, based on the selection of a subset of inputs in each state using multiplexers. This technique has been applied to different FSM standard benchmarks and very good results have been obtained.     

Fault identification using a finite state machine model withunreliable partially observed data sequences

The problem of minimum cost identification of a finite state machine (FSM) using a trace of its event history is addressed. The motivation is fault identification in communication systems, although other applications are possible as well. The event history used for the identification is partially observed, i.e., it is known to be a member of a regular language. Any string which belongs in this regular language is a possible trace of the FSM's event history. Furthermore, the event history is assumed to be corrupted with deletions, additions, and changes of symbols. The FSM to be estimated is related to a known FSM by performing an unknown number of additions and changes of arcs. An identification algorithm based on a fast algorithm that can correct corrupted data strings generated by a known finite state machine is developed. Examples of the method are provided, including one based on the IEEE 802.2 logical link control protocol