Characteristics of MOSFETs fabricated in silicon-on-insulator material formed by high-dose oxygen ion implantation

By implanting a dose of 6×1017 cm?2 of 32O at 300 keV into a silicon wafer, a buried oxide layer is formed. Crystallinity of the silicon layer above the buried oxide layer is maintained by applying a high (>200°C) substrate temperature during the ion implantation process. A two-step anneal cycle is found to be adequate to form the insulating buried oxide layer and to repair the implantation damage in the silicon layer on top of the buried oxide. A surface electron mobility as high as 710 cm2/Vs has been measured in n-channel MOSFETs fabricated in a 0.5 ?m-thick epitaxial layer grown on the buried oxide wafer. A minimum subthreshold current of about 10 pA per micron of channel width at VDS=2 V has been measured.     

Simox technology and its application to CMOS LSIS

SIMOX technology has been developed for fabricating SOI-type devices. In this technology, buried silicon oxide is used for the vertical isolation of semiconductor devices. The buried oxide is formed by oxygen-ion implantation into silicon, followed by epitaxial growth of silicon onto the surface of the residual silicon above the buried oxide. The crystallinity of the residual silicon was investigated by electron beam diffraction, while the implanted oxygen depth profile was analyzed by Rutherford backscattering spectroscopy. A 1Kb CMOS static RAM has been fabricated using polysilicon gate SIMOX technology with a 1.5μm effective channel length. The chip-select access time of the RAM was 12ns at 45mW dissi-pation power.     

CMOS on buried nitride—A VLSI SOI technology

A CMOS technology in silicon on insulator (SOI) for VLSI applications is presented. The insulator is a buried silicon nitride formed by nitrogen implantation and annealing. The CMOS devices are fabricated in the superficial monocrystalline silicon layer without an epitaxial process, 1-µm PMOS and 2-µm NMOS transistors have been realized, which have been used to built inverters, ring Oscillators, and other circuits. With 40-nm gate oxide the transistors withstand gate and drain voltages of 10 V. Mobilities, subthreshold behavior, and leakage currents are nearly the same as in bulk-CMOS devices. Ring-oscillator measurements yield inverter delay times of 230 ps and power delay products of 14 fJ.     

Hardening silicon-on-insulator nMOSFETs by multiple-step Si+ implantation

A novel technique is proposed to improve total irradiation dose (TID) hardness of buried oxides in a 0.13 μm silicon-on-insulator (SOI) technology. Multiple-step Si ion implantation is implemented to avoid silicon film amorphization. Each implant step introduces silicon ion implantation of a lower dose into buried oxides which creates an amorphous/crystalline (a/c) interface inside the silicon layer. Rapid thermal annealing (RTA) removes implant-induced lattice damages by silicon recrystallization reflected in a/c interface moving towards the top silicon surface. The thermal process prevents top silicon layers from total amorphization arising in the technique of single high dose implantation method. X-ray Diffraction (XRD) spectrum confirms the existence of the a/c interface and determines the single implant dose. Experimental results on pseudo-MOS and H-gate partially-depleted SOI n-type MOSFETs show radiation tolerance up to 1.0 Mrad(Si) though introduced metastable electron traps lead to I–V hysteresis and bias instabilities.     

A back-wafer contacted silicon-on-glass integrated bipolar process. Part I. The conflict electrical versus thermal isolation

A novel silicon-on-glass integrated bipolar technology is presented. The transfer to glass is performed by gluing and subsequent removal of the bulk silicon to a buried oxide layer. Low-ohmic collector contacts are processed on the back-wafer by implantation and dopant activation by excimer laser annealing. The improved electrical isolation with reduced collector-base capacitance, collector resistance and substrate capacitance, also provide an extremely good thermal isolation. The devices are electrothermally characterized in relationship to different heat-spreader designs by electrical measurement and nematic liquid crystal imaging. Accurate values of the temperature at thermal breakdown and thermal resistance are extracted from current-controlled Gummel plot measurements.     

Ion implantation of neon in silicon for planar amorphous isolation

A new planar isolation technique for silicon integrated circuits is presented. The process uses neon implantation to create high-resistivity regions of amorphous silicon between active devices on a common substrate. Excellent surface planarity is obtained, and no high-temperature processing ii required. Results on test devices and an amorphous isolated m.n.o.s. capacitor memory are described.     

Novel semiconductor substrate for high-speed integrated circuit manufacture

High-resistivity layers formed beneath silicon surface layers by using proton implantation and annealing are described. Three-step annealing is suggested to form a buried layer of higher resistivity. Experiments show that the quality of the top layers has been improved, with an increase in surface mobility.<>     

Improvement of crystalline quality of the surface layer in buried implanted oxide structures by silicon implantation

An improvement of the crystalline quality of the surface layer in buried implanted oxide structures in silicon has been achieved by silicon in implantation and subsequent 570°C anneal treatment.     

Ion-implanted FET for power applications

High-energy ion implantation is coupled with the conventional planar technology to realize a silicon FET for power application. This device known as "Gridistor" is a multichannel FET with a p-type buried as gate. Boron implantation at various energies (600-900 keV) through a metallic mask are used to do a high-doped p-type gate layer, 0.8 µ thick and buried 1 µ below the surface. Since there is no implantation induced defects in the active regions of the device, low annealing temperature can be effectively used. As a consequence, the pattern sharpness is only limited by the definition of the mask. Using ion-etched gold layer as mask, 1 µ wide channels are made in a reproductible way. Few test structures have been made to check the behavior of implantation and planar technologies by measuring their capaci tances, transconductance, and I-V characteristics.     

Silicon-on-insulator power integrated circuits

A power integrated circuit process has been developed, based on silicon-on-insulator, which allows intelligent CMOS control circuitry to be placed alongside integrated high-voltage power devices. A breakdown voltage of 335 V has been obtained by using a silicon layer of 4 μm thickness together with a buried oxide layer of 3 μm thickness. The respective LDMOS specific on-resistance and LIGBT on-state voltage for this breakdown voltage were 148 mΩ cm² and 3.9 V, respectively.     

Scaled CMOS technology using SEG isolation and buried well process

An advanced bulk CMOS technology has been developed using the selective epitaxial growth (SEG) isolation technique and buried n-well process. CMOS devices are fabricated on a selective epitaxial layer, isolated by a thick SiO2insulator over the p⁺substrate. p-channel devices are designed on buried n-wells, formed by introducing a phosphorus ion implantation into the p⁺substrate before the epitaxial growth. The use of an SiO2sidewall and square side direction is effective for defect-free selective epitaxy. The epitaxial autodoping effect from the p⁺substrate and the buried layer is estimated to be within less than 1 µm. A 20-nm-thick gate oxide and 500-nm-thick phosphorus-doped polysilicon gate electrode are used for both channel devices. Submicrometer gate CMOS operation is confirmed using the SEG isolation technique. This isolation structure, combined with the buried well, shows large latchup immunity for scaled CMOS circuits.     

Buried-guarded layer ion-implanted resistors

Megohm silicon monolithic resistors have been fabricated with sheet resistances up to 120 kΩ/□ using an implanted p-layer resistor which is buried under an implanted n-guard layer. The n-guard layer protects against slice-to-slice variations of the fixed surface charge, and was made using phosphorus doses and energy of 1.5-5 × 10¹²/cm²and 30 keV. Resistors have been fabricated up to 20 MΩ; sheet resistances were in the range of 7-120 kΩ/□ using boron doses and energies of 1-3 × 10^:12/cm²and 30-300 keV. The sheet resistance, voltage dependence of resistance, temperature coefficients, junction leakage, and parasitic capacitance have been measured for different implantation parameters. This process has been used to fabricate two matched 8-MΩ resistors for use in a high input impedance differential preamplifier integrated circuit. A match of 2 percent and a magnitude tolerance of ±10 percent has been achieved. The temperature coefficient of resistance (TCR) is about 4000 ppm/°C and tracks within 400 ppm/ °C. These resistors are linear up to ∼1 V, about 50 times higher bias voltage than required in the application. The structure and fabrication are compatible with present monolithic silicon integrated circuit processing.     

Dielectric isolation techniques for integrated circuits

There has been an increasing interest in producing dielectrically isolated integrated circuits over the past five years for both bipolar and MOS. This impetus stems from the potential of such a technique to increase the operational speed of the circuit, particularly CMOS by reduction of the stray capacitance and a need to reduce the susceptibility of monolithic circuits to photocurrents generated by radiation in space and military environments. In general, early methods for producing dielectrically isolated circuits involved relatively costly lapping and polishing techniques which were generally low yield processes or the development of a completely new process e.g. silicon on sapphire. Recently, preferential anisotropic silicon etchants which may eliminate the mechanical process steps have been announced, as well as the possibility of ion implantation of heavy doses of nitrogen or oxygen at relatively high energies to produce the buried dielectric layer. These new processes will be compared with more traditional methods.     

Photosensing Arrays with Improved Spatial Resolution

The spatial resolution obtainable in a photosensing array used for optical imaging may be limited by the diffusion of photogenerated carriers within a uniformly doped semiconductor even if other components of the optical system are optimized and scattered light is reduced. A technique has been developed to improve the spatial resolution for critical applications by incorporating subsurface electric fields that accelerate the photogenerated carriers toward or away from the surface so that the carriers are prevented from diffusing to distant photosensing elements. The subsurface fields are obtained by incorporating suitable dopant concentration gradients into the structure. In one structure fabricated the subsurface field was formed by using a heavily doped buried layer and a lightly doped epitaxial film over a lightly doped substrate, all of the same conductivity type. This structure is compatible with the incorporation of other semiconductor devices in the same monolithic substrate. The technique has been applied to an array of photodiodes in a silicon integrated circuit, but the principle is directly applicable to other types of photosensing arrays, such as charge-coupled devices (CCD's), and other semiconductor materials.     

Mosfet fabrication using ion beam nitridation

Ion beam nitridation has been suggested as an alternative to the conventional local oxidation process which is used in the fabrication of most metal-oxide-semiconductor (MOS) integrated circuits. The implantation of 2 keV nitrogen ions in doses of up to 8 x 10¹⁷ cm^-2 results in the formation of a silicon nitride layer approximately 10 nm thick. Herein we describe the electrical characteristics of n-channel silicon gate metal-oxide-semiconductor-field-effect-transistors (MOSFETs) fabricated using this modified local oxidation process, and compare them to devices fabricated simultaneously but using the conventional local oxidation technology. The effective device channel lengths and widths are determined from the electrical characteristics of devices with mask (ideal) dimensions of 4, 6, 8 or 10 μm. The ion beam nitrided devices exhibit a significant reduction in the lateral oxidation effect. A 1.3 μm increase in channel width relative to conventional processing is observed for the ion beam nitrided devices with a 690 mm thick field oxide. On the other hand, fixed oxide charge densities are found to increase by a factor of about two due to the nitrogen implantation, and device channel mobilities are reduced by about 25%.     

Photosensing arrays with improved spatial resolution

The spatial resolution obtainable in a photosensing array used for optical imaging may be limited by the diffusion of photogenerated carriers within a uniformly doped semiconductor even if other components of the optical system are optimized and scattered light is reduced. A technique has been developed to improve the spatial resolution for critical applications by incorporating subsurface electric fields that accelerate the photogenerated carriers toward or away from the surface so that the carriers are prevented from diffusing to distant photosensing elements. The subsurface fields are obtained by incorporating suitable dopant concentration gradients into the structure. In one structure fabricated the subsurface field was formed by using a heavily doped buried layer and a lightly doped epitaxial film over a lightly doped substrate, all of the same conductivity type. This structure is compatible with the incorporation of other semiconductor devices in the same monolithic substrate. The technique has been applied to an array of photodiodes in a silicon integrated circuit, but the principle is directly applicable to other types of photosensing arrays, such as charge-coupled devices (CCD's), and other semiconductor materials.     

A vertically integrated dynamic RAM-cell: Buried bit line memory cell with floating transfer layer

A charge injection device has been realized in which charge can be injected on to an MOS-capacitor from a buried layer via an isolated transfer layer. The cell is positioned vertically between word and bit line. LOCOS (local oxidation) is used to isolate the cells and (deep) ion implantation to realize the buried bit line and transfer layer. This isolation prevents carriers from diffusing to neighbouring cells and hence preserves stored information. The device physics has been analysed using simulation programs and bipolar modelling. It is shown that this device can be used as a dynamic RAM-cell of extreme simplicity and potentially small cell size compared to conventional DRAM cells.     

Integration of High Aspect Ratio Tapered Silicon Via for Silicon Carrier Fabrication

This paper provides a detailed overview of silicon carrier-based packaging for 3-D system in packaging application. In this work the various critical process modules that play a vital role in the integration and fabrication of silicon carrier with high aspect ratio tapered through-silicon interconnections have been explained and discussed with experimental data. A method of fabricating tapered deep silicon via in a three-step approach has been developed and characterized which controls via depth, sidewall profile, and surface roughness effectively. A low-temperature dielectric deposition process is also developed that has minimum residual stress and good dielectric coverage on the via sidewall. The above processes were then integrated with back-end processes like seed metallization, copper electroplating, chemical mechanical polishing, and wafer thinning to realize a fully integrated silicon carrier fabrication technology. The silicon carriers were finally assembled and tested for through silicon interconnection.      

Vertical n-p-n bipolar transistors fabricated on buried oxide SOI

Vertical n-p-n bipolar transistors have been fabricated in silicon-on-insulator (SOI) films prepared by buried oxide implantation. Electrical device characteristics are shown to be comparable to those obtained on devices fabricated in bulk silicon, indicating no significant degradation owing to the buried oxide layer. Dielectric isolation in excess of 10¹¹Ω.cm and µ 3 × 10⁶V/cm is measured.     

Self-Replication of Deeply Buried Doped Silicon Structures,which Remotely Control the Etching Process: A New Method for Forming a Silicon Pattern from the Bottom Up

A typical microstructuring process utilizes photolithographic masks to create arbitrary patterns on silicon substrates in a top-down approach. Herein, a new, bottom-up microstructuring method is reported, which enables the patterning of n-doped silicon substrates to be performed without the need for application of etch-masks or stencils during the etching process. Instead, the structuring process developed herein involves a simple alkaline etching performed under illumination and is remotely controlled by the p-doped micro-sized implants, buried beneath a homogeneous n-doped layer at depths of 0.25 to 1 µm. The microstructuring is realized because the buried implants act upon illumination as micro-sized photovoltaic cells, which generate a flux of electrons and increase the negative surface charge in areas above the implants. The locally increased surface charge causes a local protection of the native silicon oxide layer from alkaline etching, which ultimately leads to the microstructuring of the substrate. In this way, substrates having at their top a thick layer of homogeneously n-doped silicon can be structured, reducing the need for costly, time-consuming photolithography steps.