一种新颖的数模转换器静态参数内建自测试方法

提出了一种新颖的数模转换器（DAC）静态参数内建自测试（BIST）方法。该方法采用斜坡信号发生器和两个参考电压作为标准信号源和误差极限电压,测试DAC的四个主要的静态参数：失调误差（offset）,增益误差（gain error）,积分非线性误差（INL ）和微分非线性误差（DNL ）,有效地节省了参考源的数目。静态参数计算的优化以及测试器件的共享使得BIST电路所占芯片面积大大减小。仿真结果表明该方法是一种简单的测试DAC静态误差的内建自测试结构。     

一种基于直方图的ADC静态参数内建自测试设计方案

本文提出了一种基于直方图（Histogram）的内建自测试（BIST）结构来测试ADC的静态参数,包括偏移误差（OffsetError）、增益误差（GainError）、积分非线性（INL）和微分非线性（DNL）．BIST体系结构主要包括波形生成控制器、一个基于DDS的数字正弦发生器、一个数字三角波发生器和一个CPU核．三角波信号被用来作为激励信号,经过数字三角波发生器和DAC转换而成．这种ADC内建自测试方案可以通过编程实现重配置,主要包括ADC精度（与待测AI）C有关）、激励信号波形类型、频率和初始相位．整个BIST通过FPGA开发板来实现,实验结果表明此BIST结构可以有效测试ADC的静态参数．     

内建自测试技术（BIST）的测试产生和响应压缩方法

本文分析了内建自测试技术(BIST)的测试产生和响应压缩的各种方法和结构,并提出了适用于层次化自测试结构的BIST测试产生和响应压缩方法。     

一种嵌入式RAM的BIST设计

本文分析了嵌入式RAM的传统测试方法和内建自测试(BIST)方法,提出了一种新的BI ST设计方案,该设计方案具有测试生成快,节约测试成本等优点.     

数字VLSI电路测试技术-BIST方案

分析了数字VLSI电路的传统测试手段及其存在问题,通过对比的方法,讨论了内建自测试(BIST)技术及其优点,简介了多芯片组件(MCM)内建自测试的目标、设计和测试方案。     

基于BIST的编译码器IP核测试

介绍了用于IP核测试的内建自测试方法（BIST）和面向测试的IP核设计方法,指出基于IP核的系统芯片（SOC）的测试、验证以及相关性测试具有较大难度,传统的测试和验证方法均难以满足。以编译码器IP核为例,说明了基于BIST的编译码器IP核测试的基本实现原理和具体实现过程,通过加入测试外壳实现了对IP核的访问、隔离和控制,提高了IP核的可测性。     

一款雷达信号处理SOC芯片的存储器内建自测试设计

内建自测试(BIST)为嵌入式存储器提供了一种有效的测试方法.详细介绍了存储器故障类型及内建自测试常用的March算法和ROM算法.在一款雷达信号处理SOC芯片中BIST被采用作为芯片内嵌RAM和ROM的可测试性设计的解决方案.利用BIST原理成功地为芯片内部5块RAM和2块ROM设计了自测试电路,并在芯片的实际测试过程中成功完成对存储器的测试并证明内嵌存储器不存在故障.     

基于LFSR优化的BIST低功耗设计

在BIST(内建自测试)过程中,线性反馈移位寄存器作为测试矢量生成器,为保障故障覆盖率,会产生很长的测试矢量,从而消耗了大量功耗。在分析BIST结构和功耗模型的基础上,针对test-per-scan和test-per-clock两大BIST类型,介绍了几种基于LFSR(线性反馈移位寄存器)优化的低功耗BIST测试方法,设计和改进可测性设计电路,研究合理的测试策略和测试矢量生成技术,实现测试低功耗要求。     

基于LFSR优化的BIST低功耗设计

在BIST(内建自测试)过程中,线性反馈移位寄存器作为测试矢量生成器,为保障故障覆盖率,会产生很长的测试矢量,从而消耗了大量功耗.在分析BIST结构和功耗模型的基础上,针对test-per-scan和test-per-clock两大BIST类型,介绍了几种基于LFSR(线性反馈移位寄存器)优化的低功耗BIST测试方法,设计和改进可测性设计电路,研究合理的测试策略和测试矢量生成技术,实现测试低功耗要求.     

新型IDDT测试的BIST测试生成器设计

内建自测试(BIST)是一种有效降低测试开销的技术,在瞬态电流测试中得到了应用。本文给出了一种新型的瞬态电流测试BIST测试生成器设计方案,该设计可以产生所需要的测试向量对,同时具有硬件开销小的优点。     

一种基于受控LFSR的内建自测试结构及其测试矢量生成

本文提出了一种基于受控线性反馈移位寄存器（LFSR）进行内建自测试的结构及其测试矢量生成方法。使用受控LFSR可以跳过伪随机测试序列中对故障覆盖率没有贡献的测试矢量，众而达到减少测试矢量长度，缩短测试时间的目的。     

A new on-chip digital BIST for analog-to-digital converters

A fully digital built-in self-test (BIST) for analog-to-digital converters is presented in this paper. This test circuit is capable of measuring the DNL, INL, offset error and gain error, and mainly consists of several registers and some digital subtracters. The main advantage of this BIST is the ability to test DNL and INL for all codes in the digital domain, which in turn eliminates the necessity of calibration. On the other hand, some parts of the analog-to-digital converter with minor modifications are used in the BIST simultaneously. This also reduces the area overhead and the cost of the test. The proposed BIST structure presents a compromise between test accuracy, area overhead and test cost. The BIST circuitry has been designed using Mitel CMOS 1.5 μm technology. The simulation results of the test show that it can be applied to medium resolution analog-to-digital converters or high resolution pipelined analog-to-digital converters. The presented BIST shows satisfactory results for a nine-bit pipe-lined analog-to-digital converter.     

Allocation Techniques for Reducing BIST Area Overhead of Data Paths

Built-in self-test (BIST) techniques modify functional hardware so that a chip has the capability to test itself. A prime concern in using BIST is the area overhead due to the modification of normal registers to BIST registers. This paper proposes register and interconnect assignment techniques that address the BIST area overhead issue during high-level synthesis. A minimal intrusion BIST methodology is employed where a subset of the functional registers are modified to be BIST registers. Depending on the BIST functions performed (test pattern generation and/or test response compression) and the concurrency of the functions, four types of BIST registers with varying costs are used. Data path allocation techniques are presented that (1) maximize the sharing of BIST registers between modules, and (2) minimize the number of expensive BIST registers that are essential for minimal intrusion BIST of a data path. The designs synthesized by our techniques have the same number of functional modules and registers as those synthesized using traditional approaches but require significantly lower BIST area overhead.     

Low-cost test technique using a new RF BIST circuit for 4.5-5.5 GHz low noise amplifiers

This paper presents a low-cost test technique using a new RF Built-In Self-Test (BIST) circuit for 4.5-5.5 GHz low noise amplifiers (LNAs). The test technique measures input impedance, voltage gain, noise figure, input return loss and output signal-to-noise ratio of the LNA. The BIST circuit is designed using 0.18 μm SiGe technology. The BIST circuit contains test amplifier and RF peak detectors. The complete measurement set-up contains LNA with BIST circuit, external RF source, RF relays, 50 Ω load impedance, and a DC voltmeter. The test technique utilizes output DC voltage measurements and these measured values are translated to the LNA specifications such as input impedance and gain through the developed equations. The technique is simple and inexpensive.     

Deterministic Built-in Pattern Generation for Sequential Circuits

We present a new pattern generation approach for deterministic built-in self testing (BIST) of sequential circuits. Our approach is based on precomputed test sequences, and is especially suited to sequential circuits that contain a large number of flip-flops but relatively few controllable primary inputs. Such circuits, often encountered as embedded cores and as filters for digital signal processing, are difficult to test and require long test sequences. We show that statistical encoding of precomputed test sequences can be combined with low-cost pattern decoding to provide deterministic BIST with practical levels of overhead. Optimal Huffman codes and near-optimal Comma codes are especially useful for test set encoding. This approach exploits recent advances in automatic test pattern generation for sequential circuits and, unlike other BIST schemes, does not require access to a gate-level model of the circuit under test. It can be easily automated and integrated with design automation tools. Experimental results for the ISCAS 89 benchmark circuits show that the proposed method provides higher fault coverage than pseudorandom testing with shorter test application time and low to moderate hardware overhead.     

An ADC BIST with on-chip ramp generator

This work presents built-in self-test (BIST) techniques for the production testing of mixed signal circuits. The special test strategy for the typical mixed-signal component analog-to-digital converter (ADC) is discussed. The traditional test for such mixed-signal components can be completed through a DSP-based mixed-signal tester with an arbitrary waveform generator and a signal digitizer, but such a test is very costly and time consuming. Hence, a BIST strategy based on an on chip ramp generator (OCRG) is proposed in this work for testing ADC. This BIST method has an advantage testing ADC without DAC to overcome area overhead. This BIST method realizes the test controller, test pattern generation and output response analyser at the aspect of the on-chip circuitry. The demonstration of the proposed BIST is given through various simulation results in the last parts of this work.     

一种超前进位加法器的新颖BIST架构

针对超前时进位加法器（CLA），提出了一种高效的BIST架构。这种新的架构结合了确定性测试和伪随机测试的优点，并避免了各自的短处。同时，还提出了一个测试向量集，并充分利用了CLA加法器内部结构的规整性，向量集规模较小，便于片内集成。最后，提出了一种计算特征值的新方法。