一种新的可编程、可扩展的Hamming神经网络

提出了一种新的可编程、可扩展Hamming神经网络。它采用电流镜计算待识模式与标准模式的匹配度。然后,通过电流型排序电路进行匹配度的排序操作并输出识别结果。该Hamming神经网络中的标准模式模板是可编程的,以满足不同场合的应用要求。另外,该网络芯片在规模上可以很容易地进行扩展,这较大地提高了该处理芯片应用的灵活性。由于网络电路中模拟部分完全采用电流型电路,使其可完全直接采用标准数字CMOS工艺进行制作,并易于模/数混合集成。已经采用单层金属、单层多晶的2pm N阱标准数字CMOS工艺成功地制作了该Hamming网络中的核心单元电路芯片,测试结果表明,该核心单元电路芯片的性能很好,完全可以满足处理器的性能要求。     

一种用于复杂模式分类的电流型Hamming神经网络

本文结合手写体数字识别，讨论了一种用Ｈａｍｍｉｎｇ神经网络实现复杂模式分类的方法．文中提出了模式分解，分级模板匹配及模糊匹配技术及其电流型ＶＬＳＩ的实现，并着重论述了一种高精度，低复杂度，结构灵活的电流型ｋ－ＷＴＡ的实现．     

一种新的可编程、可扩展的Hamming神经网络

提出了一种新的可编程、可扩展Ｈａｍｍｉｎｇ神经网络．它采用电流镜计算待识模式与标准模式的匹配度．然后,通过电流型排序电路进行匹配度的排序操作并输出识别结果．该Ｈａｍ－ｍｉｎｇ神经网络中的标准模式模板是可编程的,以满足不同场合的应用要求．另外,该网络芯片在规模上可以很容易地进行扩展,这较大地提高了该处理芯片应用的灵活性．由于网络电路中模拟部分完全采用电流型电路,使其可完全直接采用标准数字ＣＭＯＳ工艺进行制作,并易于模／数混合集成．已经采用单层金属、单层多晶的２μｍＮ阱标准数字ＣＭＯＳ工艺成功地制作了该Ｈａｍ     

一种可编程Hamming神经网络特征提取器

根据Hamming神经网络的工作原理提出了一种可用于手写体数字识别的电流型可编程局部结构特征提取电路．该特征提取器的模板不仅是可编程的，它可根据不同的需要来随时更改模板的内容以适应不同的情况，而且其特征合并的方式也是可配置的，它可根据不同的需要把所需的特征合并成不同的特征类别．对于该可编程特征的电路模拟以及用单层多晶、双层金属1.2μm数字CMOS工艺所制作的实验芯片的测试表明该电路能很好地完成特征提取的功能．     

神经网络求解逆运算问题的能力

用正运算方法求解逆运算问题是一值得重视的思想。本文分析了反馈型神经网络在解计算问题方面所具有的这一独特性质。利用这一概念可用模拟电路的神经网络构成一些崭新的高速运算器。本文给出三个实例，其一是由乘法运算构成除法器；其二是由矩阵参数求逆矩阵问题；其三是用简单的求余数运算组成其逆运算器，即解中国余数定理网络。这种网络的特点是以简单的正运算方法完成复杂的逆运算，使设计变得简单，在一些情况下可省去传统逆运算所需的许多参数，同时使运算器的运用范围大大增加。此外，该神经网络是用模拟电路实现，因而适用于高速实时处理。本文提出的思想在解决大量线性和非线性束逆运算问题中有着普遍的意义。     

跨导线性MOCCII电路实现

本文提出了一种由跨导线性环电路和双极型多端输出的电流镜构成的MOCCⅡ(多端输出的第二代电流传输器)的实现电路。文中详细分析了该电路的工作原理，并给出了实验结果。该电路具有频带宽、电压传输和电流传输精度高、结构简单、易于实现及成本低廉且实用性好的特点。     

一种改进的高分辨精度的CMOS电流型排序电路

提出了一种改进的高分辨精度的CMOS电流型排序电路.该电路不需要偏置信号,简化了系统设计.其电路结构简单,便于扩展.利用平均值电路、减法电路、WTA电路和控制电路,可以使该排序电路在大输入电流下依然保持高性能.它已经采用0.8μm标准CMOS工艺成功制作.芯片面积为2.38mm×2.00mm(核心电路面积仅为1.12mm×0.52mm).测试结果表明该排序电路动态范围大、分辨精度高、准确度好、功耗低,可以广泛地应用于中值滤波、模式识别、神经网络、模糊逻辑等信号处理领域,具有很高的应用价值.     

一种新的高性能开关电容排序电路

本文首次提出了一种高性能的开关电流型排序电路．它采用开关电流镜跟踪／保持输入信号，通过全对称的ＷＴＡ（Ｗｉｎｎｅｒ－Ｔａｋｅ－Ａｌ）电路网络求最大，最后分时输出排序结果．该电路结构简单、灵活，规模易扩展．ＰＳＰＩＣＥ模拟结果表明，该电路的输出电流相对于输入电流的偏差小，最大偏差为５μＡ；排序电路有较高的分辨精度，在５μＡ以内．由于采用开关电流技术，该电路完全同数字ＣＭＯＳ工艺相兼容，易于ＶＬＳＩ实现     

一种改进的高分辨精度的CMOS电流型排序电路

提出了一种改进的高分辨精度的CMOS电流型排序电路.该电路不需要偏置信号,简化了系统设计.其电路结构简单,便于扩展.利用平均值电路、减法电路、WTA电路和控制电路,可以使该排序电路在大输入电流下依然保持高性能.它已经采用0.8μm标准CMOS工艺成功制作.芯片面积为2.38mm×2.00mm(核心电路面积仅为1.12mm×0.52mm).测试结果表明该排序电路动态范围大、分辨精度高、准确度好、功耗低,可以广泛地应用于中值滤波、模式识别、神经网络、模糊逻辑等信号处理领域,具有很高的应用价值.     

一种新的高性能开关电流排序电路

本文首次提出了一种高性能的开关电流型排序电路．它采用开关电流镜跟踪／保持输入信号，通过全对称的ＷＴＡ（Ｗｉｎｎｅｒ－Ｔａｋｅ－Ａｌ）电路网络求最大，最后分时输出排序结果．该电路结构简单、灵活，规模易扩展．ＰＳＰＩＣＥ模拟结果表明，该电路的输出电流相对于输入电流的偏差小，最大偏差为５μＡ；排序电路有较高的分辨精度，在５μＡ以内．由于采用开关电流技术，该电路完全同数字ＣＭＯＳ工艺相兼容，易于ＶＬＳＩ实现     

A Current-Mode Hysteretic Winner-take-all Network, with Excitatory and Inhibitory Coupling

Winner-take-all (WTA) circuits are commonly used in a wide variety of applications. One of the most used current-mode WTA designs is the one originally proposed by Lazzaro et al. [1]. Several extensions to this design have been suggested in the past. In this paper we present a variant of this current-mode WTA circuit, containing all of the enhancements previously proposed, together with new additional modifications that endow it with interesting hysteretic and lateral inhibition and excitation properties. We compare the performance of this WTA circuit to the original WTA design, providing experimental data obtained from a VLSI chip containing both types of circuits, designed using closely matched layouts. We derive analytically the response properties of the circuit's lateral diffusion network, pointing out the differences to previously proposed diffusion networks, and present experimental data confirming the theoretical predictions. We also describe application domains that can best exploit these types of hysteretic WTA circuits.     

一种用于模式识别的新型开关电流Hamming神经网络

本文首次提出了一种用于模式识别的新型开关电流Ｈａｍｍｉｎｇ神经网络，它采用电流镜计算待识模式与标准模式的匹配度，然后，通过开关电流型排序电路进行匹配度的比较并输出识别结果，该Ｈａｍｍｉｎｇ神经网络可以按匹配度大小的顺序依次输出匹配度以及相应的标准模式，这将十分有利于改善系统的性能同时，该Ｈａｍｍｉｎｇ网络还可以进行绝对拒识和相对拒识的判断，这大大地提高了系统的可靠性，通过ＰＳＰＩＣＥ模拟，结果表明     

Current-Mode First-Order Allpass Filter Employing Single Current Operational Amplifier

A current-mode first-order allpass filter configuration is proposed. The presented circuit uses a single current operational amplifier (COA), a resistor and a capacitor, which are of minimum number. High output impedance of the proposed filter enables the circuit to be cascaded without additional buffers. The proposed circuit is insensitive to parasitic input capacitances and input resistances due to internally grounded input terminals of COA. It does not impose any component matching constraint in analog signal processing circuits. Non-ideal effects of COA to the first-order allpass network are also investigated. To demonstrate the performance of the proposed filter a new current-mode quadrature oscillator is given as an application example. The theoretical results are verified with PSPICE simulations using a new realization of fully differential CMOS COA.     

Design, implementation and evaluation of a high-speed integratedHamming neural classifier

This paper describes a fixed-weight Hamming binary neural classifier chip suitable for applications where high-speed operation is required. The circuit uses switched current-mode techniques throughout and achieves classification in one forward pass through the network. The chip was realized in 2.4-μm n-well CMOS technology and was designed to recognize the integers 0-9. It achieved a classification rate of 10 MHz without any observable tendency to misclassification or instability     

一种改进的高精度电流型排序电路

提出了一种改进的高精度电流型排序电路.它的结构复杂性仅为O(N),便于扩展;动态范围大;它是自适应的,工作点由输入电流确定,故不需要偏置信号,这对作为通用器件使用的排序电路来说是很重要的.通过利用平均值电路、减法电路、WTA电路和控制电路,可以使该电路在大输入电流下依然保持高性能.HSPICE模拟表明该电路具有高准确性、高精度、低功耗的特点.它能用标准数字CMOS工艺来实现,可以被应用于很多领域,具有很高的应用价值.     

一种改进的高精度电流型排序电路

提出了一种改进的高精度电流型排序电路 .它的结构复杂性仅为 O(N) ,便于扩展 ;动态范围大 ;它是自适应的 ,工作点由输入电流确定 ,故不需要偏置信号 ,这对作为通用器件使用的排序电路来说是很重要的 .通过利用平均值电路、减法电路、WTA电路和控制电路 ,可以使该电路在大输入电流下依然保持高性能 .HSPICE模拟表明该电路具有高准确性、高精度、低功耗的特点 .它能用标准数字 CMOS工艺来实现 ,可以被应用于很多领域 ,具有很高的应用价值 .     

Single-electron winner-take-all network

A winner-take-all (WTA) single-electron neuron is developed for the first time. This new single-electron circuit is proposed in order to implement a WTA neural network with lateral inhibition architecture. An expression for the neuron's activation function is presented. Furthermore, a dot pattern recognition task is successfully performed by the implemented network considering effects such as offset charges and co-tunnelling.     

High Precision Image Centroid Computation via an Adaptive K-Winner-Take-all Circuit in Conjunction with a Dynamic Element Matching Algorithm for Star Tracking Applications

An approach for implementing a high precision image target centroid—center of mass (COM) detection system via an adaptive K-winner-take-all (WTA) circuit in conjunction with a 2-D dynamic element matching (DEM) algorithm implementation for image sensor arrays is proposed. The proposed system outputs a high precision COM location of the most salient target in a programmable active region of the field of view (FOV) for star tracking purposes and is suitable for real time applications. The system allows target selection and locking with multiple targets tracking capability. This solution utilizes the separability property of the COM, and therefore reduces the computational complexity by utilizing 1-D circuits for the computation. The DEM algorithm, commonly used in ADC and DAC circuits, allows reducing the required WTA circuit precision to 5–6 bits, while still achieving a high output precision. Simulation results prove the concept and demonstrate the high precision COM result. In addition, a possible low-level hardware implementation is described.     

Insensitive current-mode universal filter with minimum componentsusing dual-output current conveyors

A novel universal current-mode active filter with four inputs and one output is presented, which contains only three dual-output current conveyors. Two grounded capacitors and two grounded resistors. The circuit is very advantageous from an integration point of view. The proposed active filter realises all filter responses without any matching conditions at high impedance output and has low passive and active sensitivities     

Realization of current-mode SC-CNN-based Chua’s circuit

A current-mode State-Controlled Cellular Neural Network (SC-CNN) cell based on current conveyors (CCIIs) and multi-output current conveyors (MOCCII) is presented in this paper. Different from the voltage-mode SC-CNN cell whose state variable is voltage signal, the current-mode SC-CNN cell takes current signal as its state variable. A current-mode SC-CNN-based chaotic circuit is developed by using the suitable connection of three current-mode SC-CNN cells. When compared with the existing voltage-mode chaotic circuits, the proposed current-mode chaotic circuit can operate at higher frequency ranges. In addition to this, state currents can be directly obtained at high impedance outputs of MOCCIIs. Furthermore, all elements in this circuit are grounded, thus it is very suitable for integrated circuit (IC) fabrication. Pspice simulations are given to demonstrate the dynamical behaviors of the proposed circuit and its high frequency performance.