Fully integrated CMOS nano-particle assembly circuit for biological detections

Recently, along with the booming of research and production of CMOS Integrated Bio-sensing System, selective assembly of organic nano-particles on the on-chip electrodes, which serves for specific bio-sensing and detection purposes, is in high demand in areas like biological analysis and detection, DNA probing and surveying systems and etc. In this paper, a fully integrated bio-circuit targeting at electrical selective assembly of charged nano-particles is proposed and designed in SMIC 0.18 μm CMOS mixed signal process. The proposed circuit integrates the 16 pixels of 19 μm × 19 μm electrode array, counter electrode, potentiostat circuit, digital decoding circuit, as well as control logics on a single chip, and provides a rail-to-rail range of assembling voltage, a potential resolution of 8 bit, and a maximal assembling current up to 459 μA, biased at a current of 1 μA. Meanwhile, a novel electrode-reuse scheme is also proposed to further simplify the architecture and save chip area as well, without degrading the functionalities. Experimental results from on-chip selective assembly of 50 nm polystyrene nano-particles are included and discussed to verify the feasibility of the proposed circuits.     

Current-mode CMOS multiplier/divider circuit operating in linear/saturation regions

A CMOS current-mode analog multiplier/divider circuit is presented. It is suited to standard CMOS fabrication and can be successfully employed in a wide range of analog signal processing applications. Measurement results for a 0.5 μm CMOS test chip prototype verify the approach employed. The circuit consumes 120 μW using a single supply voltage of 1.5 V and requires a silicon area of 150 × 140 μm.     

CMOS micro-heater design for direct integration of carbon nanotubes

Carbon nanotubes (CNTs) are nanomaterials that exhibit many remarkable electrical, mechanical and thermal properties, which can be exploited in various smart sensing applications by integrating them in standard CMOS processes. However, such integration technique is challenging since CMOS does not tolerate high temperatures required for local CNT synthesis. This work involves designing power efficient CMOS micro-heaters that can generate CNT growth temperature (~ 900 °C) in a post-CMOS CNT fabrication step, while maintaining CMOS compatible temperature (< 300 °C) in the microsystem. One suitable metal interconnect layer and a polysilicon layer available in AMS 0.18 μm CMOS technology have been used to design and simulate the micro-heaters. This paper proposes and compares six different optimal micro-heater designs alongside their thermal and thermomechanical analysis using multiphysics simulation software, ANSYS. Feasibility of implementing the designed micro-heaters in a real chip is discussed based on the analysis. Required CMOS post processing steps for the designed micro-heaters are also discussed. The promising results are expected to lead the way for successful implementation of carbon nanotube based sensors in a commercial CMOS process.     

CMOS silicon avalanche photodiodes for NIR light detection: a survey

This paper surveys recent research on CMOS silicon avalanche photodiodes (SiAPD) and presents the design of a SiAPD based photoreceiver dedicated to near-infrared spectroscopy (NIRS) application. Near-infrared spectroscopy provides an inexpensive, non-invasive, and portable means to image brain function, and is one of the most efficient diagnostic techniques of different neurological diseases. In NIRS system, brain tissue is penetrated by near-infrared (NIR) radiation and the reflected signal is captured by a photodiode. Since the reflected NIR signal has very low amplitude, SiAPD is a better choice than regular photodiode for NIR signal detection due to SiAPD`s ability to amplify the photo generated signal by avalanche multiplication. Design requirements of using CMOS SiAPDs for NIR light detection are discussed, and the challenges of fabricating SiAPDs using standard CMOS process are addressed. Performances of state-of-the-art CMOS SiAPDs with different device structures are summarized and compared. The efficacy of the proposed SiAPD based photoreceiver is confirmed by post layout simulation. Finally, the SiAPD and its associated circuits has been implemented in one chip using 0.35 μm standard CMOS technology for an integrated NIRS system.     

An active device based wide tuning range CMOS transconductor

A CMOS transconductor for wide tuning range filter application is presented. The linear transconductor is designed based on the flipped-voltage follower (FVF) circuit and can work in the weak, moderate, and strong inversion regions to maximize the transconductance tuning range. The transconductance tuning can be achieved by changing the bias current of the active resistor, and a ratio of 28 is obtained. The transconductor was evaluated by using TSMC 0.18 μm CMOS process, and the total harmonic distortion (THD) of −56 dB can be obtained by giving a 12 MHz 0.4 Vpp input swing signal. In the design, the maximum power consumption is 2 mW with the transconductance of 1.1 mS under a 1.8 V supply voltage.     

Electronically tunable CMOS class-AB output stage

A new technique for CMOS class-AB output stages is introduced in this Letter. The technique uses a master–slave configuration of a complementary common-source output stage. It offers the advantage that the quiescent and minimum currents of the output stage can be independently tuned. The effectiveness of the proposed technique was verified by simulations using a standard n-well 0.18 μm CMOS process with 1 V supply voltage. A voltage buffer, that includes the proposed output stage, is able to drive a capacitive load of 0.5 nF obtaining −63 dB total harmonic distortion. The topology features also power efficiency of about 63% for a pure resistive output load equal to 50 Ω.     

A high-speed sample-and-hold circuit based on CMOS transmission lines

We introduce the design of a high-speed sample-and-hold circuit (SHC) based on spatial sampling with CMOS transmission lines (TLs). Signal propagation analysis shows that periodically loaded CMOS TLs exhibit filter properties, which cause attenuation and deformation of signal pulses. Nevertheless, the dispersion effects on clock pulse propagation are minimal since clock lines are short, much shorter than the meandered input-signal line. Design considerations on clock pulse generator, sampling switches, and charge amplifiers are presented. Compared with other CMOS approaches, the proposed SHC generates clock pulses on chip and avoids clock jitter difficulties. The SHC is implemented in a 0.13 μm digital CMOS process with standard on-chip coplanar waveguides (CPW) as signal and clock pulse propagation TLs, silicon N-type field effect transistors (NFET) as sampling switches, and high-frequency charge amplifiers for charge amplification. Clock pulse signals of ~50 ps width with ~17 ps fall edge are generated on-chip. Simulation analysis with Cadence Spectre shows that a sampling rate of 20 Giga-sample/s with a 25 dB spurious free dynamic range (SFDR) can be achieved. With shorter clock pulses, both sampling rate and SFDR can be improved in future design.     

Fully integrated dual-band VCOs with power controlled by body voltage in 130 nm CMOS/SOI for multi-standard applications

In this paper, the design of two VCOs for wireless multi-standard applications is presented. The oscillation frequencies are 5.2 and 3.3 GHz. These circuits have been produced using CMOS/SOI technology, with body voltage to control power consumption and phase noise performance. A new architecture for multi-standard applications is proposed. Five standards are covered by these structures: GSM (900 MHz), GPS (1.5 GHz), DCS (1.8 GHz), Bluetooth (2.45 GHz) and 802.11 a (5.8 GHz). The tuning range can vary from 2.45 to 5.8 GHz for the first VCO and from 850 MHz to 1.9 GHz for the second by using frequency divider. The main idea is to use only two MOS varactors to cover the entire frequency span. The first one is needed to get the matched frequency variation and the second to adjust the oscillation frequency. Such VCOs can be made thanks to CMOS/SOI technology advantages, high-Q passives and body voltage biasing that allow current change and power dissipation in the VCO core. These circuits were produced with a view to producing a single VCO covering all these standards. Switched resonators were therefore studied. At a frequency offset of 100 kHz, the single side band phase noise measurements were −89 and −93 dBc/Hz at 5.2 and 3.6 GHz respectively.     

Design and simulation of integrated inductors on porous silicon in CMOS-compatible processes

We present a comprehensive approach of designing on-chip inductors using a CMOS-compatible technology on a porous silicon substrate. On-chip inductors realized on standard CMOS technology on bulk silicon suffer from mediocre Q-factor values partly because of the loss created by the Si substrate at higher frequencies, in addition to the metal losses. We examine the alternative of using porous Si as a thick layer isolating the Si substrate from the metallization in an otherwise standard CMOS technology. We present theoretical designs produced with full-wave Method-of-Moments simulations, verified by measurements in standard 0.18 μm CMOS technology using Al metallization. When porous Si is introduced in that technology, the same inductor metallization produced Q-factor enhancements of the order of 50%, compared to the same inductor on bulk crystalline silicon. We also produce optimized single-ended inductor designs using Cu on porous Si, in a 0.13 μm-compatible CMOS technology. The resulting Q-factors are enhanced by a factor of 2 and reach values of 30 or more in the 2–3 GHz frequency range. Even higher quality factors can be obtained in this technology when differential designs are used.     

Clock aligner based on delay locked loop with double edge synchronization

In CMOS multistage clock buffer design, the duty-cycle of clock is liable to be changed when the clock passes through several buffer stages. The pulse-width may be changed due to unbalance of the p- and n-OS transistors in the long buffer. This paper describes a delay locked loop with double edge synchronization for use in a clock alignment process. Results of its SPICE simulation, that relate to 1.2 μm CMOS technology, shown that the duty-cycle of the multistage output pulses can be precisely adjusted to (50 ± 1)% within the operating frequency range, from 55 MHz up to 166 MHz.     

Low-power high-speed phase frequency detector based on carbon nano-tube field effect transistors

A phase frequency detector (PFD) with a very low dead zone is proposed which is based on a configuration adaptable to both CMOS or carbon nano-tube transistors (CNTFETs). In the first step the proposed configuration is designed using CMOS transistors, and then CNTFETs are substituted to improve the speed and reduce the propagation delay. The proposed PFD in addition to very low dead zone, has low power consumption and high frequency range of operation, which are achieved as a result of the elimination of the reset path. The simulation results based on 32 nm technology for CNTFET and 180 nm technology for CMOS, illustrate that CNTFET-based proposed circuit dissipates 2 µW and has frequency of operation up to 30 GHz, and the dead zone equal to 1 ps. Compared to the conventional PFD based on CMOS technology, its dead zone and power consumption are lower. In addition, the effects of blocks’ parameters including the phase detector, which affect the operation of the phase locked loop, or delay locked loop, are systematically analyzed.

     

An 8-bit, 10 kHz, 5.1 μW, 0.18 μm CMOS SAR ADC for RFID applications with sensing capabilities

An 5.1 μW, 1.8 V, 8-bit, successive approximation (SAR) analog-to-digital converter (ADC) using 10 kHz clock was designed and fabricated in a 0.18 μm CMOS technology for passive UHF radio frequency identification (RFID) applications. The ADC utilises a resistive digital to analog converter (DAC). The ADC can operate with low power consumption. The proposed comparator with cascode active load can offer large gain and can operate at a low supply voltage. The measured total power consumption is 5.1 μW at a 10 kHz input clock with a 1.8 V single supply, and 0.5 μW with 970 mV supply.     

A 60 GHz receiver front-end in 65 nm CMOS

In the past few years, the mm-wave silicon, especially 60 GHz CMOS design has experienced a transition from an obscure topic to a research hot spot. This paper presents the design of a 60 GHz receiver front-end using 65 nm CMOS technology. Initially, a heterodyne receiver front-end architecture is presented to exploit its possible compatibility with legacy systems. In order to implement the front-end, an EM simulation based methodology and the corresponding design flow are proposed. A transistor EM model, using existing compact models as core, is developed to account for the parasitic elements due to wiring stacks. A spiral inductor lumped model, based on S-parameter data from EM simulation is also derived. After the device modeling efforts, a single-stage LNA and a single-gate mixer are designed using 65 nm CMOS technology. They are characterized by EM co-simulation, and compared with the state-of-the-art. After integration, the simulated front-end achieves a conversion gain of 11.9 dB and an overall SSB noise figure of 8.2 dB, with an input return loss of −13.7 dB. It consumes 6.1 mW DC power, and its layout occupies a die area of 0.33 mm × 0.44 mm.     

Low voltage four-quadrant current multiplier: an improved topology for n-well CMOS process

An analog CMOS current multiplier building block for low voltage applications using an n-well process is presented. The multiplier equations are derived to proof its linear characteristic, and then a low voltage design is proposed. Post layout simulation in a 0.35 μm AMS CMOS process and 1.5 V supply voltage shows a THD of 0.84% at 10 MHz and a frequency response bandwidth of 140 MHz.     

A low power CMOS phase-switching prescaler for 1.8–2.4 GHz wireless communications

A divide-by-31/32 phase switching prescaler with a simple divide-by-4 multi-phase ring counter is presented. By using this divide-by-4 unit, a low power consumption is obtained while a wide range operation is maintained. Fabricated with a standard 0.18 μm CMOS technology, the prescaler can work properly from 1.8 to 3.1 GHz with a maximum current dissipation of 1.3 mA from a 1.8 V supply voltage. It can cover most of wireless communication standards in 1.8/1.9 GHz and 2.4 GHz bands.     

Low voltage CMOS fully differential current feedback amplifier with controllable 3-dB bandwidth

This paper presents a CMOS fully differential current feedback operational amplifier with controllable 3-dB bandwidth. The FDCFOA has the advantage of a wide range controllable 3-dB bandwidth (∼57–500 MHz) without changing the feedback resistance. The FDCFOA has a standby current of 320 μA. Application of the proposed FDCFOA in realizing second order low-pass filter with controllable 3-dB bandwidth is given. PSpice simulations of the FDCFOA block and its application are given using 0.25 μm CMOS technology from MOSIS and dual supply voltages ±0.75 V.     

A <Emphasis Type="Italic">G</Emphasis><Subscript><Emphasis Type="Italic">m</Emphasis></Subscript><Emphasis Type="Italic">-C</Emphasis> continuous-time analog filter for IEEE 802.11 a/b/g/n wireless LANs

A CMOS transconductor for multi-mode wireless channel selection filter is presented. The linear transconductor is designed based on the flipped-voltage follower (FVF) circuit and an active resistor to achieve the transconductance tuning. The transconductance tuning can be obtained by changing the bias current of the active resistor. A third-order Butterworth low-pass filter implemented with the transconductors was designed by TSMC 0.18-μm CMOS process. The results show that the filter can operate with the cutoff frequency of 10–20 MHz. The tuning range would be suitable for the specifications of IEEE 802.11 a/b/g/n Wireless LANs under the consideration of saving chip areas. In the design, the maximum power consumption is 13 mW with the cutoff frequency of 20 MHz under a 1.8 V supply voltage.     

An ultra-low-power CMOS symmetrical OTA for low-frequency <Emphasis Type="Italic">G</Emphasis><Subscript><Emphasis Type="Italic">m</Emphasis></Subscript>-<Emphasis Type="Italic">C</Emphasis> applications

In this paper an ultra-low-power CMOS symmetrical operational transconductance amplifier (OTA) for low-frequency G _m -C applications in weak inversion is presented. Its common mode input range and its linear input range can be made large using DC shifting and bulk-driven differential pair configuration (without using complex approaches). The symmetrical OTA was successfully verified in a standard CMOS 0.35-μm process. The measurements show an open loop gain of 61 dB and a unit gain frequency of 195 Hz with only 800 mV of power supply voltage and just 40 nW of power consumption. The transconductance is 66 nS, which is suitable for low-frequency G _m -C applications.     

A spread spectrum clock generator with a wide frequency and attenuation tuning range based on a third-order error-feedback delta-sigma modulator

In this paper, a novel design of spread-spectrum clock generator (SSCG) with a third-order error-feedback delta-sigma modulator is presented. The proposed SSCG with triangular modulation can generate clocks with center spread ratios of 0.25, 1, 1.75, 2.5, 3.5, 5% and down spread ratios of 0.5, 2, 3.5, 5, 7, 10% over a wide frequency range from 20 to 700 MHz. The SSCG is implemented on a chip using SMIC 0.13 um CMOS process. Our tests show that 11.31 dB attenuation of the EMI at 80 MHz with down spread ratio of 10% and 12.98 dB attenuation at 133.3 MHz with center spread ratio of 5% can be achieved which is in agreement with the theoretic calculation.     

A new constant-<Emphasis Type="Italic">Q</Emphasis> CMOS active inductor with applications to low-noise oscillators

This paper investigates the dependence of the quality factor of CMOS active inductors on the signal swing of the inductors and its impact on the phase noise of LC-tank oscillators employing the active inductors. A new CMOS active inductor with a nearly constant quality factor is proposed. Two 4-GHz LC oscillators with and without constant-Q active inductors have been implemented in UMC-0.13 μm 1.2 V CMOS technology and analyzed using SpectreRF from Cadence with BSIM3V3 device models. Simulation results demonstrate the phase noise of the oscillator with the constant-Q active inductor is −118dBc/Hz at 1 MHz frequency offset.