一种2.4GHzCMOS低噪声放大器的优化设计

通过对共源共栅结构的低噪声放大器的噪声和线性度的理论分析。得出该结构的放大器的噪声主要受第一级MOS管的影响。而线性度主要受第二级MOS管的影响。并由此提出一种对该电路的噪声和线性度的分别优化的方法。采用该方法设计一个基于TSMC0．25μmCMOS工艺、2．4GHz的低噪声放大器。仿真结果表明在2．4GHz下，它的噪声系数[NF]为1．15dB，增益S21为16．5dB。工作电压1．5V时，功耗为14mW，线性度IIP3为0.3dBm。     

基于0.18μm CMOS工艺的2.4/5.2GHz双频段LNA的设计

采用0.18 μm CMOS工艺,实现了双频段低噪声放大器设计.通过射频选择开关,电路可以分别工作在无线局域网标准802.11g规定的2.4 GHz和802.11a规定的5.2 GHz频段.该低噪声放大器为共源共栅结构,设计中采用了噪声阻抗和输入阻抗同时匹配的噪声优化技术.电路仿真结果表明:在2.4 GHz频段电路线性增益为15.4 dB,噪声系数为2.3 dB,1 dB压缩点为-12.5 dBm,IIP3为-4.7 dBm;5.2 GHz频段线性增益为12.5 dB,噪声系数为2.9 dB,1 dB压缩点为-11.3 dBm,IIP3为-5.5 dBm.     

电视调谐器中电阻负反馈结构的宽带低噪声放大器设计

设计了一种应用于DVB-S标准的数字电视调谐器的宽带放大器.采用电阻负反馈输入匹配结构,把交流反馈和直流偏置结合在一起,在噪声、增益和线性度方面达到了很好的性能,满足射频电视调谐器的应用需要.此低噪声放大器有约2.5 GHz的3 dB带宽,大于20 dB的电压增益,输入匹配优于-14 dB,噪声系数低于3.3 dB,IIP3在2.5 dBm之上.此LNA的输入匹配、线性度、噪声性能作了较为详细的讨论.     

一种高性能宽带直接变频射频前端设计

提出一种宽带(250 MHz~4.7 GHz)无电感BiCMOS射频前端结构,包含低噪声跨导放大器(LNTA)、带电阻无源混频器和跨阻级。低噪声跨导放大器使用了噪声和线性度消除技术,例如输入交叉耦合结构、互补输入和电流复用技术。带电阻无源混频器采用退化电阻来提高线性度。仿真结果表明, 当电源电压为3.3 V时,总电流为9.38 mA, 噪声系数为9.8 dB(SSB),电压转换增益为20 dB,输入3阶交调为+11.8 dBm。     

WLAN中带ESD保护的低噪声放大器设计

介绍了一个基于IBM0.18μmCMOS工艺,用于无线局域网(WLAN)IEEE802.11a的带ESD保护电路的低噪声放大器(LNA)。通过分析电感负反馈共源共栅放大器的输入阻抗、增益和噪声系数,以及ESD保护电路对低噪声放大器性能的影响,对该5GHz低噪声放大器进行设计和优化。测试结果表明,当电源电压为1.8V时,消耗电流为6.5mA,增益达到10dB,输入匹配达到-18dB,噪声为4.29dB,线性度IIP3为4dBm。     

宽带低噪声放大器单片微波集成电路

从行波放大器设计理论出发,研制了一款基于低噪声GaAs赝配高电子迁移率晶体管(PHEMT)工艺设计的2~20 GHz单片微波集成电路(MMIC)宽带低噪声放大器。该款放大器由九级电路构成。为了进一步提高放大器的增益,采用了一个共源场效应管和一个共栅场效应管级联的拓扑结构,每级放大器采用自偏压技术实现单电源供电。测试结果表明,本款低噪声放大器在外加+5 V工作电压下,能够在2~20 GHz频率内实现小信号增益大于16 dB,增益平坦度小于±0.5 dB,输出P-1 dB大于14 dBm,噪声系数典型值为2.5 dB,输入和输出回波损耗均小于-15 dB,工作电流仅为63 mA,低噪声放大器芯片面积为3.1 mm×1.3 mm。     

超宽带低温接收机后级低噪声放大器设计

设计了一种用于超宽频低温接收机后级放大的宽带低噪声放大器,并给出了仿真和测试结果。该低噪声放大器采用三个单片级联,并在级间加入了均衡和衰减网络对增益进行修正,使增益平坦度得到很大改善,同时对噪声等指标影响较小。最终实现的低噪声放大器在1～9GHz 频率范围内,常温噪声系数优于2dB,增益大于35dB,平坦度小于3.5dB,输入输出驻波比小于2.5,输出1dB 压缩点功率大于10dBm。     

基于GaAs pHEMT的1.0～2.4 GHz放大衰减多功能芯片

基于0.25 μm GaAs赝高电子迁移晶体管(pHEMT)工艺,研制了一种1.0～2.4 GHz的放大衰减多功能芯片,该芯片具有低噪声、高线性度和增益可数控调节等特点。电路由第一级低噪声放大器、4位数控衰减器、第二级低噪声放大器依次级联构成,同时在片上集成了TTL驱动电路。为获得较大的增益和良好的线性度,两级低噪声放大器均采用共源共栅结构(Cascode)。测试结果表明,在1.0～2.4 GHz频带范围内,该芯片基态小信号增益约为36 dB,噪声系数小于1.8 dB,输出1 dB压缩点功率大于16 dBm,增益调节范围为15 dB,调节步进1 dB,衰减RMS误差小于0.3 dB,输入输出电压驻波比小于1.5。其中放大器采用单电源+5 V供电,静态电流小于110 mA,TTL驱动电路采用-5 V供电,静态功耗小于3 mA。整个芯片的尺寸为3.5 mm×1.5 mm×0.1 mm。     

1.9GHz0.18μm CMOS低噪声放大器的设计

针对1.9GHzPHS和DECT无线接入系统的应用,提出了一种可工作于1.2V电压的基于源级电感负反馈共源共栅结构而改进的CMOS低噪声放大器,并对其电路结构、噪声及线性特性等主要性能进行分析。并与传统的低噪声放大器进行对比,该电路采用两级放大结构,通过加入电容和电感负反馈可以分别实现低功耗约束下的噪声优化和高的线性度。采用TSMC0.18μm CMOS工艺模型设计与验证,实验结果表明：该低噪声放大器能很好满足要求,且具有1.4dB的噪声系数和好的线性度,输入1dB压缩点-7.8dBm,增益11dB,功耗11mW。     

采用多级噪声抵消技术的CMOS全差分LNA设计

设计了一种用于2.4GHz RFID单芯片阅读器的CMOS低噪声放大器(LNA)。该设计采用全差分共源共栅结构和新颖的多级噪声抵消技术,不仅减小了电路的噪声而且增加了系统的线性度。芯片采用标准UMC 0.18um CMOS工艺,工作电压为1.2V时,消耗电流小于8mA,后仿真结果表明2.4GHz时,芯片达到1.69dB噪声系数,大于14.25dB功率增益以及-1.1dBm的输入三阶截点(IIP3)。设计满足单芯片阅读器低噪声,低功耗和高线性度的要求。     

A novel high dynamic range differential LNA using quartet topology

In some applications such as short-range radars, a large target can desensitize the receiver. A high dynamic range low-noise amplifier (LNA), as a key component of a transmitter/receiver module, can improve the entire system performance. This study presents a high dynamic range differential LNA that uses a differential quartet topology for the first time. The LNA shows more linearity than the conventional differential common source LNAs. For a typical 0.18 µm CMOS technology, it achieves a power gain of about 5.5 dB at 24 GHz, a low noise figure (NF) of 3.5 dB, very good linearity performance, an input-referred third-order intercept point (IIP3) of +?6.3 dBm, and an input-referred 1 dB compression point (P1dB) of ??4.5 dBm.     

Millimeter‐Wave High‐Linear CMOS Low‐Noise Amplifier Using Multiple‐Gate Transistors

A millimeter‐wave (mm‐wave) high‐linear low‐noise amplifier (LNA) is presented using a 0.18 µm standard CMOS process. To improve the linearity of mm‐wave LNAs, we adopted the multiple‐gate transistor (MGTR) topology used in the low frequency range. By using an MGTR having a different gate‐source bias at the last stage of LNAs, third‐order input intercept point (IIP3) and 1‐dB gain compression point (P_1dB) increase by 4.85 dBm and 4 dBm, respectively, without noise figure (NF) degradation. At 33 GHz, the proposed LNAs represent 9.5 dB gain, 7.13 dB NF, and 6.25 dBm IIP3.     

Erratum to: Using Improved Product-Coded Modulation Codes to Reduce the Peak-to-Average Power Ratio in Single-Carrier Frequency Division Multiple Access Systems

A new ultra-wideband common gate low noise amplifier (LNA) for 3–6 GHz WLAN and WPAN applications is presented in which a current reused noise canceling structure utilized in the first stage not only provides a suitable noise performance, but also enhances the linearity characteristics of the LNA in a power efficient manner needed by WLAN/WPAN applications. The overall structure of the proposed LNA, consisting of three stages, namely input matching common gate stage with noise canceling, gain stage, and buffer one, is designed, laid out, and analyzed in 0.18 µm RF CMOS process. The LNA has a noise figure of 3.5–3.6 dB, a high and flat power gain of 20.27 ± 0.13 dB, and input and output losses of better than ?11 and ?14 dB, respectively, over the entire frequency band of 3–5 GHz, while these parameters are 3.5 dB, 20.75 ± 0.25 dB, ?15 and ?9 dB for the frequency band of 5–6 GHz, respectively. IIP2 and IIP3 of the proposed topology are equal to 25.9 and ?1.85 dBm, respectively, at 4 GHz frequency. The proposed LNA has 15.3 mW power dissipation from a 1.8 V supply.     

A Wideband CMOS Low Noise Amplifier Employing Noise and IM2 Distortion Cancellation for a Digital TV Tuner

A wideband CMOS low noise amplifier (LNA) with single-ended input and output employing noise and IM2 distortion cancellation for a digital terrestrial and cable TV tuner is presented. By adopting a noise canceling structure combining a common source amplifier and a common gate amplifier by current amplification, the LNA obtains a low noise figure and high IIP3. IIP2 as well as IIP3 of the LNA is important in broadband systems, especially digital terrestrial and cable TV applications. Accordingly, in order to overcome the poor IIP2 performance of conventional LNAs with single-ended input and output and avoid the use of external and bulky passive transformers along with high sensitivity, an IM2 distortion cancellation technique exploiting the complementary RF performance of NMOS and PMOS while retaining thermal noise canceling is adopted in the LNA. The proposed LNA is implemented in a 0.18 $muhbox{m}$ CMOS process and achieves a power gain of 14 dB, an average noise figure of 3 dB, an IIP3 of 3 dBm, an IIP2 of 44 dBm at maximum gain, and S11 of under ${- 9}~{rm dB}$ in a frequency range from 50 MHz to 880 MHz. The power consumption is 34.8 mW at 2.2 V and the chip area is 0.16 ${rm mm}^{2}$.      

Linearization technique using bipolar transistor at 5 GHz low noise amplifier

A CMOS low noise amplifier (LNA) used in wireless communication systems, such as WLAN and CDMA, must have low noise figure, high linearity, and sufficient gain. Several techniques have been proposed to improve the linearity of CMOS LNA circuits. The proposed low noise amplifier achieves high third-order input intercept point (IIP3) using multi-gated configuration technique, by using two transistors, the first is the main CMOS transistor, and the second is bipolar transistor in TSMC 0.18 m technology. Bipolar transistor is used to cancel the third-order component from MOS transistor to fulfill high linearity operation. This work is designed and fabricated in TSMC 0.18 m CMOS process. At 5 GHz, the proposed LNA achieves a measurement results as 16 dBm of IIP3, 10.5 dB of gain, 2.1 dB of noise figure, and 8 mW of power consumption.     

Design of a capacitor cross-coupled dual-band LNA with switched current-reuse technique

This paper presents the design of a 2.5/3.5-GHz dual-band low-power and low-noise CMOS amplifier (LNA), which uses the capacitor cross-coupling technique and current-reuse method with four switches. The proposed LNA uses a single RF block and a broadband input stage, which is a key aspect for the easy reconfiguration of a dual-band LNA. Switching at the inter-stage and output allows for the selection of a different standard. The dual-band LNA attenuates the undesired interference of a broadband gain response circuit, which allows the linearity of the amplifier to be improved. The capacitor cross-coupled gm-boosting method improves the NF and reduces the current consumption. The proposed LNA employs a current-reused structure to decrease the total power consumption. The inter-stage and output switched resonators switch the LNA between the 2.5-GHz and 3.5-GHz bands. The proposed dual-band LNA optimises power consumption by the securing gain, noise figure and linearity. The simulated performance reveals gains of 16.7 dB and 19.6 dB, and noise figures of 3.04 dB and 2.63 dB at the two frequency bands, respectively. The linearity parameters of IIP3 are ?5.7 dBm at 2.5 GHz and ?9.7 dBm at 3.5 GHz. The proposed dual-band LNA consumes 5.6 mW from a 1.8 V power supply.     

一种用于地面和有线接收机的宽带低噪声放大器

提出并设计了一种用于数字电视接收调谐芯片的宽带低噪声放大器.该设计采用0.35μm SiGe BiCMOS工艺,器件的主要性能为:增益等于18.8dB,增益平坦度小于1.4dB,噪声系数小于5dB,1dB压缩点为-2dBm,输入三阶交调为8dBm.在5V供电的情况下,直流功耗为120mW.     

A Novel IP3 Boosting Technique Using Feedforward Distortion Cancellation Method for 5 GHz CMOS LNA

Low noise amplifier (LNA) in many wireless and wireline communication systems must have low noise, sufficient gain and high linearity performance. This paper presents a novel IP3 boosting technique using Feedforward Distortion Cancellation (FDC) method, that is, use an additional path to generate distortion and then cancel with the original LNA's distortion at its output. Through this technique, the IIP3 of LNA can be boosted from about 0 dBm, which is reported in most public literature to date, to +21 dBm, which is firstly reported to this day, with negligible noise degradation.     

用于SiGe HBT LNA的新型双有源偏置电路的设计

偏置工作点是影响低噪声放大器(LNA)线性度的因素之一.为了保证LNA能够更好地对信号进行线性放大,稳定的偏置工作点对于放大器来说显得尤为重要.提出了一种新型有源偏置技术,通过同时采用两个电流源为LNA提供直流偏置,以达到稳定放大器偏置工作点的目的.基于JAZZ 0.35 μm SiGe工艺,采用该新型双有源偏置技术,设计了一款LNA.在1.8～2.2 GHz频带时,放大器的增益为22.03±0.46 dB,噪声系数小于3.7dB,2.0 GHz时的输入3阶交调点(IIP3)为5 dBm,相对于传统无源偏置的LNA提高了10 dBm.仿真验证了该新型有源偏置技术对提高LNA线性度的有效性.     

A Noise Reduction and Linearity Improvement Technique for a Differential Cascode LNA

A typical common source cascode low-noise amplifier (CS-LNA) can be treated as a CS-CG two stage amplifier. In the published literature, an inductor is added at the drain of the main transistor to reduce the noise contribution of the cascode transistors. In this work, an inductor connected at the gate of the cascode transistor and capacitive cross-coupling are strategically combined to reduce the noise and the nonlinearity influences of the cascode transistors in a differential cascode CS-LNA. It uses a smaller noise reduction inductor compared with the conventional inductor based technique. It can reduce the noise, improve the linearity and also increase the voltage gain of the LNA. The proposed technique is theoretically formulated. Furthermore, as a proof of concept, a 2.2 GHz inductively degenerated CS-LNA was fabricated using TSMC 0.35 mum CMOS technology. The resulting LNA achieves 1.92 dB noise figure, 8.4 dB power gain, better than 13 dB S11, more than 30 dB isolation (S12), and -2.55 dBm IIP3, with the core fully differential LNA consuming 9 mA from a 1.8 V power supply.