Design and fabrication of multiple-valued multiplexer using negative differential resistance circuits and standard SiGe process

The design of a four-valued multiplexer using the negative differential resistance (NDR) circuit is demonstrated. The NDR circuit used in this work is made of the Si-based metal–oxide–semiconductor field-effect-transistor (MOS) and the SiGe-based heterojunction bipolar transistor (HBT). However we can obtain the NDR characteristic in its combined I–V curve by suitably arranging the MOS parameters. This novel multiplexer is made of MOS–HBT–NDR-based decoders and inverters. The fabrication is based on the standard 0.35 μm SiGe BiCMOS process.     

Multiple-valued decoder using MOS-HBT-NDR circuit

The design of a four-valued decoder based on the negative-differential- resistance (NDR) circuit is demonstrated. The presented NDR circuit is composed of a Si-based metal-oxide-semiconductor field-effect- transistor (MOS) and a SiGe-based heterojunction bipolar transistor (HBT). The fabrication of the four-valued decoder using this MOS- HBT-NDR circuit is based on the standard 0.35 mum SiGe-based BiCMOS process.     

Multiple-input logic circuit design using BiCMOS-based negative differential resistance circuits

We first propose an inverter circuit design using the negative differential resistance (NDR) circuit composed of the standard Si-based n-channel metal-oxide-semiconductor field-effect-transistor (NMOS) and SiGe-based heterojunction bipolar transistor (HBT). By suitably designing the MOS width/length parameters, we can obtain the ??-type NDR current?Cvoltage (I?CV) characteristic. Expanding the inverter circuit operation, the two-input and four-input NOR logic gates are demonstrated. Especially, the design and fabrication of the logic circuit is based on the standard SiGe BiCMOS process. Compared to the traditional NDR device like resonant tunneling diode (RTD), our MOS?CHBT?CNDR-based applications are much easier to be combined with some Si-based or SiGe-based devices on the same chip.     

Design and characterization of the negative differential resistance circuits using the CMOS and BiCMOS process

We investigate four novel negative-differential-resistance (NDR) circuits using the combination of the standard Si-based n-channel metal-oxide-semiconductor field-effect-transistor (NMOS) and SiGe-based heterojunction bipolar transistor (HBT). By suitably designing the parameters, we can obtain the Λ- or N-type current–voltage (I–V) curve. Especially, the peak current of the combined I–V curve could be easy adjusted by the external voltage. In application, we utilize the NDR circuit to design an inverter circuit based on the monostable–bistable transition logic element. The fabrication of these NDR circuits and applications could be completely implemented by the simple and standard Si-based CMOS or SiGe-based BiCMOS process without using the complex and expensive process such as metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).     

Four-valued memory circuit using three-peak MOS-NDR devices and circuits

A four-valued memory circuit using the three-peak MOS-NDR circuit as the driver and a current source as the load is demonstrated. The fabrication of the circuit is based on the standard 0.35 /spl mu/m CMOS process.     

Fabrication and application of MOS-HBT-NDR circuit using standard SiGe process

A novel negative differential resistance (NDR) circuit made of a metal-oxide-semiconductor field-effect-transistor (MOS) and a heterojunction bipolar transistor (HBT) is presented. By suitably modulating the width/length parameters of the MOS devices, the fabrication of this MOS-HBT-NDR circuit and its application to inverter design based on the standard 0.35 mum SiGe process was demonstrated     

Mixed body bias techniques with fixed V/sub t/ and I/sub ds/ generation circuits

There remains a need to improve sub-1-V CMOS VLSIs with respect to variation in transistor behavior. In this paper, to minimize variation in delay and the noise margin of the circuits in processors, we propose several mixed body bias techniques using body bias generation circuits. In these circuits, either the saturation region of the current between source and drain (I/sub ds/) or the threshold voltage (V/sub t/) of PMOS/NMOS is permanently fixed, regardless of temperature range or variation in process. A test chip that featured these body bias generation circuits was fabricated using a 130-nm CMOS process with a triple-well structure. The mixed body bias techniques which keep the I/sub ds/ of the MOS in the decoder and I/O circuits of a register file fixed and maintain the V/sub t/ of the MOS in both the memory cell and domino circuits of the register file fixed resulted in positive temperature dependence of delay from -40 /spl deg/C to 125 /spl deg/C, 85% reduction of the delay variation compared with normal body bias (NBB) at V/sub DD/ = 0.8 V. In addition, the results using these techniques show a 100-mV improvement in lower operating voltage compared with NBB at -40 /spl deg/C on a 4-kb SRAM.     

Dynamic-type CMOS four-valued logic circuits

We first briefly introduce the various kinds of basic CMOS four-valued logic circuit that can be suitably employed for circuits with clock pulses. Using these, the design of multiple-valued MAX and MIN circuits with many inputs, each of which has two quaternary figures, are developed. It is shown that the number of MOS transistors required for these circuits can be reduced in comparison to binary circuits having equivalent functions. Successful simulation results using SPICE-2 for the circuit operations are given.     

Design of monostable–bistable transition logic element using the BiCMOS-based negative differential resistance circuit

The monostable–bistable transition logic element (MOBILE) is a promising application for negative differential resistance (NDR) circuit. Previously reported MOBILE is constructed by resonant tunneling diode (RTD) that is implemented by the molecular beam epitaxy (MBE) process. However in this paper, we first propose a NDR circuit composed of standard Si-based metal–oxide–semiconductor field-effect transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT). Then we demonstrate the inverter, NAND, and NOR gate operations using this MOS–HBT–NDR-based MOBILE circuit. The great advantage of this NDR-based application is that we can implement it using the standard SiGe BiCMOS process without the need for the MBE system.     

Realization of negative differential resistance and switching devices based on copper phthalocyanine by the control of evaporation rate

We have observed, respectively, a negative differential resistance (NDR) and switching conduction in current–voltage (I–V) characteristics of organic diodes based on copper phthalocyanine (CuPc) film sandwiched between indium-tin-oxide (ITO) and aluminum (Al) by controlling the evaporation rate. The NDR effect is repeatable, which can be well controlled by sweep rate and start voltage, and the switching exhibits write-once-read-many-times (WORM) memory characteristic. The traps in the organic layer and interfacial dipole have been used to explain the NDR effect and switching conduction. This opens up potential applications for CuPc organic semiconductor in low power memory and logic circuits.     

新型恒压控制型负阻HBT的研制进展

研究了HBT产生负阻的可能机制,通过对材料结构和器件结构的特殊设计,采用常规台面HBT工艺,先后研制出3类高电流峰谷比的恒压控制型负阻HBT.超薄基区HBT的负阻特性是由超薄基区串联电阻压降调制效应造成的,在GaAs基InGaP/GaAs和AlGaAs/GaAs体系DHBT中均得到了验证.双基区和电阻栅型负阻HBT均为复合型负阻器件.双基区负阻HBT通过刻断基区,电阻栅负阻HBT通过在集电区制作基极金属形成集电区反型层,构成纵向npn与横向pnp的复合结构,由反馈结构(pnp)的集电极电流来控制主结构(npn)的基极电流从而产生负阻特性.3类负阻HBT与常规HBT在结构和工艺上兼容,兼具HBT的高速高频特性和负阻器件的双稳、自锁、节省器件的优点.     

An on-chip back-bias generator for MOS dynamic memory

An on-chip back-bias generator for 64K dynamic MOS RAM has been developed.The use of this generator achieves the goal of a single 5 V power supply part while preserving the advantages of substrate bias in n-channel MOS technology. These advantages include the elimination of substrate injection current from localized forward biasing of diodes, improved speed and power characteristics, and a larger differential data signal on the bit sense lines. The generator circuit avoids several pit-falls on on-chip V/SUB BB/ generation. The circuit pumps to a known regulated voltage. This avoids substrate drift with changes in substrate current resulting from changes in cycle time. This drift will change device characteristics and degrade storage levels. A unique two-level reference scheme avoids changes in substrate bias voltage that otherwise result from the shift in V/SUB BB/ between precharged and active memory states when memory duty cycle changes. The standby power used by the generator is only 0.74 mW.     

A 5.7–6.4GHz GaAs HBT Power Amplifier with a Gain Enhanced Bias Circuit

This paper describes the design of a 5.7–6.4GHz GaAs Heterojunction bipolar transistor (HBT) power amplifier for broadband wireless application such as wireless metropolitan area networks. A bias circuit is proposed which enhances the power gain and provides a good linearity. Using the wideband matching network tech-niques with trap circuits embedded to filter the harmonics and the diode-based linearizing techniques, a broadband power amplifier module was obtained which exhibited a gain above 28dB. This is about 1dB improvement com-pared with those normal bias circuits at a supply volt-age of 5V in the frequency range of 5.7–6.4GHz, measured with Continuous wave(CW) signals. The saturated output power was greater than 33dBm in 5.7–6.4GHz and the out-put 1dB compression point was greater than 31dBm. The phase deviation was less than 5 degrees when the output power below 33dBm. The second and third order harmonic components were also less than -45dBc and -50dBc.     

与HBT工艺兼容的新型负阻器件的研制与分析

在HBT工艺基础上,通过对器件结构的特殊设计,研制出了一类新型三端负阻器件,其恒压控制型负阻的PVCR大于800,并伴有恒流控制型负阻。通过atlas器件模拟软件进行模拟后对其物理机制进行了解释。该器件既能保持HBT高频、高速的特点,又具有负阻、双稳、自锁等特性,同时与普通台面HBT工艺兼容,易于集成,是一种具有研究和应用价值的新型负阻器件。     

HBT MMIC功率放大器的自适应线性化偏置技术

设计HBT MMIC功率放大器,偏置电路的选择对于提高功率放大器的效率和线性度至关重要.为了在效率和线性度之间取得良好折中,一个重要的方法是让HBT的偏置点随输入信号的功率变化而变化.许多文献都对这种自适应偏置技术进行了研究,然而,对于多种自适应线性化偏置电路比较和分析的文章尚未见报道.本文综合叙述了适用于HBT MMIC工艺,尺寸小、成本低的多种自适应线性化偏置电路,总结了这些偏置电路的基本工作原理,并提出了一种改进的线性化偏置电路.     

Design and implementation of a switched-current memory cell forlow-power and weak-current operations

This paper describes the design and implementation of a new switched-current (SI) memory cell for current-mode signal processing. The SI memory cell operates in a pico-to-nanoampere range. To obtain an acceptable accuracy, a procedure to reduce the negative effects of the nonideal characteristics of MOS transistor in SI circuits is proposed and implemented. A prototype circuit including the new SI memory cell associated with optical sensors has been fabricated with a 0.35-μm n-well technology. The test results show that, in a range of 0.5 pA to 15 nA, the error rate of current memorization/reproduction in the proposed SI memory is below 1% and the power dissipation is in a range of nanowatts or below     

Compact multiple-valued multiplexers using negative differentialresistance devices

Quantum electronic devices with negative differential resistance (NDR) characteristics have been used to design compact multiplexers. These multiplexers may be used either as analog multiplexers where the signal on a single select line selects one out of four analog inputs, or as four-valued logic multiplexers where the select line and the input lines represent one of four quantized signal values and the output line corresponds to the selected input. Any four-valued logic function can be implemented using only four-valued multiplexers (also known as T-gates), and this T-gate uses just 13 devices (transistors) as compared to 44 devices in CMOS. The design of the T-gate was done using a combination of resonant tunneling diodes (RTD's) and heterojunction bipolar transistors (HBT's) with the folded I-V characteristic (NDR characteristic) of the RTD's providing the compact logic implementation and the HBT's providing the gain and isolation. The application of the same design principles to the design of T-gates using other NDR devices such as resonant tunneling hot electron transistors (RHET's) and resonant tunneling bipolar transistors (RTBT's) is also demonstrated     

一种低功耗的锂离子电池保护电路的设计

设计了一种适用于CMOS工艺的锂离子电池充放电保护电路,采用工作在亚阈值区的电路结构,使电路具有超低消耗电流驱动、高精度检测电压等特点。通过取样电路、基准电路和偏置电路设计的改进,保护电路功耗较低并且在较低电压下可以正常工作。模拟结果表明,该电路实现了基本的电池保护功能并在功耗方面达到了设计的目标。     

基于新型量子逻辑门库的最优NCV三量子电路快速综合算法

许多量子电路综合算法由于指数级时间与空间复杂度,只能用可逆逻辑门综合3量子逻辑电路,仅有少数算法实现用量子非门,控制非门,控制V门与控制V⁺门(NCV)综合3量子逻辑电路,主要方法是将电路综合问题简化为四值逻辑综合问题.本文提出用NCV门构造新型量子逻辑门库,该库与NCV门库在综合最优3量子逻辑电路上等价,因此又可将四值逻辑综合问题进一步简化为更易求解的二值逻辑综合问题,使用基于完备Hash函数的3量子电路快速综合算法,快速生成全部最优的3量子逻辑电路,以最小代价综合电路的平均速度是目前最好结果Maslov 2007的近127倍.