可演化TMR容错表决电路的设计研究

在高温、辐射等恶劣环境下微电子设备的可靠性要求越来越高,利用演化硬件(EHW)原理,将EHW技术与三模块冗余(TMR)容错技术相结合,在FPGA上实现可演化的TMR表决电路,使硬件本身具有自我重构和自修复能力,大大提高了系统的可靠性.     

面向航空环境的多时钟单粒子翻转故障注入方法

随着新型电子器件越来越多地被机载航电设备所采用,单粒子翻转(Single Event Upset, SEU)故障已经成为影响航空飞行安全的重大隐患。首先,针对由于单粒子翻转故障的随机性,该文对不同时刻发生的单粒子翻转故障引入了多时钟控制,构建了SEU故障注入测试系统。然后模拟真实情况下单粒子效应引发的多时间点故障,研究了单粒子效应对基于FPGA构成的时序电路的影响,并在线统计了被测模块的失效数据和失效率。实验结果表明,对于基于FPGA构建容错电路,采用多时钟沿三模冗余(Triple Modular Redundancy, TMR) 加固技术可比传统TMR技术提高约1.86倍的抗SEU性能;该多时钟SEU故障注入测试系统可以快速、准确、低成本地实现单粒子翻转故障测试,从而验证了SEU加固技术的有效性。     

一种基于ALU单元的改进的三模冗余结构设计

对于传统的三模冗余结构(TMR),当其中两个模块发生失效时可能出现功能相同的情况,造成三模冗余失效.为了解决这一问题,针对ALU模块的结构特点提出了对操作数编码的方法到达三个模块差异化的效果,采用此方法后能100%的消除TMR同功能失效的问题,同时此方法相对于模块的差异化设计成本更低,效果更明显.     

可重构硬件芯片级故障定位与自主修复方法

 外部集中控制的可重构硬件容错系统,其重构控制算法复杂、重构时间开销大,且存在单点失效问题.本文研究芯片级分布式在线自主容错技术,提出了能够实现芯片级自修复的新型可重构硬件细胞阵列结构,阐述了互连资源的在线故障定位和自主修复方法.设计了功能细胞电路和容错开关块电路,采用分段定位法检测互连资源中多路器故障和连线开路故障,通过重配置布线和线移位操作分别实现多路器与连线故障自修复.以4位串并乘法器电路为例进行实验验证,分析了容错设计的硬件开销与时间开销,实验结果表明新方案的容错时间短、资源利用率高.     

冗余磁盘阵列的故障容错分析

本文在介绍冗余磁盘阵列(RAID)的故障容错机理之后,着重研究了设备故障对RAID系统可靠性的影响.其平均持续正常工作时间和系统在线修复设备故障容许的平均间隔时间的计算结果表明,只要在一定的容许时间内替换或修复故障磁盘,系统可保持持续正常工作状态.     

三余度数字式伺服电机控制器的设计

介绍了一种基于DSP和FPGA的三余度数字式伺服电机控制器,该控制器采用"3+2"冗余方案进行设计,即数字控制部分采用三模冗余容错方式,功率驱动部分采用双余度驱动控制,其中数字控制部分的三模冗余容错工作模式具备故障检测、隔离、系统降级运行能力;驱动部分使用两套独立的功率驱动电路驱动交流同步电机的两路绕组,当判断一路驱动电路出现问题时,可通过软件操作使用另外一路功率驱动电路进行控制。     

检错冗余模型及剩余码检错算法研究

针对星上系统三模冗余(TMR)容错模型资源开销大的问题,提出了一种具有普适性的检错冗余模型.在此模型下分析了基于剩余码的检错算法,使用该方法可根据检错性能需求灵活调整资源开销.适用于解决星上系统所面临的单粒子翻转(SEU)问题.算法仿真表明,对于乘、加等基本运算以及FFT等复杂运算,剩余码检错算法均能够取得较好的检错效果.通过选择合适的剩余码码长,剩余码检错算法能够以允许范围内的资源开销代价获得满足需求的检错性能.     

基于FPGA的三模冗余容错技术研究

基于SRAM的FPGA对于空间粒子辐射非常敏感,很容易产生软故障,所以对基于FPGA的电子系统采取容错措施以防止此类故障的出现是非常重要的。三模冗余（TMR）方法以其实现的简单性和效果的可靠性而被广泛用于对单粒子翻转（SEU）进行容错处理。但传统TMR方法存在系统硬件资源消耗较多且功耗较大等问题。总结了传统TMR方法存在的问题,分析了一些近年来出现的改进的TMR方法的优劣,针对其存在问题指出了改进策略,并展望了TMR技术的发展趋势。     

两种系统级单粒子效应容错方法性能仿真分析

基于VLSI的信息处理系统空间应用时容易遭受单粒子翻转效应(SEU:Single Event Upset)的影响.基于结构冗余的三模冗余(TMR:Three Module Redundancy)和基于信息冗余的错误检纠错(EDAC:Error Detection and Correction)是两种常见的系统级抗单粒子翻转的容错方法,被广泛应用于空间信息处理系统中.从可靠性改进、存储资源占用、硬件实现代价以及实现延时等四个方面,对两种方法进行了性能分析和仿真实验.性能分析和仿真实验结果表明,EDAC方法适合应用于基本数据宽度较大、存储资源受限、实时性要求不高的应用中,结构TMR方法适合应用于基本数据宽度较小、存储资源充足、实时性要求较高的应用中.     

DICE型D触发器三模冗余实现及辐照实验验证

分析了三模冗余(TMR)型D触发器和双互锁存储单元(DICE)型D触发器各自的优点和缺点,基于三模冗余和双互锁存储单元技术的(TMRDICE)相融合方法,设计实现了基于双互锁存储单元技术的三模冗余D触发器。从电路级研究了TMRDICE型D触发器抗单粒子翻转的性能,与其他传统类型电路结构的D触发器进行了抗单粒子翻转性能比较,并通过电路仿真和辐照实验进行了验证。仿真结果表明,TMRDICE型D触发器的抗单粒子翻转性能明显优于传统的普通D触发器、TMR型D触发器和DICE型D触发器。辐照实验结果表明,TMRDICE型D触发器具有最小的翻转截面。     

Optimal Placement of Spare Modules in a Cascaded Chain

A class of redundant cascaded chains with i.i.d. modules is considered in which recovery from a failure takes place by replacing the faulty module by a spare module. The complexity of the reconfiguration process depends upon the location of spare modules in the cascade. This paper deals with the question of optimally placing the spare modules in order to minimize the s-expected recovery time (down time) of the system. Exact analysis is carried out for cascades with one and two spare modules and an approximate analysis is given for three or more spares. Even though exact analysis does not seem to be practical in the general case, the symmetry of spare module positions in the special cases discussed here and linearity of the system suggest that one might expect the optimal positions to be symmetric in general. Because of this symmetry, one can reduce the number of variables to be considered in the general case, however, some inaccuracies might be introduced.     

基于VXI总线的某计算机模块测试系统实现

针对某两种计算机模块的测试需求,组建及开发了基于VXI总线的某计算机模块测试设备和测试系统软件。该系统采用VXI总线实现多串口通信,对底层测量仪器的测量数据进行采集,同时将采集到的数据进行计算,从而快速、准确地得到各种参数,并将结果保存,方便后期数据查询。通过自动测试和交互测试2种方式可以对模块各个部分进行全面测试。该测试设备的研制对实现某计算机模块大批量生产的快速检测,提高模块参数的测量精度和效率,对返修件定位提供了有利工具。     

A Fault Tolerant Approach for FPGA Embedded Processors Based on Runtime Partial Reconfiguration

The ever increasing adoption of field programmable devices in various application domains for building complex embedded systems based on FPGA processors along with the reliability issues having emerged for FPGA devices built with the latest nanometer technologies, have raised the need for new fault tolerant techniques in order to improve dependability and extend system lifetime. In addition, the runtime partial reconfiguration technology highly mature in the modern FPGA families along with the availability of unused programmable resources in most FPGA designs provide new and interesting opportunities to build advanced fault tolerance mechanisms. In this paper, we exploit the dynamic reconfiguration potential of today’s FPGA architectures and the advances in the related design support tools and we propose a fault-tolerant approach for FPGA embedded processors based on runtime partial reconfiguration. According to the proposed methodology, the processor core is partitioned into reconfigurable modules and each module is duplicated to implement a concurrent error detection mechanism. Precompiled configurations containing spare resources are generated for each duplicated module and are used to repair at runtime the defective modules. Also, a fault tolerance scheme for the proxy logic of the reconfigurable modules, which cannot move in the alternative configurations along with the rest logic, is proposed. Moreover, a compression method for the alternative partial bitstreams, which significantly reduces the high storage space requirements of the proposed approach, is presented. Two different hardware decompression schemes have been implemented in a Virtex-5 device and compared in terms of area overhead and decompression latency. Furthermore, a thorough examination has been performed, regarding how the percentage of the spare resources and their allocation in the reconfigurable regions affect the compression efficiency and the processor performance. Finally, the proposed approach has been demonstrated in three different components – ALU, multiplier-accumulator, and instruction-fetch unit – of an open-source embedded processor.     

数字雷达阵面T/ R 组件故障定位方法研究

数字T/ R 组件是新型数字雷达阵面的关键组成部件,其符合性判别与故障定位是数字雷达阵面批产集成联试的重要环节。结合数字雷达阵面集成联试实际情况,开展了集成手段与方法的研究,分析了T/ R 组件在阵面联试中的故障模式,确定了判断准则,实现了组件判故的自动化处理,形成了典型数据异常故障的排故流程与方法,完善了组件调试平台控制措施,为新型数字雷达阵面工程量产提供了实用参考。     

多任务下的系统实时检测

本文根据ＳＴＤ总线控制系统的要求和环境，以ＲＡＭ的故障模型为基础，提出了基于时间控制及模块的系统故是实时检测设计，重点研究了暂时故障的处理问题。由各模块检测算法构成的检测任务灵活方便，实用性强，能处理文中提出的所有故障。     

基于闭环集成运放的模拟电路模块级软故障诊断

基于斜率故障模型,提出了一种诊断模拟电路中基于闭环集成运算放大器的模块级软故障的字典法.在由闭环运放组成的模拟电路中,通过对电路以闭环运放及与其输入直接相连的元件看作一个整体划分模块,对各个模块中的任一元件或进行宏模型替代之后的运放等效电路,利用电路中的两节点电压增量计算出的斜率作为统一故障特征,建立故障字典,实现电路中相应模块包含的运放和所有元件的软故障诊断.给出了运放的等效宏模型和模块级软故障的诊断步骤,并用仿真实例证明了该诊断方法的有效性.     

高速公路汽车追尾预警系统设计

针对高速公路汽车追尾预警系统进行了总体结构设计,将系统分为主控模块、信息处理模块、电源模块、报警模块、制动模块、存储模块以及通信模块7个部分。从硬件的角度对各个模块进行了功能分析、器件的选型。最终从软件的角度,对整个流程进行了设计。设计该系统以期达到降低交通事故发生率,体现经济性和实用性原则。     

基于ATmega16的便携式机车信号发生器的研制

便携式机车速度信号发生器能够模拟机车运行参数,准确输出速度变化信号,便于检修工作人员及时排查故障点,提高检修效率.该设备采用手持式结构,主集成了脉冲形成模块、功率放大模块、故障诊断、信息显示及输入输出等功能模块,形成一套完善的系统,能够独立,精确模拟机车速度信号,并能方便,有效,可靠的检测出机车速度信号相关的线路状况,本文详细叙述了该信号发生器的研发方案、系统构成和主要功能特点,并介绍了其现场使用情况.     

A linear-time algorithm to find modules of fault trees

A module of a fault tree is a subtree whose terminal events do not occur elsewhere in the tree. Modules, which are independent subtrees, can be used to reduce the computational cost of basic operations on fault trees, such as the computation of the probability of the root event or the computation of the minimal cut sets. This paper presents a linear time algorithm to detect modules of a fault tree, coherent or not, that is derived from the Tarjan algorithm to find strongly connected components of a graph. The authors show, on a benchmark of real fault trees, that their method detects modules of trees with several hundred gates and events within few milliseconds on a personal computer     

Modular design [From the Editor's Bench]

For many years now, there has been a move toward modular design. Modular equipment is often cheaper to maintain. If you need to only test ten modules to determine why a piece of equipment is not working, you can save a lot of money on fault analysis. If repairing the piece of equipment means throwing out the bad module and slotting in its replacement, you can save a lot of money on repairs too. Though you may decry the waste of all the good parts still left in the broken module, you are likely to feel that overall modularity has served you well.